Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 45c0a7ee0e5bdfd32e90db11d0deb49b4c256ae9 / . / configs / MPC8548CDS_defconfig
blob: 535b65e5fce99b992e1871f678e4dd1b0992aecf [file] [log] [blame]
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900[diff] [blame]1CONFIG_PPC=y
Tom Rini0c4dded2022-03-30 09:30:15 -0400[diff] [blame]2CONFIG_SYS_IMMR=0xE0000000
Tom Rini07edfae2018-02-03 12:10:38 -0500[diff] [blame]3CONFIG_SYS_TEXT_BASE=0xFFF80000
Tom Rinie25a03a2021-11-01 12:19:22 +0000[diff] [blame]4CONFIG_SYS_MALLOC_LEN=0x100000
Tom Rini5cd7ece2019-11-18 20:02:10 -0500[diff] [blame]5CONFIG_ENV_SIZE=0x2000
6CONFIG_ENV_SECT_SIZE=0x20000
Tom Rini84610272020-07-28 08:46:52 -0400[diff] [blame]7CONFIG_DEFAULT_DEVICE_TREE="mpc8548cds"
Tom Rini4b2fcb32022-04-08 13:36:51 -0400[diff] [blame]8CONFIG_ENV_ADDR=0xFFF60000
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900[diff] [blame]9CONFIG_MPC85xx=y
Simon Glass9fdc0de2017-05-17 03:25:15 -0600[diff] [blame]10# CONFIG_CMD_ERRATA is not set
Masahiro Yamadad3ae6782014-07-30 14:08:14 +0900[diff] [blame]11CONFIG_TARGET_MPC8548CDS=y
Tom Rini527ded82019-09-23 11:47:37 -0400[diff] [blame]12CONFIG_MPC85XX_HAVE_RESET_VECTOR=y
Tom Rinia7fa9762022-06-15 12:03:45 -0400[diff] [blame]13CONFIG_ENABLE_36BIT_PHYS=y
Tom Rini7485ebf62022-06-20 08:07:45 -0400[diff] [blame]14CONFIG_PCIE1=y
Simon Glasse3ee2fb2016-02-22 22:55:43 -0700[diff] [blame]15CONFIG_OF_BOARD_SETUP=y
16CONFIG_OF_STDOUT_VIA_ALIAS=y
Tom Rini8c70baa2021-12-14 13:36:40 -0500[diff] [blame]17CONFIG_DYNAMIC_SYS_CLK_FREQ=y
Heiko Schocher0b368b12016-06-07 08:31:14 +0200[diff] [blame]18CONFIG_BOOTDELAY=10
Tom Rini5ddf1722021-11-10 09:11:40 -0500[diff] [blame]19CONFIG_USE_BOOTCOMMAND=y
20CONFIG_BOOTCOMMAND="setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off console=$consoledev,$baudrate $othbootargs;tftp $loadaddr $bootfile;tftp $fdtaddr $fdtfile;bootm $loadaddr - $fdtaddr"
Adam Ford10541762018-07-29 13:13:29 -0500[diff] [blame]21# CONFIG_MISC_INIT_R is not set
Tom Rini4abdf142021-08-17 17:59:41 -0400[diff] [blame]22CONFIG_ID_EEPROM=y
Tom Rinid209eda2022-08-10 10:29:27 -0400[diff] [blame]23CONFIG_SYS_I2C_EEPROM_CCID=y
Tom Rinif852e732016-04-21 21:37:19 -0400[diff] [blame]24CONFIG_HUSH_PARSER=y
Tom Rinicbfa1392022-05-11 17:38:09 -0400[diff] [blame]25CONFIG_SYS_PBSIZE=276
Tuomas Tynkkynen28d56bd2017-10-08 21:48:01 +0300[diff] [blame]26CONFIG_CMD_IMLS=y
Tom Rinifaed5672021-08-17 17:59:45 -0400[diff] [blame]27CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2
Tom Rini0f2dcb92016-04-22 16:41:25 -0400[diff] [blame]28CONFIG_CMD_I2C=y
Simon Glassc88a09a2017-08-04 16:34:34 -0600[diff] [blame]29CONFIG_CMD_PCI=y
Tom Rini256aa742017-06-19 09:47:40 -0400[diff] [blame]30CONFIG_CMD_DHCP=y
Tom Rini1c47c4a2022-02-25 11:19:50 -0500[diff] [blame]31CONFIG_BOOTP_BOOTFILESIZE=y
Tom Rini1d9ac832016-04-24 17:29:26 -0400[diff] [blame]32CONFIG_CMD_MII=y
Tom Rini0f2dcb92016-04-22 16:41:25 -0400[diff] [blame]33CONFIG_CMD_PING=y
Simon Glass027608e2017-05-17 03:25:25 -0600[diff] [blame]34# CONFIG_CMD_HASH is not set
Tom Rini527ded82019-09-23 11:47:37 -0400[diff] [blame]35CONFIG_OF_CONTROL=y
Adam Ford710966e2020-07-03 06:48:56 -0500[diff] [blame]36CONFIG_ENV_OVERWRITE=y
Tom Rini5fb860c2022-02-25 11:19:48 -0500[diff] [blame]37CONFIG_USE_BOOTFILE=y
38CONFIG_BOOTFILE="8548cds/uImage.uboot"
Tom Rinife586752022-03-11 09:12:07 -0500[diff] [blame]39CONFIG_USE_ETHPRIME=y
40CONFIG_ETHPRIME="eTSEC0"
Tom Rini56184602022-02-25 11:19:53 -0500[diff] [blame]41CONFIG_CHIP_SELECTS_PER_CTRL=2
Tom Rini468c2d52021-08-21 13:50:18 -0400[diff] [blame]42CONFIG_DDR_ECC=y
43CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
Tom Rinif7eed202021-11-13 18:10:40 -0500[diff] [blame]44CONFIG_SYS_BR0_PRELIM_BOOL=y
45CONFIG_SYS_BR0_PRELIM=0xFF801001
46CONFIG_SYS_OR0_PRELIM=0xFF806E65
47CONFIG_SYS_BR1_PRELIM_BOOL=y
48CONFIG_SYS_BR1_PRELIM=0xFF001001
49CONFIG_SYS_OR1_PRELIM=0xFF806E65
50CONFIG_SYS_BR2_PRELIM_BOOL=y
51CONFIG_SYS_BR2_PRELIM=0xF0001861
52CONFIG_SYS_OR2_PRELIM=0xFC006901
53CONFIG_SYS_BR3_PRELIM_BOOL=y
54CONFIG_SYS_BR3_PRELIM=0xF8000801
55CONFIG_SYS_OR3_PRELIM=0xFFF00FF7
Tom Rini3eea5772020-05-08 09:08:39 -0400[diff] [blame]56CONFIG_DM_I2C=y
Tom Rinib1b13072021-08-18 23:12:37 -0400[diff] [blame]57CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
Tom Rinibe94c762021-08-18 23:12:35 -0400[diff] [blame]58CONFIG_SYS_I2C_FSL=y
Tom Rinifaed5672021-08-17 17:59:45 -0400[diff] [blame]59CONFIG_SYS_I2C_EEPROM_ADDR=0x57
Tom Rini9834b902017-03-13 13:48:42 -0400[diff] [blame]60# CONFIG_MMC is not set
Masahiro Yamada8cea9b52017-02-11 22:43:54 +0900[diff] [blame]61CONFIG_MTD_NOR_FLASH=y
Adam Ford76da1b22018-10-14 15:10:50 -0500[diff] [blame]62CONFIG_FLASH_CFI_DRIVER=y
Tom Rini302bd672022-07-23 13:04:55 -0400[diff] [blame]63CONFIG_SYS_FLASH_EMPTY_INFO=y
Adam Ford76da1b22018-10-14 15:10:50 -0500[diff] [blame]64CONFIG_SYS_FLASH_CFI=y
Tom Rinid38112c2022-07-23 13:05:04 -0400[diff] [blame]65CONFIG_SYS_MAX_FLASH_SECT=128
Patrick Delaunay1576abf2022-01-04 14:24:00 +0100[diff] [blame]66CONFIG_SYS_MAX_FLASH_BANKS=2
Tom Rini5d154192020-04-24 15:35:53 -0400[diff] [blame]67CONFIG_PHY_ATHEROS=y
68CONFIG_PHY_BROADCOM=y
69CONFIG_PHY_DAVICOM=y
70CONFIG_PHY_LXT=y
Mario Sixf504d1a2018-04-27 14:52:21 +0200[diff] [blame]71CONFIG_PHY_MARVELL=y
Tom Rini5d154192020-04-24 15:35:53 -0400[diff] [blame]72CONFIG_PHY_NATSEMI=y
73CONFIG_PHY_REALTEK=y
74CONFIG_PHY_SMSC=y
75CONFIG_PHY_VITESSE=y
Tom Rinica22e962017-08-07 22:00:34 -0400[diff] [blame]76CONFIG_PHY_GIGE=y
Simon Glass9008a5b2015-08-19 09:33:43 -0600[diff] [blame]77CONFIG_E1000=y
Tom Rini527ded82019-09-23 11:47:37 -0400[diff] [blame]78CONFIG_MII=y
79CONFIG_TSEC_ENET=y
Hou Zhiqiang3f7f8e62019-08-27 11:05:29 +0000[diff] [blame]80CONFIG_DM_PCI_COMPAT=y
81CONFIG_PCIE_FSL=y
Tom Rinie69ba982018-03-06 19:02:27 -0500[diff] [blame]82CONFIG_CONS_INDEX=2
Thomas Choua6cec012015-11-19 21:48:14 +0800[diff] [blame]83CONFIG_SYS_NS16550=y