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git01.mediatek.com / filogic / uboot / 4531d7c0ae12d2d014edb5b8fbc43c41e953cdf6 / . / dts / upstream / Bindings / phy / qcom,sc8280xp-qmp-ufs-phy.yaml
blob: f9cfbd0b2de6c4d7096fbd8658431ad68c18c4f2 [file] [log] [blame]
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-ufs-phy.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm QMP PHY controller (UFS, SC8280XP)
8
9maintainers:
10 - Vinod Koul <vkoul@kernel.org>
11
12description:
13 The QMP PHY controller supports physical layer functionality for a number of
14 controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
15
16properties:
17 compatible:
18 enum:
19 - qcom,msm8996-qmp-ufs-phy
20 - qcom,msm8998-qmp-ufs-phy
21 - qcom,sa8775p-qmp-ufs-phy
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]22 - qcom,sc7180-qmp-ufs-phy
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]23 - qcom,sc7280-qmp-ufs-phy
24 - qcom,sc8180x-qmp-ufs-phy
25 - qcom,sc8280xp-qmp-ufs-phy
26 - qcom,sdm845-qmp-ufs-phy
27 - qcom,sm6115-qmp-ufs-phy
28 - qcom,sm6125-qmp-ufs-phy
29 - qcom,sm6350-qmp-ufs-phy
30 - qcom,sm7150-qmp-ufs-phy
31 - qcom,sm8150-qmp-ufs-phy
32 - qcom,sm8250-qmp-ufs-phy
33 - qcom,sm8350-qmp-ufs-phy
34 - qcom,sm8450-qmp-ufs-phy
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]35 - qcom,sm8475-qmp-ufs-phy
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]36 - qcom,sm8550-qmp-ufs-phy
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]37 - qcom,sm8650-qmp-ufs-phy
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]38
39 reg:
40 maxItems: 1
41
42 clocks:
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]43 minItems: 2
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]44 maxItems: 3
45
46 clock-names:
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]47 minItems: 2
48 maxItems: 3
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]49
50 power-domains:
51 maxItems: 1
52
53 resets:
54 maxItems: 1
55
56 reset-names:
57 items:
58 - const: ufsphy
59
60 vdda-phy-supply: true
61
62 vdda-pll-supply: true
63
64 "#clock-cells":
65 const: 1
66
67 "#phy-cells":
68 const: 0
69
70required:
71 - compatible
72 - reg
73 - clocks
74 - clock-names
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]75 - resets
76 - reset-names
77 - vdda-phy-supply
78 - vdda-pll-supply
79 - "#phy-cells"
80
81allOf:
82 - if:
83 properties:
84 compatible:
85 contains:
86 enum:
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]87 - qcom,msm8998-qmp-ufs-phy
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]88 - qcom,sa8775p-qmp-ufs-phy
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]89 - qcom,sc7180-qmp-ufs-phy
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]90 - qcom,sc7280-qmp-ufs-phy
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]91 - qcom,sc8180x-qmp-ufs-phy
92 - qcom,sc8280xp-qmp-ufs-phy
93 - qcom,sdm845-qmp-ufs-phy
94 - qcom,sm6115-qmp-ufs-phy
95 - qcom,sm6125-qmp-ufs-phy
96 - qcom,sm6350-qmp-ufs-phy
97 - qcom,sm7150-qmp-ufs-phy
98 - qcom,sm8150-qmp-ufs-phy
99 - qcom,sm8250-qmp-ufs-phy
100 - qcom,sm8350-qmp-ufs-phy
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]101 - qcom,sm8450-qmp-ufs-phy
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]102 - qcom,sm8475-qmp-ufs-phy
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]103 - qcom,sm8550-qmp-ufs-phy
Tom Rini93743d22024-04-01 09:08:13 -0400[diff] [blame]104 - qcom,sm8650-qmp-ufs-phy
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]105 then:
106 properties:
107 clocks:
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]108 minItems: 3
109 maxItems: 3
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]110 clock-names:
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]111 items:
112 - const: ref
113 - const: ref_aux
114 - const: qref
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]115
116 - if:
117 properties:
118 compatible:
119 contains:
120 enum:
121 - qcom,msm8996-qmp-ufs-phy
122 then:
123 properties:
124 clocks:
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]125 minItems: 2
126 maxItems: 2
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]127 clock-names:
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]128 items:
129 - const: ref
130 - const: qref
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]131
Tom Rini762f85b2024-07-20 11:15:10 -0600[diff] [blame]132 - if:
133 properties:
134 compatible:
135 contains:
136 enum:
137 - qcom,msm8996-qmp-ufs-phy
138 - qcom,msm8998-qmp-ufs-phy
139 then:
140 properties:
141 power-domains:
142 false
143 else:
144 required:
145 - power-domains
146
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]147additionalProperties: false
148
149examples:
150 - |
151 #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]152 #include <dt-bindings/clock/qcom,rpmh.h>
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]153
154 ufs_mem_phy: phy@1d87000 {
155 compatible = "qcom,sc8280xp-qmp-ufs-phy";
156 reg = <0x01d87000 0x1000>;
157
Tom Rini6bb92fc2024-05-20 09:54:58 -0600[diff] [blame]158 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
159 <&gcc GCC_UFS_REF_CLKREF_CLK>;
160
161 clock-names = "ref", "ref_aux", "qref";
Tom Rini53633a82024-02-29 12:33:36 -0500[diff] [blame]162
163 power-domains = <&gcc UFS_PHY_GDSC>;
164
165 resets = <&ufs_mem_hc 0>;
166 reset-names = "ufsphy";
167
168 vdda-phy-supply = <&vreg_l6b>;
169 vdda-pll-supply = <&vreg_l3b>;
170
171 #phy-cells = <0>;
172 };