wdenk | f806271 | 2005-01-09 23:16:25 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Basic I2C functions |
| 3 | * |
| 4 | * Copyright (c) 2004 Texas Instruments |
| 5 | * |
| 6 | * This package is free software; you can redistribute it and/or |
| 7 | * modify it under the terms of the license found in the file |
| 8 | * named COPYING that should have accompanied this file. |
| 9 | * |
| 10 | * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR |
| 11 | * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED |
| 12 | * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. |
| 13 | * |
| 14 | * Author: Jian Zhang jzhang@ti.com, Texas Instruments |
| 15 | * |
| 16 | * Copyright (c) 2003 Wolfgang Denk, wd@denx.de |
| 17 | * Rewritten to fit into the current U-Boot framework |
| 18 | * |
| 19 | * Adapted for OMAP2420 I2C, r-woodruff2@ti.com |
| 20 | * |
Lubomir Popov | 4d98efd | 2013-06-01 06:44:38 +0000 | [diff] [blame] | 21 | * Copyright (c) 2013 Lubomir Popov <lpopov@mm-sol.com>, MM Solutions |
| 22 | * New i2c_read, i2c_write and i2c_probe functions, tested on OMAP4 |
| 23 | * (4430/60/70), OMAP5 (5430) and AM335X (3359); should work on older |
| 24 | * OMAPs and derivatives as well. The only anticipated exception would |
| 25 | * be the OMAP2420, which shall require driver modification. |
| 26 | * - Rewritten i2c_read to operate correctly with all types of chips |
| 27 | * (old function could not read consistent data from some I2C slaves). |
| 28 | * - Optimized i2c_write. |
| 29 | * - New i2c_probe, performs write access vs read. The old probe could |
| 30 | * hang the system under certain conditions (e.g. unconfigured pads). |
| 31 | * - The read/write/probe functions try to identify unconfigured bus. |
| 32 | * - Status functions now read irqstatus_raw as per TRM guidelines |
| 33 | * (except for OMAP243X and OMAP34XX). |
| 34 | * - Driver now supports up to I2C5 (OMAP5). |
Hannes Petermaier | d588505 | 2014-02-03 21:22:18 +0100 | [diff] [blame] | 35 | * |
Hannes Schmelzer | 7935f03 | 2015-05-28 15:41:12 +0200 | [diff] [blame] | 36 | * Copyright (c) 2014 Hannes Schmelzer <oe5hpm@oevsv.at>, B&R |
Hannes Petermaier | d588505 | 2014-02-03 21:22:18 +0100 | [diff] [blame] | 37 | * - Added support for set_speed |
| 38 | * |
wdenk | f806271 | 2005-01-09 23:16:25 +0000 | [diff] [blame] | 39 | */ |
| 40 | |
| 41 | #include <common.h> |
Mugunthan V N | 560037b | 2016-07-18 15:11:01 +0530 | [diff] [blame] | 42 | #include <dm.h> |
Heiko Schocher | f53f2b8 | 2013-10-22 11:03:18 +0200 | [diff] [blame] | 43 | #include <i2c.h> |
Simon Glass | 0f2af88 | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 44 | #include <log.h> |
Simon Glass | dbd7954 | 2020-05-10 11:40:11 -0600 | [diff] [blame] | 45 | #include <linux/delay.h> |
wdenk | cb99da5 | 2005-01-12 00:15:14 +0000 | [diff] [blame] | 46 | |
wdenk | f806271 | 2005-01-09 23:16:25 +0000 | [diff] [blame] | 47 | #include <asm/io.h> |
Jean-Jacques Hiblot | 58994fc | 2018-12-07 14:50:42 +0100 | [diff] [blame] | 48 | #include <asm/omap_i2c.h> |
wdenk | f806271 | 2005-01-09 23:16:25 +0000 | [diff] [blame] | 49 | |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 50 | /* |
| 51 | * Provide access to architecture-specific I2C header files for platforms |
| 52 | * that are NOT yet solely relying on CONFIG_DM_I2C, CONFIG_OF_CONTROL, and |
| 53 | * the defaults provided in 'omap24xx_i2c.h' for all U-Boot stages where I2C |
| 54 | * access is desired. |
| 55 | */ |
| 56 | #ifndef CONFIG_ARCH_K3 |
| 57 | #include <asm/arch/i2c.h> |
| 58 | #endif |
| 59 | |
Steve Sakoman | 10acc71 | 2010-06-12 06:42:57 -0700 | [diff] [blame] | 60 | #include "omap24xx_i2c.h" |
| 61 | |
Tom Rini | 49fbf67 | 2012-02-20 18:49:16 +0000 | [diff] [blame] | 62 | #define I2C_TIMEOUT 1000 |
Steve Sakoman | e2bdc13 | 2010-07-19 20:31:55 -0700 | [diff] [blame] | 63 | |
Lubomir Popov | 4d98efd | 2013-06-01 06:44:38 +0000 | [diff] [blame] | 64 | /* Absolutely safe for status update at 100 kHz I2C: */ |
| 65 | #define I2C_WAIT 200 |
| 66 | |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 67 | enum { |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 68 | OMAP_I2C_REV_REG = 0, /* Only on IP V1 (OMAP34XX) */ |
| 69 | OMAP_I2C_IE_REG, /* Only on IP V1 (OMAP34XX) */ |
| 70 | OMAP_I2C_STAT_REG, |
| 71 | OMAP_I2C_WE_REG, |
| 72 | OMAP_I2C_SYSS_REG, |
| 73 | OMAP_I2C_BUF_REG, |
| 74 | OMAP_I2C_CNT_REG, |
| 75 | OMAP_I2C_DATA_REG, |
| 76 | OMAP_I2C_SYSC_REG, |
| 77 | OMAP_I2C_CON_REG, |
| 78 | OMAP_I2C_OA_REG, |
| 79 | OMAP_I2C_SA_REG, |
| 80 | OMAP_I2C_PSC_REG, |
| 81 | OMAP_I2C_SCLL_REG, |
| 82 | OMAP_I2C_SCLH_REG, |
| 83 | OMAP_I2C_SYSTEST_REG, |
| 84 | OMAP_I2C_BUFSTAT_REG, |
| 85 | /* Only on IP V2 (OMAP4430, etc.) */ |
| 86 | OMAP_I2C_IP_V2_REVNB_LO, |
| 87 | OMAP_I2C_IP_V2_REVNB_HI, |
| 88 | OMAP_I2C_IP_V2_IRQSTATUS_RAW, |
| 89 | OMAP_I2C_IP_V2_IRQENABLE_SET, |
| 90 | OMAP_I2C_IP_V2_IRQENABLE_CLR, |
| 91 | }; |
| 92 | |
| 93 | static const u8 __maybe_unused reg_map_ip_v1[] = { |
| 94 | [OMAP_I2C_REV_REG] = 0x00, |
| 95 | [OMAP_I2C_IE_REG] = 0x04, |
| 96 | [OMAP_I2C_STAT_REG] = 0x08, |
| 97 | [OMAP_I2C_WE_REG] = 0x0c, |
| 98 | [OMAP_I2C_SYSS_REG] = 0x10, |
| 99 | [OMAP_I2C_BUF_REG] = 0x14, |
| 100 | [OMAP_I2C_CNT_REG] = 0x18, |
| 101 | [OMAP_I2C_DATA_REG] = 0x1c, |
| 102 | [OMAP_I2C_SYSC_REG] = 0x20, |
| 103 | [OMAP_I2C_CON_REG] = 0x24, |
| 104 | [OMAP_I2C_OA_REG] = 0x28, |
| 105 | [OMAP_I2C_SA_REG] = 0x2c, |
| 106 | [OMAP_I2C_PSC_REG] = 0x30, |
| 107 | [OMAP_I2C_SCLL_REG] = 0x34, |
| 108 | [OMAP_I2C_SCLH_REG] = 0x38, |
| 109 | [OMAP_I2C_SYSTEST_REG] = 0x3c, |
| 110 | [OMAP_I2C_BUFSTAT_REG] = 0x40, |
| 111 | }; |
| 112 | |
| 113 | static const u8 __maybe_unused reg_map_ip_v2[] = { |
| 114 | [OMAP_I2C_STAT_REG] = 0x28, |
| 115 | [OMAP_I2C_WE_REG] = 0x34, |
| 116 | [OMAP_I2C_SYSS_REG] = 0x90, |
| 117 | [OMAP_I2C_BUF_REG] = 0x94, |
| 118 | [OMAP_I2C_CNT_REG] = 0x98, |
| 119 | [OMAP_I2C_DATA_REG] = 0x9c, |
| 120 | [OMAP_I2C_SYSC_REG] = 0x10, |
| 121 | [OMAP_I2C_CON_REG] = 0xa4, |
| 122 | [OMAP_I2C_OA_REG] = 0xa8, |
| 123 | [OMAP_I2C_SA_REG] = 0xac, |
| 124 | [OMAP_I2C_PSC_REG] = 0xb0, |
| 125 | [OMAP_I2C_SCLL_REG] = 0xb4, |
| 126 | [OMAP_I2C_SCLH_REG] = 0xb8, |
| 127 | [OMAP_I2C_SYSTEST_REG] = 0xbc, |
| 128 | [OMAP_I2C_BUFSTAT_REG] = 0xc0, |
| 129 | [OMAP_I2C_IP_V2_REVNB_LO] = 0x00, |
| 130 | [OMAP_I2C_IP_V2_REVNB_HI] = 0x04, |
| 131 | [OMAP_I2C_IP_V2_IRQSTATUS_RAW] = 0x24, |
| 132 | [OMAP_I2C_IP_V2_IRQENABLE_SET] = 0x2c, |
| 133 | [OMAP_I2C_IP_V2_IRQENABLE_CLR] = 0x30, |
| 134 | }; |
| 135 | |
Mugunthan V N | 560037b | 2016-07-18 15:11:01 +0530 | [diff] [blame] | 136 | struct omap_i2c { |
| 137 | struct udevice *clk; |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 138 | int ip_rev; |
Mugunthan V N | 560037b | 2016-07-18 15:11:01 +0530 | [diff] [blame] | 139 | struct i2c *regs; |
| 140 | unsigned int speed; |
| 141 | int waitdelay; |
| 142 | int clk_id; |
| 143 | }; |
| 144 | |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 145 | static inline const u8 *omap_i2c_get_ip_reg_map(int ip_rev) |
| 146 | { |
| 147 | switch (ip_rev) { |
| 148 | case OMAP_I2C_REV_V1: |
| 149 | return reg_map_ip_v1; |
| 150 | case OMAP_I2C_REV_V2: |
| 151 | /* Fall through... */ |
| 152 | default: |
| 153 | return reg_map_ip_v2; |
| 154 | } |
| 155 | } |
| 156 | |
| 157 | static inline void omap_i2c_write_reg(void __iomem *base, int ip_rev, |
| 158 | u16 val, int reg) |
| 159 | { |
| 160 | writew(val, base + omap_i2c_get_ip_reg_map(ip_rev)[reg]); |
| 161 | } |
| 162 | |
| 163 | static inline u16 omap_i2c_read_reg(void __iomem *base, int ip_rev, int reg) |
| 164 | { |
| 165 | return readw(base + omap_i2c_get_ip_reg_map(ip_rev)[reg]); |
| 166 | } |
| 167 | |
Hannes Petermaier | d588505 | 2014-02-03 21:22:18 +0100 | [diff] [blame] | 168 | static int omap24_i2c_findpsc(u32 *pscl, u32 *psch, uint speed) |
wdenk | f806271 | 2005-01-09 23:16:25 +0000 | [diff] [blame] | 169 | { |
Lukasz Majewski | 698a9ba | 2017-03-15 16:59:23 +0100 | [diff] [blame] | 170 | unsigned long internal_clk = 0, fclk; |
| 171 | unsigned int prescaler; |
Tom Rix | 03b2a74 | 2009-06-28 12:52:27 -0500 | [diff] [blame] | 172 | |
Hannes Petermaier | d588505 | 2014-02-03 21:22:18 +0100 | [diff] [blame] | 173 | /* |
Lukasz Majewski | 698a9ba | 2017-03-15 16:59:23 +0100 | [diff] [blame] | 174 | * This method is only called for Standard and Fast Mode speeds |
| 175 | * |
| 176 | * For some TI SoCs it is explicitly written in TRM (e,g, SPRUHZ6G, |
| 177 | * page 5685, Table 24-7) |
| 178 | * that the internal I2C clock (after prescaler) should be between |
| 179 | * 7-12 MHz (at least for Fast Mode (FS)). |
| 180 | * |
| 181 | * Such approach is used in v4.9 Linux kernel in: |
| 182 | * ./drivers/i2c/busses/i2c-omap.c (omap_i2c_init function). |
Hannes Petermaier | d588505 | 2014-02-03 21:22:18 +0100 | [diff] [blame] | 183 | */ |
Tom Rix | 03b2a74 | 2009-06-28 12:52:27 -0500 | [diff] [blame] | 184 | |
Lukasz Majewski | 698a9ba | 2017-03-15 16:59:23 +0100 | [diff] [blame] | 185 | speed /= 1000; /* convert speed to kHz */ |
Hannes Petermaier | d588505 | 2014-02-03 21:22:18 +0100 | [diff] [blame] | 186 | |
Lukasz Majewski | 698a9ba | 2017-03-15 16:59:23 +0100 | [diff] [blame] | 187 | if (speed > 100) |
| 188 | internal_clk = 9600; |
| 189 | else |
| 190 | internal_clk = 4000; |
Hannes Petermaier | d588505 | 2014-02-03 21:22:18 +0100 | [diff] [blame] | 191 | |
Lukasz Majewski | 698a9ba | 2017-03-15 16:59:23 +0100 | [diff] [blame] | 192 | fclk = I2C_IP_CLK / 1000; |
| 193 | prescaler = fclk / internal_clk; |
| 194 | prescaler = prescaler - 1; |
| 195 | |
| 196 | if (speed > 100) { |
| 197 | unsigned long scl; |
| 198 | |
| 199 | /* Fast mode */ |
| 200 | scl = internal_clk / speed; |
| 201 | *pscl = scl - (scl / 3) - I2C_FASTSPEED_SCLL_TRIM; |
| 202 | *psch = (scl / 3) - I2C_FASTSPEED_SCLH_TRIM; |
| 203 | } else { |
| 204 | /* Standard mode */ |
| 205 | *pscl = internal_clk / (speed * 2) - I2C_FASTSPEED_SCLL_TRIM; |
| 206 | *psch = internal_clk / (speed * 2) - I2C_FASTSPEED_SCLH_TRIM; |
Tom Rix | 03b2a74 | 2009-06-28 12:52:27 -0500 | [diff] [blame] | 207 | } |
Lukasz Majewski | 698a9ba | 2017-03-15 16:59:23 +0100 | [diff] [blame] | 208 | |
| 209 | debug("%s: speed [kHz]: %d psc: 0x%x sscl: 0x%x ssch: 0x%x\n", |
| 210 | __func__, speed, prescaler, *pscl, *psch); |
| 211 | |
| 212 | if (*pscl <= 0 || *psch <= 0 || prescaler <= 0) |
| 213 | return -EINVAL; |
| 214 | |
| 215 | return prescaler; |
Hannes Petermaier | d588505 | 2014-02-03 21:22:18 +0100 | [diff] [blame] | 216 | } |
Mugunthan V N | 38d943a | 2016-07-18 15:11:00 +0530 | [diff] [blame] | 217 | |
| 218 | /* |
| 219 | * Wait for the bus to be free by checking the Bus Busy (BB) |
| 220 | * bit to become clear |
| 221 | */ |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 222 | static int wait_for_bb(void __iomem *i2c_base, int ip_rev, int waitdelay) |
Hannes Petermaier | d588505 | 2014-02-03 21:22:18 +0100 | [diff] [blame] | 223 | { |
Mugunthan V N | 38d943a | 2016-07-18 15:11:00 +0530 | [diff] [blame] | 224 | int timeout = I2C_TIMEOUT; |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 225 | int irq_stat_reg; |
Mugunthan V N | 38d943a | 2016-07-18 15:11:00 +0530 | [diff] [blame] | 226 | u16 stat; |
| 227 | |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 228 | irq_stat_reg = (ip_rev == OMAP_I2C_REV_V1) ? |
| 229 | OMAP_I2C_STAT_REG : OMAP_I2C_IP_V2_IRQSTATUS_RAW; |
| 230 | |
| 231 | /* clear current interrupts */ |
| 232 | omap_i2c_write_reg(i2c_base, ip_rev, 0xFFFF, OMAP_I2C_STAT_REG); |
| 233 | |
| 234 | while ((stat = omap_i2c_read_reg(i2c_base, ip_rev, irq_stat_reg) & |
Mugunthan V N | 38d943a | 2016-07-18 15:11:00 +0530 | [diff] [blame] | 235 | I2C_STAT_BB) && timeout--) { |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 236 | omap_i2c_write_reg(i2c_base, ip_rev, stat, OMAP_I2C_STAT_REG); |
Mugunthan V N | 38d943a | 2016-07-18 15:11:00 +0530 | [diff] [blame] | 237 | udelay(waitdelay); |
| 238 | } |
| 239 | |
| 240 | if (timeout <= 0) { |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 241 | printf("Timed out in %s: status=%04x\n", __func__, stat); |
Mugunthan V N | 38d943a | 2016-07-18 15:11:00 +0530 | [diff] [blame] | 242 | return 1; |
| 243 | } |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 244 | |
| 245 | /* clear delayed stuff */ |
| 246 | omap_i2c_write_reg(i2c_base, ip_rev, 0xFFFF, OMAP_I2C_STAT_REG); |
Mugunthan V N | 38d943a | 2016-07-18 15:11:00 +0530 | [diff] [blame] | 247 | return 0; |
| 248 | } |
| 249 | |
| 250 | /* |
| 251 | * Wait for the I2C controller to complete current action |
| 252 | * and update status |
| 253 | */ |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 254 | static u16 wait_for_event(void __iomem *i2c_base, int ip_rev, int waitdelay) |
Mugunthan V N | 38d943a | 2016-07-18 15:11:00 +0530 | [diff] [blame] | 255 | { |
| 256 | u16 status; |
| 257 | int timeout = I2C_TIMEOUT; |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 258 | int irq_stat_reg; |
Mugunthan V N | 38d943a | 2016-07-18 15:11:00 +0530 | [diff] [blame] | 259 | |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 260 | irq_stat_reg = (ip_rev == OMAP_I2C_REV_V1) ? |
| 261 | OMAP_I2C_STAT_REG : OMAP_I2C_IP_V2_IRQSTATUS_RAW; |
Mugunthan V N | 38d943a | 2016-07-18 15:11:00 +0530 | [diff] [blame] | 262 | do { |
| 263 | udelay(waitdelay); |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 264 | status = omap_i2c_read_reg(i2c_base, ip_rev, irq_stat_reg); |
Mugunthan V N | 38d943a | 2016-07-18 15:11:00 +0530 | [diff] [blame] | 265 | } while (!(status & |
| 266 | (I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY | |
| 267 | I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK | |
| 268 | I2C_STAT_AL)) && timeout--); |
| 269 | |
| 270 | if (timeout <= 0) { |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 271 | printf("Timed out in %s: status=%04x\n", __func__, status); |
Mugunthan V N | 38d943a | 2016-07-18 15:11:00 +0530 | [diff] [blame] | 272 | /* |
| 273 | * If status is still 0 here, probably the bus pads have |
| 274 | * not been configured for I2C, and/or pull-ups are missing. |
| 275 | */ |
| 276 | printf("Check if pads/pull-ups of bus are properly configured\n"); |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 277 | omap_i2c_write_reg(i2c_base, ip_rev, 0xFFFF, OMAP_I2C_STAT_REG); |
Mugunthan V N | 38d943a | 2016-07-18 15:11:00 +0530 | [diff] [blame] | 278 | status = 0; |
| 279 | } |
| 280 | |
| 281 | return status; |
| 282 | } |
| 283 | |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 284 | static void flush_fifo(void __iomem *i2c_base, int ip_rev) |
Mugunthan V N | 38d943a | 2016-07-18 15:11:00 +0530 | [diff] [blame] | 285 | { |
| 286 | u16 stat; |
| 287 | |
| 288 | /* |
| 289 | * note: if you try and read data when its not there or ready |
| 290 | * you get a bus error |
| 291 | */ |
| 292 | while (1) { |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 293 | stat = omap_i2c_read_reg(i2c_base, ip_rev, OMAP_I2C_STAT_REG); |
Mugunthan V N | 38d943a | 2016-07-18 15:11:00 +0530 | [diff] [blame] | 294 | if (stat == I2C_STAT_RRDY) { |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 295 | omap_i2c_read_reg(i2c_base, ip_rev, OMAP_I2C_DATA_REG); |
| 296 | omap_i2c_write_reg(i2c_base, ip_rev, |
| 297 | I2C_STAT_RRDY, OMAP_I2C_STAT_REG); |
Mugunthan V N | 38d943a | 2016-07-18 15:11:00 +0530 | [diff] [blame] | 298 | udelay(1000); |
| 299 | } else |
| 300 | break; |
| 301 | } |
| 302 | } |
| 303 | |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 304 | static int __omap24_i2c_setspeed(void __iomem *i2c_base, int ip_rev, uint speed, |
Mugunthan V N | 38d943a | 2016-07-18 15:11:00 +0530 | [diff] [blame] | 305 | int *waitdelay) |
| 306 | { |
Hannes Petermaier | d588505 | 2014-02-03 21:22:18 +0100 | [diff] [blame] | 307 | int psc, fsscll = 0, fssclh = 0; |
| 308 | int hsscll = 0, hssclh = 0; |
| 309 | u32 scll = 0, sclh = 0; |
Tom Rix | 03b2a74 | 2009-06-28 12:52:27 -0500 | [diff] [blame] | 310 | |
Simon Glass | ed0a60a | 2020-01-23 11:48:20 -0700 | [diff] [blame] | 311 | if (speed >= I2C_SPEED_HIGH_RATE) { |
Tom Rix | 03b2a74 | 2009-06-28 12:52:27 -0500 | [diff] [blame] | 312 | /* High speed */ |
Hannes Petermaier | d588505 | 2014-02-03 21:22:18 +0100 | [diff] [blame] | 313 | psc = I2C_IP_CLK / I2C_INTERNAL_SAMPLING_CLK; |
| 314 | psc -= 1; |
| 315 | if (psc < I2C_PSC_MIN) { |
| 316 | printf("Error : I2C unsupported prescaler %d\n", psc); |
| 317 | return -1; |
| 318 | } |
Tom Rix | 03b2a74 | 2009-06-28 12:52:27 -0500 | [diff] [blame] | 319 | |
| 320 | /* For first phase of HS mode */ |
Hannes Petermaier | d588505 | 2014-02-03 21:22:18 +0100 | [diff] [blame] | 321 | fsscll = I2C_INTERNAL_SAMPLING_CLK / (2 * speed); |
| 322 | |
| 323 | fssclh = fsscll; |
Tom Rix | 03b2a74 | 2009-06-28 12:52:27 -0500 | [diff] [blame] | 324 | |
| 325 | fsscll -= I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM; |
| 326 | fssclh -= I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM; |
| 327 | if (((fsscll < 0) || (fssclh < 0)) || |
| 328 | ((fsscll > 255) || (fssclh > 255))) { |
Andreas Müller | a30293f | 2012-01-04 15:26:19 +0000 | [diff] [blame] | 329 | puts("Error : I2C initializing first phase clock\n"); |
Hannes Petermaier | d588505 | 2014-02-03 21:22:18 +0100 | [diff] [blame] | 330 | return -1; |
Tom Rix | 03b2a74 | 2009-06-28 12:52:27 -0500 | [diff] [blame] | 331 | } |
| 332 | |
| 333 | /* For second phase of HS mode */ |
| 334 | hsscll = hssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed); |
| 335 | |
| 336 | hsscll -= I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM; |
| 337 | hssclh -= I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM; |
| 338 | if (((fsscll < 0) || (fssclh < 0)) || |
| 339 | ((fsscll > 255) || (fssclh > 255))) { |
Andreas Müller | a30293f | 2012-01-04 15:26:19 +0000 | [diff] [blame] | 340 | puts("Error : I2C initializing second phase clock\n"); |
Hannes Petermaier | d588505 | 2014-02-03 21:22:18 +0100 | [diff] [blame] | 341 | return -1; |
Tom Rix | 03b2a74 | 2009-06-28 12:52:27 -0500 | [diff] [blame] | 342 | } |
| 343 | |
| 344 | scll = (unsigned int)hsscll << 8 | (unsigned int)fsscll; |
| 345 | sclh = (unsigned int)hssclh << 8 | (unsigned int)fssclh; |
| 346 | |
| 347 | } else { |
| 348 | /* Standard and fast speed */ |
Hannes Petermaier | d588505 | 2014-02-03 21:22:18 +0100 | [diff] [blame] | 349 | psc = omap24_i2c_findpsc(&scll, &sclh, speed); |
| 350 | if (0 > psc) { |
Andreas Müller | a30293f | 2012-01-04 15:26:19 +0000 | [diff] [blame] | 351 | puts("Error : I2C initializing clock\n"); |
Hannes Petermaier | d588505 | 2014-02-03 21:22:18 +0100 | [diff] [blame] | 352 | return -1; |
Tom Rix | 03b2a74 | 2009-06-28 12:52:27 -0500 | [diff] [blame] | 353 | } |
Tom Rix | 03b2a74 | 2009-06-28 12:52:27 -0500 | [diff] [blame] | 354 | } |
wdenk | f806271 | 2005-01-09 23:16:25 +0000 | [diff] [blame] | 355 | |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 356 | /* wait for 20 clkperiods */ |
| 357 | *waitdelay = (10000000 / speed) * 2; |
| 358 | |
| 359 | omap_i2c_write_reg(i2c_base, ip_rev, 0, OMAP_I2C_CON_REG); |
| 360 | omap_i2c_write_reg(i2c_base, ip_rev, psc, OMAP_I2C_PSC_REG); |
| 361 | omap_i2c_write_reg(i2c_base, ip_rev, scll, OMAP_I2C_SCLL_REG); |
| 362 | omap_i2c_write_reg(i2c_base, ip_rev, sclh, OMAP_I2C_SCLH_REG); |
| 363 | omap_i2c_write_reg(i2c_base, ip_rev, I2C_CON_EN, OMAP_I2C_CON_REG); |
| 364 | |
| 365 | /* clear all pending status */ |
| 366 | omap_i2c_write_reg(i2c_base, ip_rev, 0xFFFF, OMAP_I2C_STAT_REG); |
Hannes Petermaier | d588505 | 2014-02-03 21:22:18 +0100 | [diff] [blame] | 367 | |
| 368 | return 0; |
| 369 | } |
Heiko Schocher | 0ecd655 | 2014-06-30 09:12:09 +0200 | [diff] [blame] | 370 | |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 371 | static void omap24_i2c_deblock(void __iomem *i2c_base, int ip_rev) |
Heiko Schocher | 0ecd655 | 2014-06-30 09:12:09 +0200 | [diff] [blame] | 372 | { |
Heiko Schocher | 0ecd655 | 2014-06-30 09:12:09 +0200 | [diff] [blame] | 373 | int i; |
| 374 | u16 systest; |
| 375 | u16 orgsystest; |
| 376 | |
| 377 | /* set test mode ST_EN = 1 */ |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 378 | orgsystest = omap_i2c_read_reg(i2c_base, ip_rev, OMAP_I2C_SYSTEST_REG); |
Heiko Schocher | 0ecd655 | 2014-06-30 09:12:09 +0200 | [diff] [blame] | 379 | systest = orgsystest; |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 380 | |
Heiko Schocher | 0ecd655 | 2014-06-30 09:12:09 +0200 | [diff] [blame] | 381 | /* enable testmode */ |
| 382 | systest |= I2C_SYSTEST_ST_EN; |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 383 | omap_i2c_write_reg(i2c_base, ip_rev, systest, OMAP_I2C_SYSTEST_REG); |
Heiko Schocher | 0ecd655 | 2014-06-30 09:12:09 +0200 | [diff] [blame] | 384 | systest &= ~I2C_SYSTEST_TMODE_MASK; |
| 385 | systest |= 3 << I2C_SYSTEST_TMODE_SHIFT; |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 386 | omap_i2c_write_reg(i2c_base, ip_rev, systest, OMAP_I2C_SYSTEST_REG); |
Heiko Schocher | 0ecd655 | 2014-06-30 09:12:09 +0200 | [diff] [blame] | 387 | |
| 388 | /* set SCL, SDA = 1 */ |
| 389 | systest |= I2C_SYSTEST_SCL_O | I2C_SYSTEST_SDA_O; |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 390 | omap_i2c_write_reg(i2c_base, ip_rev, systest, OMAP_I2C_SYSTEST_REG); |
Heiko Schocher | 0ecd655 | 2014-06-30 09:12:09 +0200 | [diff] [blame] | 391 | udelay(10); |
| 392 | |
| 393 | /* toggle scl 9 clocks */ |
| 394 | for (i = 0; i < 9; i++) { |
| 395 | /* SCL = 0 */ |
| 396 | systest &= ~I2C_SYSTEST_SCL_O; |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 397 | omap_i2c_write_reg(i2c_base, ip_rev, |
| 398 | systest, OMAP_I2C_SYSTEST_REG); |
Heiko Schocher | 0ecd655 | 2014-06-30 09:12:09 +0200 | [diff] [blame] | 399 | udelay(10); |
| 400 | /* SCL = 1 */ |
| 401 | systest |= I2C_SYSTEST_SCL_O; |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 402 | omap_i2c_write_reg(i2c_base, ip_rev, |
| 403 | systest, OMAP_I2C_SYSTEST_REG); |
Heiko Schocher | 0ecd655 | 2014-06-30 09:12:09 +0200 | [diff] [blame] | 404 | udelay(10); |
| 405 | } |
| 406 | |
| 407 | /* send stop */ |
| 408 | systest &= ~I2C_SYSTEST_SDA_O; |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 409 | omap_i2c_write_reg(i2c_base, ip_rev, systest, OMAP_I2C_SYSTEST_REG); |
Heiko Schocher | 0ecd655 | 2014-06-30 09:12:09 +0200 | [diff] [blame] | 410 | udelay(10); |
| 411 | systest |= I2C_SYSTEST_SCL_O | I2C_SYSTEST_SDA_O; |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 412 | omap_i2c_write_reg(i2c_base, ip_rev, systest, OMAP_I2C_SYSTEST_REG); |
Heiko Schocher | 0ecd655 | 2014-06-30 09:12:09 +0200 | [diff] [blame] | 413 | udelay(10); |
| 414 | |
| 415 | /* restore original mode */ |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 416 | omap_i2c_write_reg(i2c_base, ip_rev, orgsystest, OMAP_I2C_SYSTEST_REG); |
Heiko Schocher | 0ecd655 | 2014-06-30 09:12:09 +0200 | [diff] [blame] | 417 | } |
| 418 | |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 419 | static void __omap24_i2c_init(void __iomem *i2c_base, int ip_rev, int speed, |
| 420 | int slaveadd, int *waitdelay) |
Hannes Petermaier | d588505 | 2014-02-03 21:22:18 +0100 | [diff] [blame] | 421 | { |
Hannes Petermaier | d588505 | 2014-02-03 21:22:18 +0100 | [diff] [blame] | 422 | int timeout = I2C_TIMEOUT; |
Heiko Schocher | 0ecd655 | 2014-06-30 09:12:09 +0200 | [diff] [blame] | 423 | int deblock = 1; |
Hannes Petermaier | d588505 | 2014-02-03 21:22:18 +0100 | [diff] [blame] | 424 | |
Heiko Schocher | 0ecd655 | 2014-06-30 09:12:09 +0200 | [diff] [blame] | 425 | retry: |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 426 | if (omap_i2c_read_reg(i2c_base, ip_rev, OMAP_I2C_CON_REG) & |
| 427 | I2C_CON_EN) { |
| 428 | omap_i2c_write_reg(i2c_base, ip_rev, 0, OMAP_I2C_CON_REG); |
Michael Jones | 4db6786 | 2011-07-27 14:01:55 -0400 | [diff] [blame] | 429 | udelay(50000); |
wdenk | f806271 | 2005-01-09 23:16:25 +0000 | [diff] [blame] | 430 | } |
| 431 | |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 432 | /* for ES2 after soft reset */ |
| 433 | omap_i2c_write_reg(i2c_base, ip_rev, 0x2, OMAP_I2C_SYSC_REG); |
Tom Rini | 49fbf67 | 2012-02-20 18:49:16 +0000 | [diff] [blame] | 434 | udelay(1000); |
| 435 | |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 436 | omap_i2c_write_reg(i2c_base, ip_rev, I2C_CON_EN, OMAP_I2C_CON_REG); |
| 437 | while (!(omap_i2c_read_reg(i2c_base, ip_rev, OMAP_I2C_SYSS_REG) & |
| 438 | I2C_SYSS_RDONE) && timeout--) { |
Tom Rini | 49fbf67 | 2012-02-20 18:49:16 +0000 | [diff] [blame] | 439 | if (timeout <= 0) { |
| 440 | puts("ERROR: Timeout in soft-reset\n"); |
| 441 | return; |
| 442 | } |
| 443 | udelay(1000); |
| 444 | } |
| 445 | |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 446 | if (__omap24_i2c_setspeed(i2c_base, ip_rev, speed, waitdelay)) { |
Hannes Petermaier | d588505 | 2014-02-03 21:22:18 +0100 | [diff] [blame] | 447 | printf("ERROR: failed to setup I2C bus-speed!\n"); |
| 448 | return; |
| 449 | } |
Tom Rix | 03b2a74 | 2009-06-28 12:52:27 -0500 | [diff] [blame] | 450 | |
wdenk | f806271 | 2005-01-09 23:16:25 +0000 | [diff] [blame] | 451 | /* own address */ |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 452 | omap_i2c_write_reg(i2c_base, ip_rev, slaveadd, OMAP_I2C_OA_REG); |
Hannes Petermaier | d588505 | 2014-02-03 21:22:18 +0100 | [diff] [blame] | 453 | |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 454 | if (ip_rev == OMAP_I2C_REV_V1) { |
| 455 | /* |
| 456 | * Have to enable interrupts for OMAP2/3, these IPs don't have |
| 457 | * an 'irqstatus_raw' register and we shall have to poll 'stat' |
| 458 | */ |
| 459 | omap_i2c_write_reg(i2c_base, ip_rev, I2C_IE_XRDY_IE | |
| 460 | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE | |
| 461 | I2C_IE_NACK_IE | I2C_IE_AL_IE, |
| 462 | OMAP_I2C_IE_REG); |
| 463 | } |
| 464 | |
Michael Jones | 4db6786 | 2011-07-27 14:01:55 -0400 | [diff] [blame] | 465 | udelay(1000); |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 466 | flush_fifo(i2c_base, ip_rev); |
| 467 | omap_i2c_write_reg(i2c_base, ip_rev, 0xFFFF, OMAP_I2C_STAT_REG); |
Heiko Schocher | 0ecd655 | 2014-06-30 09:12:09 +0200 | [diff] [blame] | 468 | |
| 469 | /* Handle possible failed I2C state */ |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 470 | if (wait_for_bb(i2c_base, ip_rev, *waitdelay)) |
Heiko Schocher | 0ecd655 | 2014-06-30 09:12:09 +0200 | [diff] [blame] | 471 | if (deblock == 1) { |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 472 | omap24_i2c_deblock(i2c_base, ip_rev); |
Heiko Schocher | 0ecd655 | 2014-06-30 09:12:09 +0200 | [diff] [blame] | 473 | deblock = 0; |
| 474 | goto retry; |
| 475 | } |
wdenk | f806271 | 2005-01-09 23:16:25 +0000 | [diff] [blame] | 476 | } |
| 477 | |
Lubomir Popov | 4d98efd | 2013-06-01 06:44:38 +0000 | [diff] [blame] | 478 | /* |
| 479 | * i2c_probe: Use write access. Allows to identify addresses that are |
| 480 | * write-only (like the config register of dual-port EEPROMs) |
| 481 | */ |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 482 | static int __omap24_i2c_probe(void __iomem *i2c_base, int ip_rev, int waitdelay, |
| 483 | uchar chip) |
wdenk | f806271 | 2005-01-09 23:16:25 +0000 | [diff] [blame] | 484 | { |
Tom Rini | 49fbf67 | 2012-02-20 18:49:16 +0000 | [diff] [blame] | 485 | u16 status; |
wdenk | f806271 | 2005-01-09 23:16:25 +0000 | [diff] [blame] | 486 | int res = 1; /* default = fail */ |
| 487 | |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 488 | if (chip == omap_i2c_read_reg(i2c_base, ip_rev, OMAP_I2C_OA_REG)) |
wdenk | f806271 | 2005-01-09 23:16:25 +0000 | [diff] [blame] | 489 | return res; |
wdenk | f806271 | 2005-01-09 23:16:25 +0000 | [diff] [blame] | 490 | |
Lubomir Popov | 4d98efd | 2013-06-01 06:44:38 +0000 | [diff] [blame] | 491 | /* Wait until bus is free */ |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 492 | if (wait_for_bb(i2c_base, ip_rev, waitdelay)) |
Vincent Stehlé | 33205e3 | 2012-12-03 05:23:16 +0000 | [diff] [blame] | 493 | return res; |
wdenk | f806271 | 2005-01-09 23:16:25 +0000 | [diff] [blame] | 494 | |
Lubomir Popov | 4d98efd | 2013-06-01 06:44:38 +0000 | [diff] [blame] | 495 | /* No data transfer, slave addr only */ |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 496 | omap_i2c_write_reg(i2c_base, ip_rev, chip, OMAP_I2C_SA_REG); |
| 497 | |
Lubomir Popov | 4d98efd | 2013-06-01 06:44:38 +0000 | [diff] [blame] | 498 | /* Stop bit needed here */ |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 499 | omap_i2c_write_reg(i2c_base, ip_rev, I2C_CON_EN | I2C_CON_MST | |
| 500 | I2C_CON_STT | I2C_CON_TRX | I2C_CON_STP, |
| 501 | OMAP_I2C_CON_REG); |
Nick Thompson | 48f7ae4 | 2011-04-11 22:37:41 +0000 | [diff] [blame] | 502 | |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 503 | status = wait_for_event(i2c_base, ip_rev, waitdelay); |
Vincent Stehlé | 33205e3 | 2012-12-03 05:23:16 +0000 | [diff] [blame] | 504 | |
Lubomir Popov | 4d98efd | 2013-06-01 06:44:38 +0000 | [diff] [blame] | 505 | if ((status & ~I2C_STAT_XRDY) == 0 || (status & I2C_STAT_AL)) { |
| 506 | /* |
| 507 | * With current high-level command implementation, notifying |
| 508 | * the user shall flood the console with 127 messages. If |
| 509 | * silent exit is desired upon unconfigured bus, remove the |
| 510 | * following 'if' section: |
| 511 | */ |
| 512 | if (status == I2C_STAT_XRDY) |
Mugunthan V N | 38d943a | 2016-07-18 15:11:00 +0530 | [diff] [blame] | 513 | printf("i2c_probe: pads on bus probably not configured (status=0x%x)\n", |
| 514 | status); |
Vincent Stehlé | 33205e3 | 2012-12-03 05:23:16 +0000 | [diff] [blame] | 515 | |
Lubomir Popov | 4d98efd | 2013-06-01 06:44:38 +0000 | [diff] [blame] | 516 | goto pr_exit; |
Tom Rini | 27eed8b | 2012-05-21 06:46:29 +0000 | [diff] [blame] | 517 | } |
Tom Rini | 49fbf67 | 2012-02-20 18:49:16 +0000 | [diff] [blame] | 518 | |
Lubomir Popov | 4d98efd | 2013-06-01 06:44:38 +0000 | [diff] [blame] | 519 | /* Check for ACK (!NAK) */ |
| 520 | if (!(status & I2C_STAT_NACK)) { |
Hannes Petermaier | d588505 | 2014-02-03 21:22:18 +0100 | [diff] [blame] | 521 | res = 0; /* Device found */ |
Mugunthan V N | 38d943a | 2016-07-18 15:11:00 +0530 | [diff] [blame] | 522 | udelay(waitdelay);/* Required by AM335X in SPL */ |
Lubomir Popov | 4d98efd | 2013-06-01 06:44:38 +0000 | [diff] [blame] | 523 | /* Abort transfer (force idle state) */ |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 524 | omap_i2c_write_reg(i2c_base, ip_rev, I2C_CON_MST | I2C_CON_TRX, |
| 525 | OMAP_I2C_CON_REG); /* Reset */ |
Lubomir Popov | 4d98efd | 2013-06-01 06:44:38 +0000 | [diff] [blame] | 526 | udelay(1000); |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 527 | omap_i2c_write_reg(i2c_base, ip_rev, I2C_CON_EN | I2C_CON_MST | |
| 528 | I2C_CON_TRX | I2C_CON_STP, |
| 529 | OMAP_I2C_CON_REG); /* STP */ |
Lubomir Popov | 4d98efd | 2013-06-01 06:44:38 +0000 | [diff] [blame] | 530 | } |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 531 | |
Lubomir Popov | 4d98efd | 2013-06-01 06:44:38 +0000 | [diff] [blame] | 532 | pr_exit: |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 533 | flush_fifo(i2c_base, ip_rev); |
| 534 | omap_i2c_write_reg(i2c_base, ip_rev, 0xFFFF, OMAP_I2C_STAT_REG); |
wdenk | f806271 | 2005-01-09 23:16:25 +0000 | [diff] [blame] | 535 | return res; |
| 536 | } |
| 537 | |
Lubomir Popov | 4d98efd | 2013-06-01 06:44:38 +0000 | [diff] [blame] | 538 | /* |
| 539 | * i2c_read: Function now uses a single I2C read transaction with bulk transfer |
| 540 | * of the requested number of bytes (note that the 'i2c md' command |
| 541 | * limits this to 16 bytes anyway). If CONFIG_I2C_REPEATED_START is |
| 542 | * defined in the board config header, this transaction shall be with |
| 543 | * Repeated Start (Sr) between the address and data phases; otherwise |
| 544 | * Stop-Start (P-S) shall be used (some I2C chips do require a P-S). |
| 545 | * The address (reg offset) may be 0, 1 or 2 bytes long. |
| 546 | * Function now reads correctly from chips that return more than one |
| 547 | * byte of data per addressed register (like TI temperature sensors), |
| 548 | * or that do not need a register address at all (such as some clock |
| 549 | * distributors). |
| 550 | */ |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 551 | static int __omap24_i2c_read(void __iomem *i2c_base, int ip_rev, int waitdelay, |
| 552 | uchar chip, uint addr, int alen, uchar *buffer, |
| 553 | int len) |
wdenk | f806271 | 2005-01-09 23:16:25 +0000 | [diff] [blame] | 554 | { |
Lubomir Popov | 4d98efd | 2013-06-01 06:44:38 +0000 | [diff] [blame] | 555 | int i2c_error = 0; |
| 556 | u16 status; |
| 557 | |
| 558 | if (alen < 0) { |
| 559 | puts("I2C read: addr len < 0\n"); |
| 560 | return 1; |
| 561 | } |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 562 | |
Lubomir Popov | 4d98efd | 2013-06-01 06:44:38 +0000 | [diff] [blame] | 563 | if (len < 0) { |
| 564 | puts("I2C read: data len < 0\n"); |
| 565 | return 1; |
| 566 | } |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 567 | |
Lubomir Popov | 4d98efd | 2013-06-01 06:44:38 +0000 | [diff] [blame] | 568 | if (buffer == NULL) { |
| 569 | puts("I2C read: NULL pointer passed\n"); |
| 570 | return 1; |
| 571 | } |
wdenk | f806271 | 2005-01-09 23:16:25 +0000 | [diff] [blame] | 572 | |
Ilya Yanok | be6c2e4 | 2012-06-08 03:12:09 +0000 | [diff] [blame] | 573 | if (alen > 2) { |
Tom Rini | 49fbf67 | 2012-02-20 18:49:16 +0000 | [diff] [blame] | 574 | printf("I2C read: addr len %d not supported\n", alen); |
wdenk | f806271 | 2005-01-09 23:16:25 +0000 | [diff] [blame] | 575 | return 1; |
| 576 | } |
| 577 | |
Ilya Yanok | be6c2e4 | 2012-06-08 03:12:09 +0000 | [diff] [blame] | 578 | if (addr + len > (1 << 16)) { |
Tom Rini | 49fbf67 | 2012-02-20 18:49:16 +0000 | [diff] [blame] | 579 | puts("I2C read: address out of range\n"); |
wdenk | f806271 | 2005-01-09 23:16:25 +0000 | [diff] [blame] | 580 | return 1; |
| 581 | } |
| 582 | |
Guy Thouret | 51c2727 | 2016-03-11 16:23:41 +0000 | [diff] [blame] | 583 | #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW |
| 584 | /* |
| 585 | * EEPROM chips that implement "address overflow" are ones |
| 586 | * like Catalyst 24WC04/08/16 which has 9/10/11 bits of |
| 587 | * address and the extra bits end up in the "chip address" |
| 588 | * bit slots. This makes a 24WC08 (1Kbyte) chip look like |
| 589 | * four 256 byte chips. |
| 590 | * |
| 591 | * Note that we consider the length of the address field to |
| 592 | * still be one byte because the extra address bits are |
| 593 | * hidden in the chip address. |
| 594 | */ |
| 595 | if (alen > 0) |
| 596 | chip |= ((addr >> (alen * 8)) & |
| 597 | CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); |
| 598 | #endif |
| 599 | |
Lubomir Popov | 4d98efd | 2013-06-01 06:44:38 +0000 | [diff] [blame] | 600 | /* Wait until bus not busy */ |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 601 | if (wait_for_bb(i2c_base, ip_rev, waitdelay)) |
Lubomir Popov | 4d98efd | 2013-06-01 06:44:38 +0000 | [diff] [blame] | 602 | return 1; |
| 603 | |
| 604 | /* Zero, one or two bytes reg address (offset) */ |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 605 | omap_i2c_write_reg(i2c_base, ip_rev, alen, OMAP_I2C_CNT_REG); |
Lubomir Popov | 4d98efd | 2013-06-01 06:44:38 +0000 | [diff] [blame] | 606 | /* Set slave address */ |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 607 | omap_i2c_write_reg(i2c_base, ip_rev, chip, OMAP_I2C_SA_REG); |
Lubomir Popov | 4d98efd | 2013-06-01 06:44:38 +0000 | [diff] [blame] | 608 | |
| 609 | if (alen) { |
| 610 | /* Must write reg offset first */ |
| 611 | #ifdef CONFIG_I2C_REPEATED_START |
| 612 | /* No stop bit, use Repeated Start (Sr) */ |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 613 | omap_i2c_write_reg(i2c_base, ip_rev, I2C_CON_EN | I2C_CON_MST | |
| 614 | I2C_CON_STT | I2C_CON_TRX, OMAP_I2C_CON_REG); |
Lubomir Popov | 4d98efd | 2013-06-01 06:44:38 +0000 | [diff] [blame] | 615 | #else |
| 616 | /* Stop - Start (P-S) */ |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 617 | omap_i2c_write_reg(i2c_base, ip_rev, I2C_CON_EN | I2C_CON_MST | |
| 618 | I2C_CON_STT | I2C_CON_STP | I2C_CON_TRX, |
| 619 | OMAP_I2C_CON_REG); |
Lubomir Popov | 4d98efd | 2013-06-01 06:44:38 +0000 | [diff] [blame] | 620 | #endif |
| 621 | /* Send register offset */ |
| 622 | while (1) { |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 623 | status = wait_for_event(i2c_base, ip_rev, waitdelay); |
Lubomir Popov | 4d98efd | 2013-06-01 06:44:38 +0000 | [diff] [blame] | 624 | /* Try to identify bus that is not padconf'd for I2C */ |
| 625 | if (status == I2C_STAT_XRDY) { |
| 626 | i2c_error = 2; |
Mugunthan V N | 38d943a | 2016-07-18 15:11:00 +0530 | [diff] [blame] | 627 | printf("i2c_read (addr phase): pads on bus probably not configured (status=0x%x)\n", |
| 628 | status); |
Lubomir Popov | 4d98efd | 2013-06-01 06:44:38 +0000 | [diff] [blame] | 629 | goto rd_exit; |
| 630 | } |
Hannes Petermaier | d588505 | 2014-02-03 21:22:18 +0100 | [diff] [blame] | 631 | if (status == 0 || (status & I2C_STAT_NACK)) { |
Lubomir Popov | 4d98efd | 2013-06-01 06:44:38 +0000 | [diff] [blame] | 632 | i2c_error = 1; |
| 633 | printf("i2c_read: error waiting for addr ACK (status=0x%x)\n", |
| 634 | status); |
| 635 | goto rd_exit; |
| 636 | } |
| 637 | if (alen) { |
| 638 | if (status & I2C_STAT_XRDY) { |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 639 | u8 addr_byte; |
Lubomir Popov | 4d98efd | 2013-06-01 06:44:38 +0000 | [diff] [blame] | 640 | alen--; |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 641 | addr_byte = (addr >> (8 * alen)) & 0xff; |
| 642 | omap_i2c_write_reg(i2c_base, ip_rev, |
| 643 | addr_byte, |
| 644 | OMAP_I2C_DATA_REG); |
| 645 | omap_i2c_write_reg(i2c_base, ip_rev, |
| 646 | I2C_STAT_XRDY, |
| 647 | OMAP_I2C_STAT_REG); |
Lubomir Popov | 4d98efd | 2013-06-01 06:44:38 +0000 | [diff] [blame] | 648 | } |
| 649 | } |
| 650 | if (status & I2C_STAT_ARDY) { |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 651 | omap_i2c_write_reg(i2c_base, ip_rev, |
| 652 | I2C_STAT_ARDY, |
| 653 | OMAP_I2C_STAT_REG); |
Lubomir Popov | 4d98efd | 2013-06-01 06:44:38 +0000 | [diff] [blame] | 654 | break; |
| 655 | } |
wdenk | f806271 | 2005-01-09 23:16:25 +0000 | [diff] [blame] | 656 | } |
| 657 | } |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 658 | |
Lubomir Popov | 4d98efd | 2013-06-01 06:44:38 +0000 | [diff] [blame] | 659 | /* Set slave address */ |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 660 | omap_i2c_write_reg(i2c_base, ip_rev, chip, OMAP_I2C_SA_REG); |
Lubomir Popov | 4d98efd | 2013-06-01 06:44:38 +0000 | [diff] [blame] | 661 | /* Read len bytes from slave */ |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 662 | omap_i2c_write_reg(i2c_base, ip_rev, len, OMAP_I2C_CNT_REG); |
Lubomir Popov | 4d98efd | 2013-06-01 06:44:38 +0000 | [diff] [blame] | 663 | /* Need stop bit here */ |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 664 | omap_i2c_write_reg(i2c_base, ip_rev, I2C_CON_EN | I2C_CON_MST | |
| 665 | I2C_CON_STT | I2C_CON_STP, OMAP_I2C_CON_REG); |
wdenk | f806271 | 2005-01-09 23:16:25 +0000 | [diff] [blame] | 666 | |
Lubomir Popov | 4d98efd | 2013-06-01 06:44:38 +0000 | [diff] [blame] | 667 | /* Receive data */ |
| 668 | while (1) { |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 669 | status = wait_for_event(i2c_base, ip_rev, waitdelay); |
Lubomir Popov | 4d98efd | 2013-06-01 06:44:38 +0000 | [diff] [blame] | 670 | /* |
| 671 | * Try to identify bus that is not padconf'd for I2C. This |
| 672 | * state could be left over from previous transactions if |
| 673 | * the address phase is skipped due to alen=0. |
| 674 | */ |
| 675 | if (status == I2C_STAT_XRDY) { |
| 676 | i2c_error = 2; |
Mugunthan V N | 38d943a | 2016-07-18 15:11:00 +0530 | [diff] [blame] | 677 | printf("i2c_read (data phase): pads on bus probably not configured (status=0x%x)\n", |
| 678 | status); |
Lubomir Popov | 4d98efd | 2013-06-01 06:44:38 +0000 | [diff] [blame] | 679 | goto rd_exit; |
| 680 | } |
Hannes Petermaier | d588505 | 2014-02-03 21:22:18 +0100 | [diff] [blame] | 681 | if (status == 0 || (status & I2C_STAT_NACK)) { |
Lubomir Popov | 4d98efd | 2013-06-01 06:44:38 +0000 | [diff] [blame] | 682 | i2c_error = 1; |
| 683 | goto rd_exit; |
| 684 | } |
| 685 | if (status & I2C_STAT_RRDY) { |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 686 | *buffer++ = omap_i2c_read_reg(i2c_base, ip_rev, |
| 687 | OMAP_I2C_DATA_REG); |
| 688 | omap_i2c_write_reg(i2c_base, ip_rev, |
| 689 | I2C_STAT_RRDY, OMAP_I2C_STAT_REG); |
Lubomir Popov | 4d98efd | 2013-06-01 06:44:38 +0000 | [diff] [blame] | 690 | } |
| 691 | if (status & I2C_STAT_ARDY) { |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 692 | omap_i2c_write_reg(i2c_base, ip_rev, |
| 693 | I2C_STAT_ARDY, OMAP_I2C_STAT_REG); |
Lubomir Popov | 4d98efd | 2013-06-01 06:44:38 +0000 | [diff] [blame] | 694 | break; |
| 695 | } |
| 696 | } |
| 697 | |
| 698 | rd_exit: |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 699 | flush_fifo(i2c_base, ip_rev); |
| 700 | omap_i2c_write_reg(i2c_base, ip_rev, 0xFFFF, OMAP_I2C_STAT_REG); |
Lubomir Popov | 4d98efd | 2013-06-01 06:44:38 +0000 | [diff] [blame] | 701 | return i2c_error; |
wdenk | f806271 | 2005-01-09 23:16:25 +0000 | [diff] [blame] | 702 | } |
| 703 | |
Lubomir Popov | 4d98efd | 2013-06-01 06:44:38 +0000 | [diff] [blame] | 704 | /* i2c_write: Address (reg offset) may be 0, 1 or 2 bytes long. */ |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 705 | static int __omap24_i2c_write(void __iomem *i2c_base, int ip_rev, int waitdelay, |
| 706 | uchar chip, uint addr, int alen, uchar *buffer, |
| 707 | int len) |
wdenk | f806271 | 2005-01-09 23:16:25 +0000 | [diff] [blame] | 708 | { |
Tom Rini | 49fbf67 | 2012-02-20 18:49:16 +0000 | [diff] [blame] | 709 | int i; |
| 710 | u16 status; |
| 711 | int i2c_error = 0; |
Hannes Petermaier | d588505 | 2014-02-03 21:22:18 +0100 | [diff] [blame] | 712 | int timeout = I2C_TIMEOUT; |
Lubomir Popov | 4d98efd | 2013-06-01 06:44:38 +0000 | [diff] [blame] | 713 | |
| 714 | if (alen < 0) { |
| 715 | puts("I2C write: addr len < 0\n"); |
| 716 | return 1; |
| 717 | } |
| 718 | |
| 719 | if (len < 0) { |
| 720 | puts("I2C write: data len < 0\n"); |
| 721 | return 1; |
| 722 | } |
| 723 | |
| 724 | if (buffer == NULL) { |
| 725 | puts("I2C write: NULL pointer passed\n"); |
| 726 | return 1; |
| 727 | } |
wdenk | f806271 | 2005-01-09 23:16:25 +0000 | [diff] [blame] | 728 | |
Ilya Yanok | be6c2e4 | 2012-06-08 03:12:09 +0000 | [diff] [blame] | 729 | if (alen > 2) { |
Tom Rini | 49fbf67 | 2012-02-20 18:49:16 +0000 | [diff] [blame] | 730 | printf("I2C write: addr len %d not supported\n", alen); |
wdenk | f806271 | 2005-01-09 23:16:25 +0000 | [diff] [blame] | 731 | return 1; |
Tom Rini | 49fbf67 | 2012-02-20 18:49:16 +0000 | [diff] [blame] | 732 | } |
wdenk | f806271 | 2005-01-09 23:16:25 +0000 | [diff] [blame] | 733 | |
Ilya Yanok | be6c2e4 | 2012-06-08 03:12:09 +0000 | [diff] [blame] | 734 | if (addr + len > (1 << 16)) { |
Tom Rini | 49fbf67 | 2012-02-20 18:49:16 +0000 | [diff] [blame] | 735 | printf("I2C write: address 0x%x + 0x%x out of range\n", |
Lubomir Popov | 4d98efd | 2013-06-01 06:44:38 +0000 | [diff] [blame] | 736 | addr, len); |
wdenk | f806271 | 2005-01-09 23:16:25 +0000 | [diff] [blame] | 737 | return 1; |
| 738 | } |
| 739 | |
Guy Thouret | 51c2727 | 2016-03-11 16:23:41 +0000 | [diff] [blame] | 740 | #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW |
| 741 | /* |
| 742 | * EEPROM chips that implement "address overflow" are ones |
| 743 | * like Catalyst 24WC04/08/16 which has 9/10/11 bits of |
| 744 | * address and the extra bits end up in the "chip address" |
| 745 | * bit slots. This makes a 24WC08 (1Kbyte) chip look like |
| 746 | * four 256 byte chips. |
| 747 | * |
| 748 | * Note that we consider the length of the address field to |
| 749 | * still be one byte because the extra address bits are |
| 750 | * hidden in the chip address. |
| 751 | */ |
| 752 | if (alen > 0) |
| 753 | chip |= ((addr >> (alen * 8)) & |
| 754 | CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); |
| 755 | #endif |
| 756 | |
Lubomir Popov | 4d98efd | 2013-06-01 06:44:38 +0000 | [diff] [blame] | 757 | /* Wait until bus not busy */ |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 758 | if (wait_for_bb(i2c_base, ip_rev, waitdelay)) |
Vincent Stehlé | 33205e3 | 2012-12-03 05:23:16 +0000 | [diff] [blame] | 759 | return 1; |
Michael Jones | bb54d57 | 2011-09-04 14:01:55 -0400 | [diff] [blame] | 760 | |
Lubomir Popov | 4d98efd | 2013-06-01 06:44:38 +0000 | [diff] [blame] | 761 | /* Start address phase - will write regoffset + len bytes data */ |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 762 | omap_i2c_write_reg(i2c_base, ip_rev, alen + len, OMAP_I2C_CNT_REG); |
Lubomir Popov | 4d98efd | 2013-06-01 06:44:38 +0000 | [diff] [blame] | 763 | /* Set slave address */ |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 764 | omap_i2c_write_reg(i2c_base, ip_rev, chip, OMAP_I2C_SA_REG); |
Lubomir Popov | 4d98efd | 2013-06-01 06:44:38 +0000 | [diff] [blame] | 765 | /* Stop bit needed here */ |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 766 | omap_i2c_write_reg(i2c_base, ip_rev, I2C_CON_EN | I2C_CON_MST | |
| 767 | I2C_CON_STT | I2C_CON_TRX | I2C_CON_STP, |
| 768 | OMAP_I2C_CON_REG); |
Michael Jones | bb54d57 | 2011-09-04 14:01:55 -0400 | [diff] [blame] | 769 | |
Lubomir Popov | 4d98efd | 2013-06-01 06:44:38 +0000 | [diff] [blame] | 770 | while (alen) { |
| 771 | /* Must write reg offset (one or two bytes) */ |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 772 | status = wait_for_event(i2c_base, ip_rev, waitdelay); |
Lubomir Popov | 4d98efd | 2013-06-01 06:44:38 +0000 | [diff] [blame] | 773 | /* Try to identify bus that is not padconf'd for I2C */ |
| 774 | if (status == I2C_STAT_XRDY) { |
| 775 | i2c_error = 2; |
Mugunthan V N | 38d943a | 2016-07-18 15:11:00 +0530 | [diff] [blame] | 776 | printf("i2c_write: pads on bus probably not configured (status=0x%x)\n", |
| 777 | status); |
Lubomir Popov | 4d98efd | 2013-06-01 06:44:38 +0000 | [diff] [blame] | 778 | goto wr_exit; |
| 779 | } |
Hannes Petermaier | d588505 | 2014-02-03 21:22:18 +0100 | [diff] [blame] | 780 | if (status == 0 || (status & I2C_STAT_NACK)) { |
Tom Rini | 49fbf67 | 2012-02-20 18:49:16 +0000 | [diff] [blame] | 781 | i2c_error = 1; |
Lubomir Popov | 4d98efd | 2013-06-01 06:44:38 +0000 | [diff] [blame] | 782 | printf("i2c_write: error waiting for addr ACK (status=0x%x)\n", |
| 783 | status); |
| 784 | goto wr_exit; |
Tom Rini | 49fbf67 | 2012-02-20 18:49:16 +0000 | [diff] [blame] | 785 | } |
Tom Rini | 49fbf67 | 2012-02-20 18:49:16 +0000 | [diff] [blame] | 786 | if (status & I2C_STAT_XRDY) { |
Lubomir Popov | 4d98efd | 2013-06-01 06:44:38 +0000 | [diff] [blame] | 787 | alen--; |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 788 | omap_i2c_write_reg(i2c_base, ip_rev, |
| 789 | (addr >> (8 * alen)) & 0xff, |
| 790 | OMAP_I2C_DATA_REG); |
| 791 | omap_i2c_write_reg(i2c_base, ip_rev, |
| 792 | I2C_STAT_XRDY, OMAP_I2C_STAT_REG); |
Lubomir Popov | 4d98efd | 2013-06-01 06:44:38 +0000 | [diff] [blame] | 793 | } else { |
| 794 | i2c_error = 1; |
| 795 | printf("i2c_write: bus not ready for addr Tx (status=0x%x)\n", |
| 796 | status); |
| 797 | goto wr_exit; |
| 798 | } |
| 799 | } |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 800 | |
Lubomir Popov | 4d98efd | 2013-06-01 06:44:38 +0000 | [diff] [blame] | 801 | /* Address phase is over, now write data */ |
| 802 | for (i = 0; i < len; i++) { |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 803 | status = wait_for_event(i2c_base, ip_rev, waitdelay); |
Hannes Petermaier | d588505 | 2014-02-03 21:22:18 +0100 | [diff] [blame] | 804 | if (status == 0 || (status & I2C_STAT_NACK)) { |
Lubomir Popov | 4d98efd | 2013-06-01 06:44:38 +0000 | [diff] [blame] | 805 | i2c_error = 1; |
| 806 | printf("i2c_write: error waiting for data ACK (status=0x%x)\n", |
| 807 | status); |
| 808 | goto wr_exit; |
| 809 | } |
| 810 | if (status & I2C_STAT_XRDY) { |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 811 | omap_i2c_write_reg(i2c_base, ip_rev, |
| 812 | buffer[i], OMAP_I2C_DATA_REG); |
| 813 | omap_i2c_write_reg(i2c_base, ip_rev, |
| 814 | I2C_STAT_XRDY, OMAP_I2C_STAT_REG); |
Tom Rini | 49fbf67 | 2012-02-20 18:49:16 +0000 | [diff] [blame] | 815 | } else { |
| 816 | i2c_error = 1; |
Lubomir Popov | 4d98efd | 2013-06-01 06:44:38 +0000 | [diff] [blame] | 817 | printf("i2c_write: bus not ready for data Tx (i=%d)\n", |
| 818 | i); |
| 819 | goto wr_exit; |
Patil, Rachna | a9e18c2 | 2012-01-22 23:44:12 +0000 | [diff] [blame] | 820 | } |
| 821 | } |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 822 | |
Hannes Petermaier | d588505 | 2014-02-03 21:22:18 +0100 | [diff] [blame] | 823 | /* |
| 824 | * poll ARDY bit for making sure that last byte really has been |
| 825 | * transferred on the bus. |
| 826 | */ |
| 827 | do { |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 828 | status = wait_for_event(i2c_base, ip_rev, waitdelay); |
Hannes Petermaier | d588505 | 2014-02-03 21:22:18 +0100 | [diff] [blame] | 829 | } while (!(status & I2C_STAT_ARDY) && timeout--); |
| 830 | if (timeout <= 0) |
| 831 | printf("i2c_write: timed out writig last byte!\n"); |
Patil, Rachna | a9e18c2 | 2012-01-22 23:44:12 +0000 | [diff] [blame] | 832 | |
Lubomir Popov | 4d98efd | 2013-06-01 06:44:38 +0000 | [diff] [blame] | 833 | wr_exit: |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 834 | flush_fifo(i2c_base, ip_rev); |
| 835 | omap_i2c_write_reg(i2c_base, ip_rev, 0xFFFF, OMAP_I2C_STAT_REG); |
Tom Rini | 49fbf67 | 2012-02-20 18:49:16 +0000 | [diff] [blame] | 836 | return i2c_error; |
wdenk | f806271 | 2005-01-09 23:16:25 +0000 | [diff] [blame] | 837 | } |
| 838 | |
Igor Opaniuk | f7c9176 | 2021-02-09 13:52:45 +0200 | [diff] [blame] | 839 | #if !CONFIG_IS_ENABLED(DM_I2C) |
Lubomir Popov | 4d98efd | 2013-06-01 06:44:38 +0000 | [diff] [blame] | 840 | /* |
Mugunthan V N | 38d943a | 2016-07-18 15:11:00 +0530 | [diff] [blame] | 841 | * The legacy I2C functions. These need to get removed once |
| 842 | * all users of this driver are converted to DM. |
Lubomir Popov | 4d98efd | 2013-06-01 06:44:38 +0000 | [diff] [blame] | 843 | */ |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 844 | static void __iomem *omap24_get_base(struct i2c_adapter *adap) |
Dirk Behme | 7a8f657 | 2009-11-02 20:36:26 +0100 | [diff] [blame] | 845 | { |
Heiko Schocher | f53f2b8 | 2013-10-22 11:03:18 +0200 | [diff] [blame] | 846 | switch (adap->hwadapnr) { |
Lubomir Popov | 4d98efd | 2013-06-01 06:44:38 +0000 | [diff] [blame] | 847 | case 0: |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 848 | return (void __iomem *)I2C_BASE1; |
Lubomir Popov | 4d98efd | 2013-06-01 06:44:38 +0000 | [diff] [blame] | 849 | break; |
| 850 | case 1: |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 851 | return (void __iomem *)I2C_BASE2; |
Lubomir Popov | 4d98efd | 2013-06-01 06:44:38 +0000 | [diff] [blame] | 852 | break; |
Adam Ford | 73010ab | 2017-08-11 06:39:13 -0500 | [diff] [blame] | 853 | #if (CONFIG_SYS_I2C_BUS_MAX > 2) |
Lubomir Popov | 4d98efd | 2013-06-01 06:44:38 +0000 | [diff] [blame] | 854 | case 2: |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 855 | return (void __iomem *)I2C_BASE3; |
Lubomir Popov | 4d98efd | 2013-06-01 06:44:38 +0000 | [diff] [blame] | 856 | break; |
Adam Ford | 73010ab | 2017-08-11 06:39:13 -0500 | [diff] [blame] | 857 | #if (CONFIG_SYS_I2C_BUS_MAX > 3) |
Lubomir Popov | 4d98efd | 2013-06-01 06:44:38 +0000 | [diff] [blame] | 858 | case 3: |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 859 | return (void __iomem *)I2C_BASE4; |
Lubomir Popov | 4d98efd | 2013-06-01 06:44:38 +0000 | [diff] [blame] | 860 | break; |
Adam Ford | 73010ab | 2017-08-11 06:39:13 -0500 | [diff] [blame] | 861 | #if (CONFIG_SYS_I2C_BUS_MAX > 4) |
Lubomir Popov | 4d98efd | 2013-06-01 06:44:38 +0000 | [diff] [blame] | 862 | case 4: |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 863 | return (void __iomem *)I2C_BASE5; |
Lubomir Popov | 4d98efd | 2013-06-01 06:44:38 +0000 | [diff] [blame] | 864 | break; |
Koen Kooi | 584ff5f | 2012-08-08 00:57:35 +0000 | [diff] [blame] | 865 | #endif |
Dirk Behme | 7a8f657 | 2009-11-02 20:36:26 +0100 | [diff] [blame] | 866 | #endif |
Lubomir Popov | 4d98efd | 2013-06-01 06:44:38 +0000 | [diff] [blame] | 867 | #endif |
Heiko Schocher | f53f2b8 | 2013-10-22 11:03:18 +0200 | [diff] [blame] | 868 | default: |
| 869 | printf("wrong hwadapnr: %d\n", adap->hwadapnr); |
| 870 | break; |
Lubomir Popov | 4d98efd | 2013-06-01 06:44:38 +0000 | [diff] [blame] | 871 | } |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 872 | |
Heiko Schocher | f53f2b8 | 2013-10-22 11:03:18 +0200 | [diff] [blame] | 873 | return NULL; |
| 874 | } |
Dirk Behme | 7a8f657 | 2009-11-02 20:36:26 +0100 | [diff] [blame] | 875 | |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 876 | static int omap24_get_ip_rev(void) |
| 877 | { |
| 878 | #ifdef CONFIG_OMAP34XX |
| 879 | return OMAP_I2C_REV_V1; |
| 880 | #else |
| 881 | return OMAP_I2C_REV_V2; |
| 882 | #endif |
| 883 | } |
Mugunthan V N | 38d943a | 2016-07-18 15:11:00 +0530 | [diff] [blame] | 884 | |
| 885 | static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr, |
| 886 | int alen, uchar *buffer, int len) |
| 887 | { |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 888 | void __iomem *i2c_base = omap24_get_base(adap); |
| 889 | int ip_rev = omap24_get_ip_rev(); |
Mugunthan V N | 38d943a | 2016-07-18 15:11:00 +0530 | [diff] [blame] | 890 | |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 891 | return __omap24_i2c_read(i2c_base, ip_rev, adap->waitdelay, chip, addr, |
Mugunthan V N | 38d943a | 2016-07-18 15:11:00 +0530 | [diff] [blame] | 892 | alen, buffer, len); |
| 893 | } |
| 894 | |
Mugunthan V N | 38d943a | 2016-07-18 15:11:00 +0530 | [diff] [blame] | 895 | static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr, |
| 896 | int alen, uchar *buffer, int len) |
| 897 | { |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 898 | void __iomem *i2c_base = omap24_get_base(adap); |
| 899 | int ip_rev = omap24_get_ip_rev(); |
Mugunthan V N | 38d943a | 2016-07-18 15:11:00 +0530 | [diff] [blame] | 900 | |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 901 | return __omap24_i2c_write(i2c_base, ip_rev, adap->waitdelay, chip, addr, |
Mugunthan V N | 38d943a | 2016-07-18 15:11:00 +0530 | [diff] [blame] | 902 | alen, buffer, len); |
| 903 | } |
| 904 | |
| 905 | static uint omap24_i2c_setspeed(struct i2c_adapter *adap, uint speed) |
| 906 | { |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 907 | void __iomem *i2c_base = omap24_get_base(adap); |
| 908 | int ip_rev = omap24_get_ip_rev(); |
Mugunthan V N | 38d943a | 2016-07-18 15:11:00 +0530 | [diff] [blame] | 909 | int ret; |
| 910 | |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 911 | ret = __omap24_i2c_setspeed(i2c_base, ip_rev, speed, &adap->waitdelay); |
Mugunthan V N | 38d943a | 2016-07-18 15:11:00 +0530 | [diff] [blame] | 912 | if (ret) { |
Masahiro Yamada | 81e1042 | 2017-09-16 14:10:41 +0900 | [diff] [blame] | 913 | pr_err("%s: set i2c speed failed\n", __func__); |
Mugunthan V N | 38d943a | 2016-07-18 15:11:00 +0530 | [diff] [blame] | 914 | return ret; |
| 915 | } |
| 916 | |
| 917 | adap->speed = speed; |
| 918 | |
| 919 | return 0; |
| 920 | } |
| 921 | |
| 922 | static void omap24_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd) |
| 923 | { |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 924 | void __iomem *i2c_base = omap24_get_base(adap); |
| 925 | int ip_rev = omap24_get_ip_rev(); |
Mugunthan V N | 38d943a | 2016-07-18 15:11:00 +0530 | [diff] [blame] | 926 | |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 927 | return __omap24_i2c_init(i2c_base, ip_rev, speed, slaveadd, |
| 928 | &adap->waitdelay); |
Mugunthan V N | 38d943a | 2016-07-18 15:11:00 +0530 | [diff] [blame] | 929 | } |
| 930 | |
| 931 | static int omap24_i2c_probe(struct i2c_adapter *adap, uchar chip) |
| 932 | { |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 933 | void __iomem *i2c_base = omap24_get_base(adap); |
| 934 | int ip_rev = omap24_get_ip_rev(); |
Mugunthan V N | 38d943a | 2016-07-18 15:11:00 +0530 | [diff] [blame] | 935 | |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 936 | return __omap24_i2c_probe(i2c_base, ip_rev, adap->waitdelay, chip); |
Mugunthan V N | 38d943a | 2016-07-18 15:11:00 +0530 | [diff] [blame] | 937 | } |
| 938 | |
Heiko Schocher | f53f2b8 | 2013-10-22 11:03:18 +0200 | [diff] [blame] | 939 | U_BOOT_I2C_ADAP_COMPLETE(omap24_0, omap24_i2c_init, omap24_i2c_probe, |
Hannes Petermaier | d588505 | 2014-02-03 21:22:18 +0100 | [diff] [blame] | 940 | omap24_i2c_read, omap24_i2c_write, omap24_i2c_setspeed, |
Tom Rini | a7a9bc0 | 2021-08-18 23:12:29 -0400 | [diff] [blame] | 941 | CONFIG_SYS_I2C_SPEED, |
| 942 | CONFIG_SYS_I2C_SLAVE, |
Heiko Schocher | f53f2b8 | 2013-10-22 11:03:18 +0200 | [diff] [blame] | 943 | 0) |
| 944 | U_BOOT_I2C_ADAP_COMPLETE(omap24_1, omap24_i2c_init, omap24_i2c_probe, |
Hannes Petermaier | d588505 | 2014-02-03 21:22:18 +0100 | [diff] [blame] | 945 | omap24_i2c_read, omap24_i2c_write, omap24_i2c_setspeed, |
Tom Rini | a7a9bc0 | 2021-08-18 23:12:29 -0400 | [diff] [blame] | 946 | CONFIG_SYS_I2C_SPEED, |
| 947 | CONFIG_SYS_I2C_SLAVE, |
Heiko Schocher | f53f2b8 | 2013-10-22 11:03:18 +0200 | [diff] [blame] | 948 | 1) |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 949 | |
Adam Ford | 73010ab | 2017-08-11 06:39:13 -0500 | [diff] [blame] | 950 | #if (CONFIG_SYS_I2C_BUS_MAX > 2) |
Heiko Schocher | f53f2b8 | 2013-10-22 11:03:18 +0200 | [diff] [blame] | 951 | U_BOOT_I2C_ADAP_COMPLETE(omap24_2, omap24_i2c_init, omap24_i2c_probe, |
| 952 | omap24_i2c_read, omap24_i2c_write, NULL, |
Tom Rini | a7a9bc0 | 2021-08-18 23:12:29 -0400 | [diff] [blame] | 953 | CONFIG_SYS_I2C_SPEED, |
| 954 | CONFIG_SYS_I2C_SLAVE, |
Heiko Schocher | f53f2b8 | 2013-10-22 11:03:18 +0200 | [diff] [blame] | 955 | 2) |
Adam Ford | 73010ab | 2017-08-11 06:39:13 -0500 | [diff] [blame] | 956 | #if (CONFIG_SYS_I2C_BUS_MAX > 3) |
Heiko Schocher | f53f2b8 | 2013-10-22 11:03:18 +0200 | [diff] [blame] | 957 | U_BOOT_I2C_ADAP_COMPLETE(omap24_3, omap24_i2c_init, omap24_i2c_probe, |
| 958 | omap24_i2c_read, omap24_i2c_write, NULL, |
Tom Rini | a7a9bc0 | 2021-08-18 23:12:29 -0400 | [diff] [blame] | 959 | CONFIG_SYS_I2C_SPEED, |
| 960 | CONFIG_SYS_I2C_SLAVE, |
Heiko Schocher | f53f2b8 | 2013-10-22 11:03:18 +0200 | [diff] [blame] | 961 | 3) |
Adam Ford | 73010ab | 2017-08-11 06:39:13 -0500 | [diff] [blame] | 962 | #if (CONFIG_SYS_I2C_BUS_MAX > 4) |
Heiko Schocher | f53f2b8 | 2013-10-22 11:03:18 +0200 | [diff] [blame] | 963 | U_BOOT_I2C_ADAP_COMPLETE(omap24_4, omap24_i2c_init, omap24_i2c_probe, |
| 964 | omap24_i2c_read, omap24_i2c_write, NULL, |
Tom Rini | a7a9bc0 | 2021-08-18 23:12:29 -0400 | [diff] [blame] | 965 | CONFIG_SYS_I2C_SPEED, |
| 966 | CONFIG_SYS_I2C_SLAVE, |
Heiko Schocher | f53f2b8 | 2013-10-22 11:03:18 +0200 | [diff] [blame] | 967 | 4) |
| 968 | #endif |
| 969 | #endif |
| 970 | #endif |
Mugunthan V N | 560037b | 2016-07-18 15:11:01 +0530 | [diff] [blame] | 971 | |
| 972 | #else /* CONFIG_DM_I2C */ |
| 973 | |
| 974 | static int omap_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs) |
| 975 | { |
| 976 | struct omap_i2c *priv = dev_get_priv(bus); |
| 977 | int ret; |
| 978 | |
| 979 | debug("i2c_xfer: %d messages\n", nmsgs); |
| 980 | for (; nmsgs > 0; nmsgs--, msg++) { |
| 981 | debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len); |
| 982 | if (msg->flags & I2C_M_RD) { |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 983 | ret = __omap24_i2c_read(priv->regs, priv->ip_rev, |
| 984 | priv->waitdelay, |
Mugunthan V N | 560037b | 2016-07-18 15:11:01 +0530 | [diff] [blame] | 985 | msg->addr, 0, 0, msg->buf, |
| 986 | msg->len); |
| 987 | } else { |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 988 | ret = __omap24_i2c_write(priv->regs, priv->ip_rev, |
| 989 | priv->waitdelay, |
Mugunthan V N | 560037b | 2016-07-18 15:11:01 +0530 | [diff] [blame] | 990 | msg->addr, 0, 0, msg->buf, |
| 991 | msg->len); |
| 992 | } |
| 993 | if (ret) { |
| 994 | debug("i2c_write: error sending\n"); |
| 995 | return -EREMOTEIO; |
| 996 | } |
| 997 | } |
| 998 | |
| 999 | return 0; |
| 1000 | } |
| 1001 | |
| 1002 | static int omap_i2c_set_bus_speed(struct udevice *bus, unsigned int speed) |
| 1003 | { |
| 1004 | struct omap_i2c *priv = dev_get_priv(bus); |
| 1005 | |
| 1006 | priv->speed = speed; |
| 1007 | |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 1008 | return __omap24_i2c_setspeed(priv->regs, priv->ip_rev, speed, |
| 1009 | &priv->waitdelay); |
Mugunthan V N | 560037b | 2016-07-18 15:11:01 +0530 | [diff] [blame] | 1010 | } |
| 1011 | |
| 1012 | static int omap_i2c_probe_chip(struct udevice *bus, uint chip_addr, |
| 1013 | uint chip_flags) |
| 1014 | { |
| 1015 | struct omap_i2c *priv = dev_get_priv(bus); |
| 1016 | |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 1017 | return __omap24_i2c_probe(priv->regs, priv->ip_rev, priv->waitdelay, |
Nikita Yushchenko | 83f3f8b | 2022-02-15 21:10:09 +0300 | [diff] [blame] | 1018 | chip_addr) ? -EREMOTEIO : 0; |
Mugunthan V N | 560037b | 2016-07-18 15:11:01 +0530 | [diff] [blame] | 1019 | } |
| 1020 | |
| 1021 | static int omap_i2c_probe(struct udevice *bus) |
| 1022 | { |
| 1023 | struct omap_i2c *priv = dev_get_priv(bus); |
Simon Glass | b75b15b | 2020-12-03 16:55:23 -0700 | [diff] [blame] | 1024 | struct omap_i2c_plat *plat = dev_get_plat(bus); |
Mugunthan V N | 560037b | 2016-07-18 15:11:01 +0530 | [diff] [blame] | 1025 | |
Jean-Jacques Hiblot | 58994fc | 2018-12-07 14:50:42 +0100 | [diff] [blame] | 1026 | priv->speed = plat->speed; |
| 1027 | priv->regs = map_physmem(plat->base, sizeof(void *), |
| 1028 | MAP_NOCACHE); |
| 1029 | priv->ip_rev = plat->ip_rev; |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 1030 | |
| 1031 | __omap24_i2c_init(priv->regs, priv->ip_rev, priv->speed, 0, |
| 1032 | &priv->waitdelay); |
Mugunthan V N | 560037b | 2016-07-18 15:11:01 +0530 | [diff] [blame] | 1033 | |
| 1034 | return 0; |
| 1035 | } |
| 1036 | |
Simon Glass | 3580f6d | 2021-08-07 07:24:03 -0600 | [diff] [blame] | 1037 | #if CONFIG_IS_ENABLED(OF_REAL) |
Simon Glass | aad29ae | 2020-12-03 16:55:21 -0700 | [diff] [blame] | 1038 | static int omap_i2c_of_to_plat(struct udevice *bus) |
Mugunthan V N | 560037b | 2016-07-18 15:11:01 +0530 | [diff] [blame] | 1039 | { |
Simon Glass | b75b15b | 2020-12-03 16:55:23 -0700 | [diff] [blame] | 1040 | struct omap_i2c_plat *plat = dev_get_plat(bus); |
Mugunthan V N | 560037b | 2016-07-18 15:11:01 +0530 | [diff] [blame] | 1041 | |
Masahiro Yamada | a89b4de | 2020-07-17 14:36:48 +0900 | [diff] [blame] | 1042 | plat->base = dev_read_addr(bus); |
Simon Glass | f0c99c5 | 2020-01-23 11:48:22 -0700 | [diff] [blame] | 1043 | plat->speed = dev_read_u32_default(bus, "clock-frequency", |
| 1044 | I2C_SPEED_STANDARD_RATE); |
Jean-Jacques Hiblot | 58994fc | 2018-12-07 14:50:42 +0100 | [diff] [blame] | 1045 | plat->ip_rev = dev_get_driver_data(bus); |
Mugunthan V N | 560037b | 2016-07-18 15:11:01 +0530 | [diff] [blame] | 1046 | |
| 1047 | return 0; |
| 1048 | } |
| 1049 | |
Mugunthan V N | 560037b | 2016-07-18 15:11:01 +0530 | [diff] [blame] | 1050 | static const struct udevice_id omap_i2c_ids[] = { |
Vignesh R | 3f51de3 | 2018-12-07 14:50:41 +0100 | [diff] [blame] | 1051 | { .compatible = "ti,omap3-i2c", .data = OMAP_I2C_REV_V1 }, |
| 1052 | { .compatible = "ti,omap4-i2c", .data = OMAP_I2C_REV_V2 }, |
Mugunthan V N | 560037b | 2016-07-18 15:11:01 +0530 | [diff] [blame] | 1053 | { } |
| 1054 | }; |
Adam Ford | 1f09846 | 2018-08-20 20:24:35 -0500 | [diff] [blame] | 1055 | #endif |
| 1056 | |
| 1057 | static const struct dm_i2c_ops omap_i2c_ops = { |
| 1058 | .xfer = omap_i2c_xfer, |
| 1059 | .probe_chip = omap_i2c_probe_chip, |
| 1060 | .set_bus_speed = omap_i2c_set_bus_speed, |
| 1061 | }; |
Mugunthan V N | 560037b | 2016-07-18 15:11:01 +0530 | [diff] [blame] | 1062 | |
| 1063 | U_BOOT_DRIVER(i2c_omap) = { |
| 1064 | .name = "i2c_omap", |
| 1065 | .id = UCLASS_I2C, |
Simon Glass | 3580f6d | 2021-08-07 07:24:03 -0600 | [diff] [blame] | 1066 | #if CONFIG_IS_ENABLED(OF_REAL) |
Mugunthan V N | 560037b | 2016-07-18 15:11:01 +0530 | [diff] [blame] | 1067 | .of_match = omap_i2c_ids, |
Simon Glass | aad29ae | 2020-12-03 16:55:21 -0700 | [diff] [blame] | 1068 | .of_to_plat = omap_i2c_of_to_plat, |
Simon Glass | b75b15b | 2020-12-03 16:55:23 -0700 | [diff] [blame] | 1069 | .plat_auto = sizeof(struct omap_i2c_plat), |
Adam Ford | 1f09846 | 2018-08-20 20:24:35 -0500 | [diff] [blame] | 1070 | #endif |
Mugunthan V N | 560037b | 2016-07-18 15:11:01 +0530 | [diff] [blame] | 1071 | .probe = omap_i2c_probe, |
Simon Glass | 8a2b47f | 2020-12-03 16:55:17 -0700 | [diff] [blame] | 1072 | .priv_auto = sizeof(struct omap_i2c), |
Mugunthan V N | 560037b | 2016-07-18 15:11:01 +0530 | [diff] [blame] | 1073 | .ops = &omap_i2c_ops, |
Bin Meng | a61b962 | 2018-10-24 06:36:31 -0700 | [diff] [blame] | 1074 | #if !CONFIG_IS_ENABLED(OF_CONTROL) |
Mugunthan V N | 560037b | 2016-07-18 15:11:01 +0530 | [diff] [blame] | 1075 | .flags = DM_FLAG_PRE_RELOC, |
Bin Meng | a61b962 | 2018-10-24 06:36:31 -0700 | [diff] [blame] | 1076 | #endif |
Mugunthan V N | 560037b | 2016-07-18 15:11:01 +0530 | [diff] [blame] | 1077 | }; |
| 1078 | |
| 1079 | #endif /* CONFIG_DM_I2C */ |