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wdenkf8062712005-01-09 23:16:25 +00001/*
2 * Basic I2C functions
3 *
4 * Copyright (c) 2004 Texas Instruments
5 *
6 * This package is free software; you can redistribute it and/or
7 * modify it under the terms of the license found in the file
8 * named COPYING that should have accompanied this file.
9 *
10 * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
11 * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
12 * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
13 *
14 * Author: Jian Zhang jzhang@ti.com, Texas Instruments
15 *
16 * Copyright (c) 2003 Wolfgang Denk, wd@denx.de
17 * Rewritten to fit into the current U-Boot framework
18 *
19 * Adapted for OMAP2420 I2C, r-woodruff2@ti.com
20 *
Lubomir Popov4d98efd2013-06-01 06:44:38 +000021 * Copyright (c) 2013 Lubomir Popov <lpopov@mm-sol.com>, MM Solutions
22 * New i2c_read, i2c_write and i2c_probe functions, tested on OMAP4
23 * (4430/60/70), OMAP5 (5430) and AM335X (3359); should work on older
24 * OMAPs and derivatives as well. The only anticipated exception would
25 * be the OMAP2420, which shall require driver modification.
26 * - Rewritten i2c_read to operate correctly with all types of chips
27 * (old function could not read consistent data from some I2C slaves).
28 * - Optimized i2c_write.
29 * - New i2c_probe, performs write access vs read. The old probe could
30 * hang the system under certain conditions (e.g. unconfigured pads).
31 * - The read/write/probe functions try to identify unconfigured bus.
32 * - Status functions now read irqstatus_raw as per TRM guidelines
33 * (except for OMAP243X and OMAP34XX).
34 * - Driver now supports up to I2C5 (OMAP5).
Hannes Petermaierd5885052014-02-03 21:22:18 +010035 *
Hannes Schmelzer7935f032015-05-28 15:41:12 +020036 * Copyright (c) 2014 Hannes Schmelzer <oe5hpm@oevsv.at>, B&R
Hannes Petermaierd5885052014-02-03 21:22:18 +010037 * - Added support for set_speed
38 *
wdenkf8062712005-01-09 23:16:25 +000039 */
40
41#include <common.h>
Mugunthan V N560037b2016-07-18 15:11:01 +053042#include <dm.h>
Heiko Schocherf53f2b82013-10-22 11:03:18 +020043#include <i2c.h>
Simon Glass0f2af882020-05-10 11:40:05 -060044#include <log.h>
Simon Glassdbd79542020-05-10 11:40:11 -060045#include <linux/delay.h>
wdenkcb99da52005-01-12 00:15:14 +000046
wdenkf8062712005-01-09 23:16:25 +000047#include <asm/io.h>
Jean-Jacques Hiblot58994fc2018-12-07 14:50:42 +010048#include <asm/omap_i2c.h>
wdenkf8062712005-01-09 23:16:25 +000049
Vignesh R3f51de32018-12-07 14:50:41 +010050/*
51 * Provide access to architecture-specific I2C header files for platforms
52 * that are NOT yet solely relying on CONFIG_DM_I2C, CONFIG_OF_CONTROL, and
53 * the defaults provided in 'omap24xx_i2c.h' for all U-Boot stages where I2C
54 * access is desired.
55 */
56#ifndef CONFIG_ARCH_K3
57#include <asm/arch/i2c.h>
58#endif
59
Steve Sakoman10acc712010-06-12 06:42:57 -070060#include "omap24xx_i2c.h"
61
Tom Rini49fbf672012-02-20 18:49:16 +000062#define I2C_TIMEOUT 1000
Steve Sakomane2bdc132010-07-19 20:31:55 -070063
Lubomir Popov4d98efd2013-06-01 06:44:38 +000064/* Absolutely safe for status update at 100 kHz I2C: */
65#define I2C_WAIT 200
66
Vignesh R3f51de32018-12-07 14:50:41 +010067enum {
Vignesh R3f51de32018-12-07 14:50:41 +010068 OMAP_I2C_REV_REG = 0, /* Only on IP V1 (OMAP34XX) */
69 OMAP_I2C_IE_REG, /* Only on IP V1 (OMAP34XX) */
70 OMAP_I2C_STAT_REG,
71 OMAP_I2C_WE_REG,
72 OMAP_I2C_SYSS_REG,
73 OMAP_I2C_BUF_REG,
74 OMAP_I2C_CNT_REG,
75 OMAP_I2C_DATA_REG,
76 OMAP_I2C_SYSC_REG,
77 OMAP_I2C_CON_REG,
78 OMAP_I2C_OA_REG,
79 OMAP_I2C_SA_REG,
80 OMAP_I2C_PSC_REG,
81 OMAP_I2C_SCLL_REG,
82 OMAP_I2C_SCLH_REG,
83 OMAP_I2C_SYSTEST_REG,
84 OMAP_I2C_BUFSTAT_REG,
85 /* Only on IP V2 (OMAP4430, etc.) */
86 OMAP_I2C_IP_V2_REVNB_LO,
87 OMAP_I2C_IP_V2_REVNB_HI,
88 OMAP_I2C_IP_V2_IRQSTATUS_RAW,
89 OMAP_I2C_IP_V2_IRQENABLE_SET,
90 OMAP_I2C_IP_V2_IRQENABLE_CLR,
91};
92
93static const u8 __maybe_unused reg_map_ip_v1[] = {
94 [OMAP_I2C_REV_REG] = 0x00,
95 [OMAP_I2C_IE_REG] = 0x04,
96 [OMAP_I2C_STAT_REG] = 0x08,
97 [OMAP_I2C_WE_REG] = 0x0c,
98 [OMAP_I2C_SYSS_REG] = 0x10,
99 [OMAP_I2C_BUF_REG] = 0x14,
100 [OMAP_I2C_CNT_REG] = 0x18,
101 [OMAP_I2C_DATA_REG] = 0x1c,
102 [OMAP_I2C_SYSC_REG] = 0x20,
103 [OMAP_I2C_CON_REG] = 0x24,
104 [OMAP_I2C_OA_REG] = 0x28,
105 [OMAP_I2C_SA_REG] = 0x2c,
106 [OMAP_I2C_PSC_REG] = 0x30,
107 [OMAP_I2C_SCLL_REG] = 0x34,
108 [OMAP_I2C_SCLH_REG] = 0x38,
109 [OMAP_I2C_SYSTEST_REG] = 0x3c,
110 [OMAP_I2C_BUFSTAT_REG] = 0x40,
111};
112
113static const u8 __maybe_unused reg_map_ip_v2[] = {
114 [OMAP_I2C_STAT_REG] = 0x28,
115 [OMAP_I2C_WE_REG] = 0x34,
116 [OMAP_I2C_SYSS_REG] = 0x90,
117 [OMAP_I2C_BUF_REG] = 0x94,
118 [OMAP_I2C_CNT_REG] = 0x98,
119 [OMAP_I2C_DATA_REG] = 0x9c,
120 [OMAP_I2C_SYSC_REG] = 0x10,
121 [OMAP_I2C_CON_REG] = 0xa4,
122 [OMAP_I2C_OA_REG] = 0xa8,
123 [OMAP_I2C_SA_REG] = 0xac,
124 [OMAP_I2C_PSC_REG] = 0xb0,
125 [OMAP_I2C_SCLL_REG] = 0xb4,
126 [OMAP_I2C_SCLH_REG] = 0xb8,
127 [OMAP_I2C_SYSTEST_REG] = 0xbc,
128 [OMAP_I2C_BUFSTAT_REG] = 0xc0,
129 [OMAP_I2C_IP_V2_REVNB_LO] = 0x00,
130 [OMAP_I2C_IP_V2_REVNB_HI] = 0x04,
131 [OMAP_I2C_IP_V2_IRQSTATUS_RAW] = 0x24,
132 [OMAP_I2C_IP_V2_IRQENABLE_SET] = 0x2c,
133 [OMAP_I2C_IP_V2_IRQENABLE_CLR] = 0x30,
134};
135
Mugunthan V N560037b2016-07-18 15:11:01 +0530136struct omap_i2c {
137 struct udevice *clk;
Vignesh R3f51de32018-12-07 14:50:41 +0100138 int ip_rev;
Mugunthan V N560037b2016-07-18 15:11:01 +0530139 struct i2c *regs;
140 unsigned int speed;
141 int waitdelay;
142 int clk_id;
143};
144
Vignesh R3f51de32018-12-07 14:50:41 +0100145static inline const u8 *omap_i2c_get_ip_reg_map(int ip_rev)
146{
147 switch (ip_rev) {
148 case OMAP_I2C_REV_V1:
149 return reg_map_ip_v1;
150 case OMAP_I2C_REV_V2:
151 /* Fall through... */
152 default:
153 return reg_map_ip_v2;
154 }
155}
156
157static inline void omap_i2c_write_reg(void __iomem *base, int ip_rev,
158 u16 val, int reg)
159{
160 writew(val, base + omap_i2c_get_ip_reg_map(ip_rev)[reg]);
161}
162
163static inline u16 omap_i2c_read_reg(void __iomem *base, int ip_rev, int reg)
164{
165 return readw(base + omap_i2c_get_ip_reg_map(ip_rev)[reg]);
166}
167
Hannes Petermaierd5885052014-02-03 21:22:18 +0100168static int omap24_i2c_findpsc(u32 *pscl, u32 *psch, uint speed)
wdenkf8062712005-01-09 23:16:25 +0000169{
Lukasz Majewski698a9ba2017-03-15 16:59:23 +0100170 unsigned long internal_clk = 0, fclk;
171 unsigned int prescaler;
Tom Rix03b2a742009-06-28 12:52:27 -0500172
Hannes Petermaierd5885052014-02-03 21:22:18 +0100173 /*
Lukasz Majewski698a9ba2017-03-15 16:59:23 +0100174 * This method is only called for Standard and Fast Mode speeds
175 *
176 * For some TI SoCs it is explicitly written in TRM (e,g, SPRUHZ6G,
177 * page 5685, Table 24-7)
178 * that the internal I2C clock (after prescaler) should be between
179 * 7-12 MHz (at least for Fast Mode (FS)).
180 *
181 * Such approach is used in v4.9 Linux kernel in:
182 * ./drivers/i2c/busses/i2c-omap.c (omap_i2c_init function).
Hannes Petermaierd5885052014-02-03 21:22:18 +0100183 */
Tom Rix03b2a742009-06-28 12:52:27 -0500184
Lukasz Majewski698a9ba2017-03-15 16:59:23 +0100185 speed /= 1000; /* convert speed to kHz */
Hannes Petermaierd5885052014-02-03 21:22:18 +0100186
Lukasz Majewski698a9ba2017-03-15 16:59:23 +0100187 if (speed > 100)
188 internal_clk = 9600;
189 else
190 internal_clk = 4000;
Hannes Petermaierd5885052014-02-03 21:22:18 +0100191
Lukasz Majewski698a9ba2017-03-15 16:59:23 +0100192 fclk = I2C_IP_CLK / 1000;
193 prescaler = fclk / internal_clk;
194 prescaler = prescaler - 1;
195
196 if (speed > 100) {
197 unsigned long scl;
198
199 /* Fast mode */
200 scl = internal_clk / speed;
201 *pscl = scl - (scl / 3) - I2C_FASTSPEED_SCLL_TRIM;
202 *psch = (scl / 3) - I2C_FASTSPEED_SCLH_TRIM;
203 } else {
204 /* Standard mode */
205 *pscl = internal_clk / (speed * 2) - I2C_FASTSPEED_SCLL_TRIM;
206 *psch = internal_clk / (speed * 2) - I2C_FASTSPEED_SCLH_TRIM;
Tom Rix03b2a742009-06-28 12:52:27 -0500207 }
Lukasz Majewski698a9ba2017-03-15 16:59:23 +0100208
209 debug("%s: speed [kHz]: %d psc: 0x%x sscl: 0x%x ssch: 0x%x\n",
210 __func__, speed, prescaler, *pscl, *psch);
211
212 if (*pscl <= 0 || *psch <= 0 || prescaler <= 0)
213 return -EINVAL;
214
215 return prescaler;
Hannes Petermaierd5885052014-02-03 21:22:18 +0100216}
Mugunthan V N38d943a2016-07-18 15:11:00 +0530217
218/*
219 * Wait for the bus to be free by checking the Bus Busy (BB)
220 * bit to become clear
221 */
Vignesh R3f51de32018-12-07 14:50:41 +0100222static int wait_for_bb(void __iomem *i2c_base, int ip_rev, int waitdelay)
Hannes Petermaierd5885052014-02-03 21:22:18 +0100223{
Mugunthan V N38d943a2016-07-18 15:11:00 +0530224 int timeout = I2C_TIMEOUT;
Vignesh R3f51de32018-12-07 14:50:41 +0100225 int irq_stat_reg;
Mugunthan V N38d943a2016-07-18 15:11:00 +0530226 u16 stat;
227
Vignesh R3f51de32018-12-07 14:50:41 +0100228 irq_stat_reg = (ip_rev == OMAP_I2C_REV_V1) ?
229 OMAP_I2C_STAT_REG : OMAP_I2C_IP_V2_IRQSTATUS_RAW;
230
231 /* clear current interrupts */
232 omap_i2c_write_reg(i2c_base, ip_rev, 0xFFFF, OMAP_I2C_STAT_REG);
233
234 while ((stat = omap_i2c_read_reg(i2c_base, ip_rev, irq_stat_reg) &
Mugunthan V N38d943a2016-07-18 15:11:00 +0530235 I2C_STAT_BB) && timeout--) {
Vignesh R3f51de32018-12-07 14:50:41 +0100236 omap_i2c_write_reg(i2c_base, ip_rev, stat, OMAP_I2C_STAT_REG);
Mugunthan V N38d943a2016-07-18 15:11:00 +0530237 udelay(waitdelay);
238 }
239
240 if (timeout <= 0) {
Vignesh R3f51de32018-12-07 14:50:41 +0100241 printf("Timed out in %s: status=%04x\n", __func__, stat);
Mugunthan V N38d943a2016-07-18 15:11:00 +0530242 return 1;
243 }
Vignesh R3f51de32018-12-07 14:50:41 +0100244
245 /* clear delayed stuff */
246 omap_i2c_write_reg(i2c_base, ip_rev, 0xFFFF, OMAP_I2C_STAT_REG);
Mugunthan V N38d943a2016-07-18 15:11:00 +0530247 return 0;
248}
249
250/*
251 * Wait for the I2C controller to complete current action
252 * and update status
253 */
Vignesh R3f51de32018-12-07 14:50:41 +0100254static u16 wait_for_event(void __iomem *i2c_base, int ip_rev, int waitdelay)
Mugunthan V N38d943a2016-07-18 15:11:00 +0530255{
256 u16 status;
257 int timeout = I2C_TIMEOUT;
Vignesh R3f51de32018-12-07 14:50:41 +0100258 int irq_stat_reg;
Mugunthan V N38d943a2016-07-18 15:11:00 +0530259
Vignesh R3f51de32018-12-07 14:50:41 +0100260 irq_stat_reg = (ip_rev == OMAP_I2C_REV_V1) ?
261 OMAP_I2C_STAT_REG : OMAP_I2C_IP_V2_IRQSTATUS_RAW;
Mugunthan V N38d943a2016-07-18 15:11:00 +0530262 do {
263 udelay(waitdelay);
Vignesh R3f51de32018-12-07 14:50:41 +0100264 status = omap_i2c_read_reg(i2c_base, ip_rev, irq_stat_reg);
Mugunthan V N38d943a2016-07-18 15:11:00 +0530265 } while (!(status &
266 (I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY |
267 I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK |
268 I2C_STAT_AL)) && timeout--);
269
270 if (timeout <= 0) {
Vignesh R3f51de32018-12-07 14:50:41 +0100271 printf("Timed out in %s: status=%04x\n", __func__, status);
Mugunthan V N38d943a2016-07-18 15:11:00 +0530272 /*
273 * If status is still 0 here, probably the bus pads have
274 * not been configured for I2C, and/or pull-ups are missing.
275 */
276 printf("Check if pads/pull-ups of bus are properly configured\n");
Vignesh R3f51de32018-12-07 14:50:41 +0100277 omap_i2c_write_reg(i2c_base, ip_rev, 0xFFFF, OMAP_I2C_STAT_REG);
Mugunthan V N38d943a2016-07-18 15:11:00 +0530278 status = 0;
279 }
280
281 return status;
282}
283
Vignesh R3f51de32018-12-07 14:50:41 +0100284static void flush_fifo(void __iomem *i2c_base, int ip_rev)
Mugunthan V N38d943a2016-07-18 15:11:00 +0530285{
286 u16 stat;
287
288 /*
289 * note: if you try and read data when its not there or ready
290 * you get a bus error
291 */
292 while (1) {
Vignesh R3f51de32018-12-07 14:50:41 +0100293 stat = omap_i2c_read_reg(i2c_base, ip_rev, OMAP_I2C_STAT_REG);
Mugunthan V N38d943a2016-07-18 15:11:00 +0530294 if (stat == I2C_STAT_RRDY) {
Vignesh R3f51de32018-12-07 14:50:41 +0100295 omap_i2c_read_reg(i2c_base, ip_rev, OMAP_I2C_DATA_REG);
296 omap_i2c_write_reg(i2c_base, ip_rev,
297 I2C_STAT_RRDY, OMAP_I2C_STAT_REG);
Mugunthan V N38d943a2016-07-18 15:11:00 +0530298 udelay(1000);
299 } else
300 break;
301 }
302}
303
Vignesh R3f51de32018-12-07 14:50:41 +0100304static int __omap24_i2c_setspeed(void __iomem *i2c_base, int ip_rev, uint speed,
Mugunthan V N38d943a2016-07-18 15:11:00 +0530305 int *waitdelay)
306{
Hannes Petermaierd5885052014-02-03 21:22:18 +0100307 int psc, fsscll = 0, fssclh = 0;
308 int hsscll = 0, hssclh = 0;
309 u32 scll = 0, sclh = 0;
Tom Rix03b2a742009-06-28 12:52:27 -0500310
Simon Glassed0a60a2020-01-23 11:48:20 -0700311 if (speed >= I2C_SPEED_HIGH_RATE) {
Tom Rix03b2a742009-06-28 12:52:27 -0500312 /* High speed */
Hannes Petermaierd5885052014-02-03 21:22:18 +0100313 psc = I2C_IP_CLK / I2C_INTERNAL_SAMPLING_CLK;
314 psc -= 1;
315 if (psc < I2C_PSC_MIN) {
316 printf("Error : I2C unsupported prescaler %d\n", psc);
317 return -1;
318 }
Tom Rix03b2a742009-06-28 12:52:27 -0500319
320 /* For first phase of HS mode */
Hannes Petermaierd5885052014-02-03 21:22:18 +0100321 fsscll = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);
322
323 fssclh = fsscll;
Tom Rix03b2a742009-06-28 12:52:27 -0500324
325 fsscll -= I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM;
326 fssclh -= I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM;
327 if (((fsscll < 0) || (fssclh < 0)) ||
328 ((fsscll > 255) || (fssclh > 255))) {
Andreas Müllera30293f2012-01-04 15:26:19 +0000329 puts("Error : I2C initializing first phase clock\n");
Hannes Petermaierd5885052014-02-03 21:22:18 +0100330 return -1;
Tom Rix03b2a742009-06-28 12:52:27 -0500331 }
332
333 /* For second phase of HS mode */
334 hsscll = hssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);
335
336 hsscll -= I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM;
337 hssclh -= I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM;
338 if (((fsscll < 0) || (fssclh < 0)) ||
339 ((fsscll > 255) || (fssclh > 255))) {
Andreas Müllera30293f2012-01-04 15:26:19 +0000340 puts("Error : I2C initializing second phase clock\n");
Hannes Petermaierd5885052014-02-03 21:22:18 +0100341 return -1;
Tom Rix03b2a742009-06-28 12:52:27 -0500342 }
343
344 scll = (unsigned int)hsscll << 8 | (unsigned int)fsscll;
345 sclh = (unsigned int)hssclh << 8 | (unsigned int)fssclh;
346
347 } else {
348 /* Standard and fast speed */
Hannes Petermaierd5885052014-02-03 21:22:18 +0100349 psc = omap24_i2c_findpsc(&scll, &sclh, speed);
350 if (0 > psc) {
Andreas Müllera30293f2012-01-04 15:26:19 +0000351 puts("Error : I2C initializing clock\n");
Hannes Petermaierd5885052014-02-03 21:22:18 +0100352 return -1;
Tom Rix03b2a742009-06-28 12:52:27 -0500353 }
Tom Rix03b2a742009-06-28 12:52:27 -0500354 }
wdenkf8062712005-01-09 23:16:25 +0000355
Vignesh R3f51de32018-12-07 14:50:41 +0100356 /* wait for 20 clkperiods */
357 *waitdelay = (10000000 / speed) * 2;
358
359 omap_i2c_write_reg(i2c_base, ip_rev, 0, OMAP_I2C_CON_REG);
360 omap_i2c_write_reg(i2c_base, ip_rev, psc, OMAP_I2C_PSC_REG);
361 omap_i2c_write_reg(i2c_base, ip_rev, scll, OMAP_I2C_SCLL_REG);
362 omap_i2c_write_reg(i2c_base, ip_rev, sclh, OMAP_I2C_SCLH_REG);
363 omap_i2c_write_reg(i2c_base, ip_rev, I2C_CON_EN, OMAP_I2C_CON_REG);
364
365 /* clear all pending status */
366 omap_i2c_write_reg(i2c_base, ip_rev, 0xFFFF, OMAP_I2C_STAT_REG);
Hannes Petermaierd5885052014-02-03 21:22:18 +0100367
368 return 0;
369}
Heiko Schocher0ecd6552014-06-30 09:12:09 +0200370
Vignesh R3f51de32018-12-07 14:50:41 +0100371static void omap24_i2c_deblock(void __iomem *i2c_base, int ip_rev)
Heiko Schocher0ecd6552014-06-30 09:12:09 +0200372{
Heiko Schocher0ecd6552014-06-30 09:12:09 +0200373 int i;
374 u16 systest;
375 u16 orgsystest;
376
377 /* set test mode ST_EN = 1 */
Vignesh R3f51de32018-12-07 14:50:41 +0100378 orgsystest = omap_i2c_read_reg(i2c_base, ip_rev, OMAP_I2C_SYSTEST_REG);
Heiko Schocher0ecd6552014-06-30 09:12:09 +0200379 systest = orgsystest;
Vignesh R3f51de32018-12-07 14:50:41 +0100380
Heiko Schocher0ecd6552014-06-30 09:12:09 +0200381 /* enable testmode */
382 systest |= I2C_SYSTEST_ST_EN;
Vignesh R3f51de32018-12-07 14:50:41 +0100383 omap_i2c_write_reg(i2c_base, ip_rev, systest, OMAP_I2C_SYSTEST_REG);
Heiko Schocher0ecd6552014-06-30 09:12:09 +0200384 systest &= ~I2C_SYSTEST_TMODE_MASK;
385 systest |= 3 << I2C_SYSTEST_TMODE_SHIFT;
Vignesh R3f51de32018-12-07 14:50:41 +0100386 omap_i2c_write_reg(i2c_base, ip_rev, systest, OMAP_I2C_SYSTEST_REG);
Heiko Schocher0ecd6552014-06-30 09:12:09 +0200387
388 /* set SCL, SDA = 1 */
389 systest |= I2C_SYSTEST_SCL_O | I2C_SYSTEST_SDA_O;
Vignesh R3f51de32018-12-07 14:50:41 +0100390 omap_i2c_write_reg(i2c_base, ip_rev, systest, OMAP_I2C_SYSTEST_REG);
Heiko Schocher0ecd6552014-06-30 09:12:09 +0200391 udelay(10);
392
393 /* toggle scl 9 clocks */
394 for (i = 0; i < 9; i++) {
395 /* SCL = 0 */
396 systest &= ~I2C_SYSTEST_SCL_O;
Vignesh R3f51de32018-12-07 14:50:41 +0100397 omap_i2c_write_reg(i2c_base, ip_rev,
398 systest, OMAP_I2C_SYSTEST_REG);
Heiko Schocher0ecd6552014-06-30 09:12:09 +0200399 udelay(10);
400 /* SCL = 1 */
401 systest |= I2C_SYSTEST_SCL_O;
Vignesh R3f51de32018-12-07 14:50:41 +0100402 omap_i2c_write_reg(i2c_base, ip_rev,
403 systest, OMAP_I2C_SYSTEST_REG);
Heiko Schocher0ecd6552014-06-30 09:12:09 +0200404 udelay(10);
405 }
406
407 /* send stop */
408 systest &= ~I2C_SYSTEST_SDA_O;
Vignesh R3f51de32018-12-07 14:50:41 +0100409 omap_i2c_write_reg(i2c_base, ip_rev, systest, OMAP_I2C_SYSTEST_REG);
Heiko Schocher0ecd6552014-06-30 09:12:09 +0200410 udelay(10);
411 systest |= I2C_SYSTEST_SCL_O | I2C_SYSTEST_SDA_O;
Vignesh R3f51de32018-12-07 14:50:41 +0100412 omap_i2c_write_reg(i2c_base, ip_rev, systest, OMAP_I2C_SYSTEST_REG);
Heiko Schocher0ecd6552014-06-30 09:12:09 +0200413 udelay(10);
414
415 /* restore original mode */
Vignesh R3f51de32018-12-07 14:50:41 +0100416 omap_i2c_write_reg(i2c_base, ip_rev, orgsystest, OMAP_I2C_SYSTEST_REG);
Heiko Schocher0ecd6552014-06-30 09:12:09 +0200417}
418
Vignesh R3f51de32018-12-07 14:50:41 +0100419static void __omap24_i2c_init(void __iomem *i2c_base, int ip_rev, int speed,
420 int slaveadd, int *waitdelay)
Hannes Petermaierd5885052014-02-03 21:22:18 +0100421{
Hannes Petermaierd5885052014-02-03 21:22:18 +0100422 int timeout = I2C_TIMEOUT;
Heiko Schocher0ecd6552014-06-30 09:12:09 +0200423 int deblock = 1;
Hannes Petermaierd5885052014-02-03 21:22:18 +0100424
Heiko Schocher0ecd6552014-06-30 09:12:09 +0200425retry:
Vignesh R3f51de32018-12-07 14:50:41 +0100426 if (omap_i2c_read_reg(i2c_base, ip_rev, OMAP_I2C_CON_REG) &
427 I2C_CON_EN) {
428 omap_i2c_write_reg(i2c_base, ip_rev, 0, OMAP_I2C_CON_REG);
Michael Jones4db67862011-07-27 14:01:55 -0400429 udelay(50000);
wdenkf8062712005-01-09 23:16:25 +0000430 }
431
Vignesh R3f51de32018-12-07 14:50:41 +0100432 /* for ES2 after soft reset */
433 omap_i2c_write_reg(i2c_base, ip_rev, 0x2, OMAP_I2C_SYSC_REG);
Tom Rini49fbf672012-02-20 18:49:16 +0000434 udelay(1000);
435
Vignesh R3f51de32018-12-07 14:50:41 +0100436 omap_i2c_write_reg(i2c_base, ip_rev, I2C_CON_EN, OMAP_I2C_CON_REG);
437 while (!(omap_i2c_read_reg(i2c_base, ip_rev, OMAP_I2C_SYSS_REG) &
438 I2C_SYSS_RDONE) && timeout--) {
Tom Rini49fbf672012-02-20 18:49:16 +0000439 if (timeout <= 0) {
440 puts("ERROR: Timeout in soft-reset\n");
441 return;
442 }
443 udelay(1000);
444 }
445
Vignesh R3f51de32018-12-07 14:50:41 +0100446 if (__omap24_i2c_setspeed(i2c_base, ip_rev, speed, waitdelay)) {
Hannes Petermaierd5885052014-02-03 21:22:18 +0100447 printf("ERROR: failed to setup I2C bus-speed!\n");
448 return;
449 }
Tom Rix03b2a742009-06-28 12:52:27 -0500450
wdenkf8062712005-01-09 23:16:25 +0000451 /* own address */
Vignesh R3f51de32018-12-07 14:50:41 +0100452 omap_i2c_write_reg(i2c_base, ip_rev, slaveadd, OMAP_I2C_OA_REG);
Hannes Petermaierd5885052014-02-03 21:22:18 +0100453
Vignesh R3f51de32018-12-07 14:50:41 +0100454 if (ip_rev == OMAP_I2C_REV_V1) {
455 /*
456 * Have to enable interrupts for OMAP2/3, these IPs don't have
457 * an 'irqstatus_raw' register and we shall have to poll 'stat'
458 */
459 omap_i2c_write_reg(i2c_base, ip_rev, I2C_IE_XRDY_IE |
460 I2C_IE_RRDY_IE | I2C_IE_ARDY_IE |
461 I2C_IE_NACK_IE | I2C_IE_AL_IE,
462 OMAP_I2C_IE_REG);
463 }
464
Michael Jones4db67862011-07-27 14:01:55 -0400465 udelay(1000);
Vignesh R3f51de32018-12-07 14:50:41 +0100466 flush_fifo(i2c_base, ip_rev);
467 omap_i2c_write_reg(i2c_base, ip_rev, 0xFFFF, OMAP_I2C_STAT_REG);
Heiko Schocher0ecd6552014-06-30 09:12:09 +0200468
469 /* Handle possible failed I2C state */
Vignesh R3f51de32018-12-07 14:50:41 +0100470 if (wait_for_bb(i2c_base, ip_rev, *waitdelay))
Heiko Schocher0ecd6552014-06-30 09:12:09 +0200471 if (deblock == 1) {
Vignesh R3f51de32018-12-07 14:50:41 +0100472 omap24_i2c_deblock(i2c_base, ip_rev);
Heiko Schocher0ecd6552014-06-30 09:12:09 +0200473 deblock = 0;
474 goto retry;
475 }
wdenkf8062712005-01-09 23:16:25 +0000476}
477
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000478/*
479 * i2c_probe: Use write access. Allows to identify addresses that are
480 * write-only (like the config register of dual-port EEPROMs)
481 */
Vignesh R3f51de32018-12-07 14:50:41 +0100482static int __omap24_i2c_probe(void __iomem *i2c_base, int ip_rev, int waitdelay,
483 uchar chip)
wdenkf8062712005-01-09 23:16:25 +0000484{
Tom Rini49fbf672012-02-20 18:49:16 +0000485 u16 status;
wdenkf8062712005-01-09 23:16:25 +0000486 int res = 1; /* default = fail */
487
Vignesh R3f51de32018-12-07 14:50:41 +0100488 if (chip == omap_i2c_read_reg(i2c_base, ip_rev, OMAP_I2C_OA_REG))
wdenkf8062712005-01-09 23:16:25 +0000489 return res;
wdenkf8062712005-01-09 23:16:25 +0000490
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000491 /* Wait until bus is free */
Vignesh R3f51de32018-12-07 14:50:41 +0100492 if (wait_for_bb(i2c_base, ip_rev, waitdelay))
Vincent Stehlé33205e32012-12-03 05:23:16 +0000493 return res;
wdenkf8062712005-01-09 23:16:25 +0000494
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000495 /* No data transfer, slave addr only */
Vignesh R3f51de32018-12-07 14:50:41 +0100496 omap_i2c_write_reg(i2c_base, ip_rev, chip, OMAP_I2C_SA_REG);
497
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000498 /* Stop bit needed here */
Vignesh R3f51de32018-12-07 14:50:41 +0100499 omap_i2c_write_reg(i2c_base, ip_rev, I2C_CON_EN | I2C_CON_MST |
500 I2C_CON_STT | I2C_CON_TRX | I2C_CON_STP,
501 OMAP_I2C_CON_REG);
Nick Thompson48f7ae42011-04-11 22:37:41 +0000502
Vignesh R3f51de32018-12-07 14:50:41 +0100503 status = wait_for_event(i2c_base, ip_rev, waitdelay);
Vincent Stehlé33205e32012-12-03 05:23:16 +0000504
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000505 if ((status & ~I2C_STAT_XRDY) == 0 || (status & I2C_STAT_AL)) {
506 /*
507 * With current high-level command implementation, notifying
508 * the user shall flood the console with 127 messages. If
509 * silent exit is desired upon unconfigured bus, remove the
510 * following 'if' section:
511 */
512 if (status == I2C_STAT_XRDY)
Mugunthan V N38d943a2016-07-18 15:11:00 +0530513 printf("i2c_probe: pads on bus probably not configured (status=0x%x)\n",
514 status);
Vincent Stehlé33205e32012-12-03 05:23:16 +0000515
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000516 goto pr_exit;
Tom Rini27eed8b2012-05-21 06:46:29 +0000517 }
Tom Rini49fbf672012-02-20 18:49:16 +0000518
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000519 /* Check for ACK (!NAK) */
520 if (!(status & I2C_STAT_NACK)) {
Hannes Petermaierd5885052014-02-03 21:22:18 +0100521 res = 0; /* Device found */
Mugunthan V N38d943a2016-07-18 15:11:00 +0530522 udelay(waitdelay);/* Required by AM335X in SPL */
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000523 /* Abort transfer (force idle state) */
Vignesh R3f51de32018-12-07 14:50:41 +0100524 omap_i2c_write_reg(i2c_base, ip_rev, I2C_CON_MST | I2C_CON_TRX,
525 OMAP_I2C_CON_REG); /* Reset */
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000526 udelay(1000);
Vignesh R3f51de32018-12-07 14:50:41 +0100527 omap_i2c_write_reg(i2c_base, ip_rev, I2C_CON_EN | I2C_CON_MST |
528 I2C_CON_TRX | I2C_CON_STP,
529 OMAP_I2C_CON_REG); /* STP */
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000530 }
Vignesh R3f51de32018-12-07 14:50:41 +0100531
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000532pr_exit:
Vignesh R3f51de32018-12-07 14:50:41 +0100533 flush_fifo(i2c_base, ip_rev);
534 omap_i2c_write_reg(i2c_base, ip_rev, 0xFFFF, OMAP_I2C_STAT_REG);
wdenkf8062712005-01-09 23:16:25 +0000535 return res;
536}
537
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000538/*
539 * i2c_read: Function now uses a single I2C read transaction with bulk transfer
540 * of the requested number of bytes (note that the 'i2c md' command
541 * limits this to 16 bytes anyway). If CONFIG_I2C_REPEATED_START is
542 * defined in the board config header, this transaction shall be with
543 * Repeated Start (Sr) between the address and data phases; otherwise
544 * Stop-Start (P-S) shall be used (some I2C chips do require a P-S).
545 * The address (reg offset) may be 0, 1 or 2 bytes long.
546 * Function now reads correctly from chips that return more than one
547 * byte of data per addressed register (like TI temperature sensors),
548 * or that do not need a register address at all (such as some clock
549 * distributors).
550 */
Vignesh R3f51de32018-12-07 14:50:41 +0100551static int __omap24_i2c_read(void __iomem *i2c_base, int ip_rev, int waitdelay,
552 uchar chip, uint addr, int alen, uchar *buffer,
553 int len)
wdenkf8062712005-01-09 23:16:25 +0000554{
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000555 int i2c_error = 0;
556 u16 status;
557
558 if (alen < 0) {
559 puts("I2C read: addr len < 0\n");
560 return 1;
561 }
Vignesh R3f51de32018-12-07 14:50:41 +0100562
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000563 if (len < 0) {
564 puts("I2C read: data len < 0\n");
565 return 1;
566 }
Vignesh R3f51de32018-12-07 14:50:41 +0100567
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000568 if (buffer == NULL) {
569 puts("I2C read: NULL pointer passed\n");
570 return 1;
571 }
wdenkf8062712005-01-09 23:16:25 +0000572
Ilya Yanokbe6c2e42012-06-08 03:12:09 +0000573 if (alen > 2) {
Tom Rini49fbf672012-02-20 18:49:16 +0000574 printf("I2C read: addr len %d not supported\n", alen);
wdenkf8062712005-01-09 23:16:25 +0000575 return 1;
576 }
577
Ilya Yanokbe6c2e42012-06-08 03:12:09 +0000578 if (addr + len > (1 << 16)) {
Tom Rini49fbf672012-02-20 18:49:16 +0000579 puts("I2C read: address out of range\n");
wdenkf8062712005-01-09 23:16:25 +0000580 return 1;
581 }
582
Guy Thouret51c27272016-03-11 16:23:41 +0000583#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
584 /*
585 * EEPROM chips that implement "address overflow" are ones
586 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
587 * address and the extra bits end up in the "chip address"
588 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
589 * four 256 byte chips.
590 *
591 * Note that we consider the length of the address field to
592 * still be one byte because the extra address bits are
593 * hidden in the chip address.
594 */
595 if (alen > 0)
596 chip |= ((addr >> (alen * 8)) &
597 CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
598#endif
599
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000600 /* Wait until bus not busy */
Vignesh R3f51de32018-12-07 14:50:41 +0100601 if (wait_for_bb(i2c_base, ip_rev, waitdelay))
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000602 return 1;
603
604 /* Zero, one or two bytes reg address (offset) */
Vignesh R3f51de32018-12-07 14:50:41 +0100605 omap_i2c_write_reg(i2c_base, ip_rev, alen, OMAP_I2C_CNT_REG);
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000606 /* Set slave address */
Vignesh R3f51de32018-12-07 14:50:41 +0100607 omap_i2c_write_reg(i2c_base, ip_rev, chip, OMAP_I2C_SA_REG);
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000608
609 if (alen) {
610 /* Must write reg offset first */
611#ifdef CONFIG_I2C_REPEATED_START
612 /* No stop bit, use Repeated Start (Sr) */
Vignesh R3f51de32018-12-07 14:50:41 +0100613 omap_i2c_write_reg(i2c_base, ip_rev, I2C_CON_EN | I2C_CON_MST |
614 I2C_CON_STT | I2C_CON_TRX, OMAP_I2C_CON_REG);
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000615#else
616 /* Stop - Start (P-S) */
Vignesh R3f51de32018-12-07 14:50:41 +0100617 omap_i2c_write_reg(i2c_base, ip_rev, I2C_CON_EN | I2C_CON_MST |
618 I2C_CON_STT | I2C_CON_STP | I2C_CON_TRX,
619 OMAP_I2C_CON_REG);
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000620#endif
621 /* Send register offset */
622 while (1) {
Vignesh R3f51de32018-12-07 14:50:41 +0100623 status = wait_for_event(i2c_base, ip_rev, waitdelay);
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000624 /* Try to identify bus that is not padconf'd for I2C */
625 if (status == I2C_STAT_XRDY) {
626 i2c_error = 2;
Mugunthan V N38d943a2016-07-18 15:11:00 +0530627 printf("i2c_read (addr phase): pads on bus probably not configured (status=0x%x)\n",
628 status);
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000629 goto rd_exit;
630 }
Hannes Petermaierd5885052014-02-03 21:22:18 +0100631 if (status == 0 || (status & I2C_STAT_NACK)) {
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000632 i2c_error = 1;
633 printf("i2c_read: error waiting for addr ACK (status=0x%x)\n",
634 status);
635 goto rd_exit;
636 }
637 if (alen) {
638 if (status & I2C_STAT_XRDY) {
Vignesh R3f51de32018-12-07 14:50:41 +0100639 u8 addr_byte;
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000640 alen--;
Vignesh R3f51de32018-12-07 14:50:41 +0100641 addr_byte = (addr >> (8 * alen)) & 0xff;
642 omap_i2c_write_reg(i2c_base, ip_rev,
643 addr_byte,
644 OMAP_I2C_DATA_REG);
645 omap_i2c_write_reg(i2c_base, ip_rev,
646 I2C_STAT_XRDY,
647 OMAP_I2C_STAT_REG);
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000648 }
649 }
650 if (status & I2C_STAT_ARDY) {
Vignesh R3f51de32018-12-07 14:50:41 +0100651 omap_i2c_write_reg(i2c_base, ip_rev,
652 I2C_STAT_ARDY,
653 OMAP_I2C_STAT_REG);
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000654 break;
655 }
wdenkf8062712005-01-09 23:16:25 +0000656 }
657 }
Vignesh R3f51de32018-12-07 14:50:41 +0100658
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000659 /* Set slave address */
Vignesh R3f51de32018-12-07 14:50:41 +0100660 omap_i2c_write_reg(i2c_base, ip_rev, chip, OMAP_I2C_SA_REG);
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000661 /* Read len bytes from slave */
Vignesh R3f51de32018-12-07 14:50:41 +0100662 omap_i2c_write_reg(i2c_base, ip_rev, len, OMAP_I2C_CNT_REG);
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000663 /* Need stop bit here */
Vignesh R3f51de32018-12-07 14:50:41 +0100664 omap_i2c_write_reg(i2c_base, ip_rev, I2C_CON_EN | I2C_CON_MST |
665 I2C_CON_STT | I2C_CON_STP, OMAP_I2C_CON_REG);
wdenkf8062712005-01-09 23:16:25 +0000666
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000667 /* Receive data */
668 while (1) {
Vignesh R3f51de32018-12-07 14:50:41 +0100669 status = wait_for_event(i2c_base, ip_rev, waitdelay);
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000670 /*
671 * Try to identify bus that is not padconf'd for I2C. This
672 * state could be left over from previous transactions if
673 * the address phase is skipped due to alen=0.
674 */
675 if (status == I2C_STAT_XRDY) {
676 i2c_error = 2;
Mugunthan V N38d943a2016-07-18 15:11:00 +0530677 printf("i2c_read (data phase): pads on bus probably not configured (status=0x%x)\n",
678 status);
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000679 goto rd_exit;
680 }
Hannes Petermaierd5885052014-02-03 21:22:18 +0100681 if (status == 0 || (status & I2C_STAT_NACK)) {
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000682 i2c_error = 1;
683 goto rd_exit;
684 }
685 if (status & I2C_STAT_RRDY) {
Vignesh R3f51de32018-12-07 14:50:41 +0100686 *buffer++ = omap_i2c_read_reg(i2c_base, ip_rev,
687 OMAP_I2C_DATA_REG);
688 omap_i2c_write_reg(i2c_base, ip_rev,
689 I2C_STAT_RRDY, OMAP_I2C_STAT_REG);
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000690 }
691 if (status & I2C_STAT_ARDY) {
Vignesh R3f51de32018-12-07 14:50:41 +0100692 omap_i2c_write_reg(i2c_base, ip_rev,
693 I2C_STAT_ARDY, OMAP_I2C_STAT_REG);
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000694 break;
695 }
696 }
697
698rd_exit:
Vignesh R3f51de32018-12-07 14:50:41 +0100699 flush_fifo(i2c_base, ip_rev);
700 omap_i2c_write_reg(i2c_base, ip_rev, 0xFFFF, OMAP_I2C_STAT_REG);
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000701 return i2c_error;
wdenkf8062712005-01-09 23:16:25 +0000702}
703
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000704/* i2c_write: Address (reg offset) may be 0, 1 or 2 bytes long. */
Vignesh R3f51de32018-12-07 14:50:41 +0100705static int __omap24_i2c_write(void __iomem *i2c_base, int ip_rev, int waitdelay,
706 uchar chip, uint addr, int alen, uchar *buffer,
707 int len)
wdenkf8062712005-01-09 23:16:25 +0000708{
Tom Rini49fbf672012-02-20 18:49:16 +0000709 int i;
710 u16 status;
711 int i2c_error = 0;
Hannes Petermaierd5885052014-02-03 21:22:18 +0100712 int timeout = I2C_TIMEOUT;
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000713
714 if (alen < 0) {
715 puts("I2C write: addr len < 0\n");
716 return 1;
717 }
718
719 if (len < 0) {
720 puts("I2C write: data len < 0\n");
721 return 1;
722 }
723
724 if (buffer == NULL) {
725 puts("I2C write: NULL pointer passed\n");
726 return 1;
727 }
wdenkf8062712005-01-09 23:16:25 +0000728
Ilya Yanokbe6c2e42012-06-08 03:12:09 +0000729 if (alen > 2) {
Tom Rini49fbf672012-02-20 18:49:16 +0000730 printf("I2C write: addr len %d not supported\n", alen);
wdenkf8062712005-01-09 23:16:25 +0000731 return 1;
Tom Rini49fbf672012-02-20 18:49:16 +0000732 }
wdenkf8062712005-01-09 23:16:25 +0000733
Ilya Yanokbe6c2e42012-06-08 03:12:09 +0000734 if (addr + len > (1 << 16)) {
Tom Rini49fbf672012-02-20 18:49:16 +0000735 printf("I2C write: address 0x%x + 0x%x out of range\n",
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000736 addr, len);
wdenkf8062712005-01-09 23:16:25 +0000737 return 1;
738 }
739
Guy Thouret51c27272016-03-11 16:23:41 +0000740#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
741 /*
742 * EEPROM chips that implement "address overflow" are ones
743 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
744 * address and the extra bits end up in the "chip address"
745 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
746 * four 256 byte chips.
747 *
748 * Note that we consider the length of the address field to
749 * still be one byte because the extra address bits are
750 * hidden in the chip address.
751 */
752 if (alen > 0)
753 chip |= ((addr >> (alen * 8)) &
754 CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
755#endif
756
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000757 /* Wait until bus not busy */
Vignesh R3f51de32018-12-07 14:50:41 +0100758 if (wait_for_bb(i2c_base, ip_rev, waitdelay))
Vincent Stehlé33205e32012-12-03 05:23:16 +0000759 return 1;
Michael Jonesbb54d572011-09-04 14:01:55 -0400760
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000761 /* Start address phase - will write regoffset + len bytes data */
Vignesh R3f51de32018-12-07 14:50:41 +0100762 omap_i2c_write_reg(i2c_base, ip_rev, alen + len, OMAP_I2C_CNT_REG);
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000763 /* Set slave address */
Vignesh R3f51de32018-12-07 14:50:41 +0100764 omap_i2c_write_reg(i2c_base, ip_rev, chip, OMAP_I2C_SA_REG);
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000765 /* Stop bit needed here */
Vignesh R3f51de32018-12-07 14:50:41 +0100766 omap_i2c_write_reg(i2c_base, ip_rev, I2C_CON_EN | I2C_CON_MST |
767 I2C_CON_STT | I2C_CON_TRX | I2C_CON_STP,
768 OMAP_I2C_CON_REG);
Michael Jonesbb54d572011-09-04 14:01:55 -0400769
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000770 while (alen) {
771 /* Must write reg offset (one or two bytes) */
Vignesh R3f51de32018-12-07 14:50:41 +0100772 status = wait_for_event(i2c_base, ip_rev, waitdelay);
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000773 /* Try to identify bus that is not padconf'd for I2C */
774 if (status == I2C_STAT_XRDY) {
775 i2c_error = 2;
Mugunthan V N38d943a2016-07-18 15:11:00 +0530776 printf("i2c_write: pads on bus probably not configured (status=0x%x)\n",
777 status);
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000778 goto wr_exit;
779 }
Hannes Petermaierd5885052014-02-03 21:22:18 +0100780 if (status == 0 || (status & I2C_STAT_NACK)) {
Tom Rini49fbf672012-02-20 18:49:16 +0000781 i2c_error = 1;
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000782 printf("i2c_write: error waiting for addr ACK (status=0x%x)\n",
783 status);
784 goto wr_exit;
Tom Rini49fbf672012-02-20 18:49:16 +0000785 }
Tom Rini49fbf672012-02-20 18:49:16 +0000786 if (status & I2C_STAT_XRDY) {
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000787 alen--;
Vignesh R3f51de32018-12-07 14:50:41 +0100788 omap_i2c_write_reg(i2c_base, ip_rev,
789 (addr >> (8 * alen)) & 0xff,
790 OMAP_I2C_DATA_REG);
791 omap_i2c_write_reg(i2c_base, ip_rev,
792 I2C_STAT_XRDY, OMAP_I2C_STAT_REG);
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000793 } else {
794 i2c_error = 1;
795 printf("i2c_write: bus not ready for addr Tx (status=0x%x)\n",
796 status);
797 goto wr_exit;
798 }
799 }
Vignesh R3f51de32018-12-07 14:50:41 +0100800
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000801 /* Address phase is over, now write data */
802 for (i = 0; i < len; i++) {
Vignesh R3f51de32018-12-07 14:50:41 +0100803 status = wait_for_event(i2c_base, ip_rev, waitdelay);
Hannes Petermaierd5885052014-02-03 21:22:18 +0100804 if (status == 0 || (status & I2C_STAT_NACK)) {
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000805 i2c_error = 1;
806 printf("i2c_write: error waiting for data ACK (status=0x%x)\n",
807 status);
808 goto wr_exit;
809 }
810 if (status & I2C_STAT_XRDY) {
Vignesh R3f51de32018-12-07 14:50:41 +0100811 omap_i2c_write_reg(i2c_base, ip_rev,
812 buffer[i], OMAP_I2C_DATA_REG);
813 omap_i2c_write_reg(i2c_base, ip_rev,
814 I2C_STAT_XRDY, OMAP_I2C_STAT_REG);
Tom Rini49fbf672012-02-20 18:49:16 +0000815 } else {
816 i2c_error = 1;
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000817 printf("i2c_write: bus not ready for data Tx (i=%d)\n",
818 i);
819 goto wr_exit;
Patil, Rachnaa9e18c22012-01-22 23:44:12 +0000820 }
821 }
Vignesh R3f51de32018-12-07 14:50:41 +0100822
Hannes Petermaierd5885052014-02-03 21:22:18 +0100823 /*
824 * poll ARDY bit for making sure that last byte really has been
825 * transferred on the bus.
826 */
827 do {
Vignesh R3f51de32018-12-07 14:50:41 +0100828 status = wait_for_event(i2c_base, ip_rev, waitdelay);
Hannes Petermaierd5885052014-02-03 21:22:18 +0100829 } while (!(status & I2C_STAT_ARDY) && timeout--);
830 if (timeout <= 0)
831 printf("i2c_write: timed out writig last byte!\n");
Patil, Rachnaa9e18c22012-01-22 23:44:12 +0000832
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000833wr_exit:
Vignesh R3f51de32018-12-07 14:50:41 +0100834 flush_fifo(i2c_base, ip_rev);
835 omap_i2c_write_reg(i2c_base, ip_rev, 0xFFFF, OMAP_I2C_STAT_REG);
Tom Rini49fbf672012-02-20 18:49:16 +0000836 return i2c_error;
wdenkf8062712005-01-09 23:16:25 +0000837}
838
Igor Opaniukf7c91762021-02-09 13:52:45 +0200839#if !CONFIG_IS_ENABLED(DM_I2C)
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000840/*
Mugunthan V N38d943a2016-07-18 15:11:00 +0530841 * The legacy I2C functions. These need to get removed once
842 * all users of this driver are converted to DM.
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000843 */
Vignesh R3f51de32018-12-07 14:50:41 +0100844static void __iomem *omap24_get_base(struct i2c_adapter *adap)
Dirk Behme7a8f6572009-11-02 20:36:26 +0100845{
Heiko Schocherf53f2b82013-10-22 11:03:18 +0200846 switch (adap->hwadapnr) {
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000847 case 0:
Vignesh R3f51de32018-12-07 14:50:41 +0100848 return (void __iomem *)I2C_BASE1;
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000849 break;
850 case 1:
Vignesh R3f51de32018-12-07 14:50:41 +0100851 return (void __iomem *)I2C_BASE2;
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000852 break;
Adam Ford73010ab2017-08-11 06:39:13 -0500853#if (CONFIG_SYS_I2C_BUS_MAX > 2)
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000854 case 2:
Vignesh R3f51de32018-12-07 14:50:41 +0100855 return (void __iomem *)I2C_BASE3;
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000856 break;
Adam Ford73010ab2017-08-11 06:39:13 -0500857#if (CONFIG_SYS_I2C_BUS_MAX > 3)
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000858 case 3:
Vignesh R3f51de32018-12-07 14:50:41 +0100859 return (void __iomem *)I2C_BASE4;
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000860 break;
Adam Ford73010ab2017-08-11 06:39:13 -0500861#if (CONFIG_SYS_I2C_BUS_MAX > 4)
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000862 case 4:
Vignesh R3f51de32018-12-07 14:50:41 +0100863 return (void __iomem *)I2C_BASE5;
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000864 break;
Koen Kooi584ff5f2012-08-08 00:57:35 +0000865#endif
Dirk Behme7a8f6572009-11-02 20:36:26 +0100866#endif
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000867#endif
Heiko Schocherf53f2b82013-10-22 11:03:18 +0200868 default:
869 printf("wrong hwadapnr: %d\n", adap->hwadapnr);
870 break;
Lubomir Popov4d98efd2013-06-01 06:44:38 +0000871 }
Vignesh R3f51de32018-12-07 14:50:41 +0100872
Heiko Schocherf53f2b82013-10-22 11:03:18 +0200873 return NULL;
874}
Dirk Behme7a8f6572009-11-02 20:36:26 +0100875
Vignesh R3f51de32018-12-07 14:50:41 +0100876static int omap24_get_ip_rev(void)
877{
878#ifdef CONFIG_OMAP34XX
879 return OMAP_I2C_REV_V1;
880#else
881 return OMAP_I2C_REV_V2;
882#endif
883}
Mugunthan V N38d943a2016-07-18 15:11:00 +0530884
885static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
886 int alen, uchar *buffer, int len)
887{
Vignesh R3f51de32018-12-07 14:50:41 +0100888 void __iomem *i2c_base = omap24_get_base(adap);
889 int ip_rev = omap24_get_ip_rev();
Mugunthan V N38d943a2016-07-18 15:11:00 +0530890
Vignesh R3f51de32018-12-07 14:50:41 +0100891 return __omap24_i2c_read(i2c_base, ip_rev, adap->waitdelay, chip, addr,
Mugunthan V N38d943a2016-07-18 15:11:00 +0530892 alen, buffer, len);
893}
894
Mugunthan V N38d943a2016-07-18 15:11:00 +0530895static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
896 int alen, uchar *buffer, int len)
897{
Vignesh R3f51de32018-12-07 14:50:41 +0100898 void __iomem *i2c_base = omap24_get_base(adap);
899 int ip_rev = omap24_get_ip_rev();
Mugunthan V N38d943a2016-07-18 15:11:00 +0530900
Vignesh R3f51de32018-12-07 14:50:41 +0100901 return __omap24_i2c_write(i2c_base, ip_rev, adap->waitdelay, chip, addr,
Mugunthan V N38d943a2016-07-18 15:11:00 +0530902 alen, buffer, len);
903}
904
905static uint omap24_i2c_setspeed(struct i2c_adapter *adap, uint speed)
906{
Vignesh R3f51de32018-12-07 14:50:41 +0100907 void __iomem *i2c_base = omap24_get_base(adap);
908 int ip_rev = omap24_get_ip_rev();
Mugunthan V N38d943a2016-07-18 15:11:00 +0530909 int ret;
910
Vignesh R3f51de32018-12-07 14:50:41 +0100911 ret = __omap24_i2c_setspeed(i2c_base, ip_rev, speed, &adap->waitdelay);
Mugunthan V N38d943a2016-07-18 15:11:00 +0530912 if (ret) {
Masahiro Yamada81e10422017-09-16 14:10:41 +0900913 pr_err("%s: set i2c speed failed\n", __func__);
Mugunthan V N38d943a2016-07-18 15:11:00 +0530914 return ret;
915 }
916
917 adap->speed = speed;
918
919 return 0;
920}
921
922static void omap24_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
923{
Vignesh R3f51de32018-12-07 14:50:41 +0100924 void __iomem *i2c_base = omap24_get_base(adap);
925 int ip_rev = omap24_get_ip_rev();
Mugunthan V N38d943a2016-07-18 15:11:00 +0530926
Vignesh R3f51de32018-12-07 14:50:41 +0100927 return __omap24_i2c_init(i2c_base, ip_rev, speed, slaveadd,
928 &adap->waitdelay);
Mugunthan V N38d943a2016-07-18 15:11:00 +0530929}
930
931static int omap24_i2c_probe(struct i2c_adapter *adap, uchar chip)
932{
Vignesh R3f51de32018-12-07 14:50:41 +0100933 void __iomem *i2c_base = omap24_get_base(adap);
934 int ip_rev = omap24_get_ip_rev();
Mugunthan V N38d943a2016-07-18 15:11:00 +0530935
Vignesh R3f51de32018-12-07 14:50:41 +0100936 return __omap24_i2c_probe(i2c_base, ip_rev, adap->waitdelay, chip);
Mugunthan V N38d943a2016-07-18 15:11:00 +0530937}
938
Heiko Schocherf53f2b82013-10-22 11:03:18 +0200939U_BOOT_I2C_ADAP_COMPLETE(omap24_0, omap24_i2c_init, omap24_i2c_probe,
Hannes Petermaierd5885052014-02-03 21:22:18 +0100940 omap24_i2c_read, omap24_i2c_write, omap24_i2c_setspeed,
Tom Rinia7a9bc02021-08-18 23:12:29 -0400941 CONFIG_SYS_I2C_SPEED,
942 CONFIG_SYS_I2C_SLAVE,
Heiko Schocherf53f2b82013-10-22 11:03:18 +0200943 0)
944U_BOOT_I2C_ADAP_COMPLETE(omap24_1, omap24_i2c_init, omap24_i2c_probe,
Hannes Petermaierd5885052014-02-03 21:22:18 +0100945 omap24_i2c_read, omap24_i2c_write, omap24_i2c_setspeed,
Tom Rinia7a9bc02021-08-18 23:12:29 -0400946 CONFIG_SYS_I2C_SPEED,
947 CONFIG_SYS_I2C_SLAVE,
Heiko Schocherf53f2b82013-10-22 11:03:18 +0200948 1)
Vignesh R3f51de32018-12-07 14:50:41 +0100949
Adam Ford73010ab2017-08-11 06:39:13 -0500950#if (CONFIG_SYS_I2C_BUS_MAX > 2)
Heiko Schocherf53f2b82013-10-22 11:03:18 +0200951U_BOOT_I2C_ADAP_COMPLETE(omap24_2, omap24_i2c_init, omap24_i2c_probe,
952 omap24_i2c_read, omap24_i2c_write, NULL,
Tom Rinia7a9bc02021-08-18 23:12:29 -0400953 CONFIG_SYS_I2C_SPEED,
954 CONFIG_SYS_I2C_SLAVE,
Heiko Schocherf53f2b82013-10-22 11:03:18 +0200955 2)
Adam Ford73010ab2017-08-11 06:39:13 -0500956#if (CONFIG_SYS_I2C_BUS_MAX > 3)
Heiko Schocherf53f2b82013-10-22 11:03:18 +0200957U_BOOT_I2C_ADAP_COMPLETE(omap24_3, omap24_i2c_init, omap24_i2c_probe,
958 omap24_i2c_read, omap24_i2c_write, NULL,
Tom Rinia7a9bc02021-08-18 23:12:29 -0400959 CONFIG_SYS_I2C_SPEED,
960 CONFIG_SYS_I2C_SLAVE,
Heiko Schocherf53f2b82013-10-22 11:03:18 +0200961 3)
Adam Ford73010ab2017-08-11 06:39:13 -0500962#if (CONFIG_SYS_I2C_BUS_MAX > 4)
Heiko Schocherf53f2b82013-10-22 11:03:18 +0200963U_BOOT_I2C_ADAP_COMPLETE(omap24_4, omap24_i2c_init, omap24_i2c_probe,
964 omap24_i2c_read, omap24_i2c_write, NULL,
Tom Rinia7a9bc02021-08-18 23:12:29 -0400965 CONFIG_SYS_I2C_SPEED,
966 CONFIG_SYS_I2C_SLAVE,
Heiko Schocherf53f2b82013-10-22 11:03:18 +0200967 4)
968#endif
969#endif
970#endif
Mugunthan V N560037b2016-07-18 15:11:01 +0530971
972#else /* CONFIG_DM_I2C */
973
974static int omap_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs)
975{
976 struct omap_i2c *priv = dev_get_priv(bus);
977 int ret;
978
979 debug("i2c_xfer: %d messages\n", nmsgs);
980 for (; nmsgs > 0; nmsgs--, msg++) {
981 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
982 if (msg->flags & I2C_M_RD) {
Vignesh R3f51de32018-12-07 14:50:41 +0100983 ret = __omap24_i2c_read(priv->regs, priv->ip_rev,
984 priv->waitdelay,
Mugunthan V N560037b2016-07-18 15:11:01 +0530985 msg->addr, 0, 0, msg->buf,
986 msg->len);
987 } else {
Vignesh R3f51de32018-12-07 14:50:41 +0100988 ret = __omap24_i2c_write(priv->regs, priv->ip_rev,
989 priv->waitdelay,
Mugunthan V N560037b2016-07-18 15:11:01 +0530990 msg->addr, 0, 0, msg->buf,
991 msg->len);
992 }
993 if (ret) {
994 debug("i2c_write: error sending\n");
995 return -EREMOTEIO;
996 }
997 }
998
999 return 0;
1000}
1001
1002static int omap_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
1003{
1004 struct omap_i2c *priv = dev_get_priv(bus);
1005
1006 priv->speed = speed;
1007
Vignesh R3f51de32018-12-07 14:50:41 +01001008 return __omap24_i2c_setspeed(priv->regs, priv->ip_rev, speed,
1009 &priv->waitdelay);
Mugunthan V N560037b2016-07-18 15:11:01 +05301010}
1011
1012static int omap_i2c_probe_chip(struct udevice *bus, uint chip_addr,
1013 uint chip_flags)
1014{
1015 struct omap_i2c *priv = dev_get_priv(bus);
1016
Vignesh R3f51de32018-12-07 14:50:41 +01001017 return __omap24_i2c_probe(priv->regs, priv->ip_rev, priv->waitdelay,
Nikita Yushchenko83f3f8b2022-02-15 21:10:09 +03001018 chip_addr) ? -EREMOTEIO : 0;
Mugunthan V N560037b2016-07-18 15:11:01 +05301019}
1020
1021static int omap_i2c_probe(struct udevice *bus)
1022{
1023 struct omap_i2c *priv = dev_get_priv(bus);
Simon Glassb75b15b2020-12-03 16:55:23 -07001024 struct omap_i2c_plat *plat = dev_get_plat(bus);
Mugunthan V N560037b2016-07-18 15:11:01 +05301025
Jean-Jacques Hiblot58994fc2018-12-07 14:50:42 +01001026 priv->speed = plat->speed;
1027 priv->regs = map_physmem(plat->base, sizeof(void *),
1028 MAP_NOCACHE);
1029 priv->ip_rev = plat->ip_rev;
Vignesh R3f51de32018-12-07 14:50:41 +01001030
1031 __omap24_i2c_init(priv->regs, priv->ip_rev, priv->speed, 0,
1032 &priv->waitdelay);
Mugunthan V N560037b2016-07-18 15:11:01 +05301033
1034 return 0;
1035}
1036
Simon Glass3580f6d2021-08-07 07:24:03 -06001037#if CONFIG_IS_ENABLED(OF_REAL)
Simon Glassaad29ae2020-12-03 16:55:21 -07001038static int omap_i2c_of_to_plat(struct udevice *bus)
Mugunthan V N560037b2016-07-18 15:11:01 +05301039{
Simon Glassb75b15b2020-12-03 16:55:23 -07001040 struct omap_i2c_plat *plat = dev_get_plat(bus);
Mugunthan V N560037b2016-07-18 15:11:01 +05301041
Masahiro Yamadaa89b4de2020-07-17 14:36:48 +09001042 plat->base = dev_read_addr(bus);
Simon Glassf0c99c52020-01-23 11:48:22 -07001043 plat->speed = dev_read_u32_default(bus, "clock-frequency",
1044 I2C_SPEED_STANDARD_RATE);
Jean-Jacques Hiblot58994fc2018-12-07 14:50:42 +01001045 plat->ip_rev = dev_get_driver_data(bus);
Mugunthan V N560037b2016-07-18 15:11:01 +05301046
1047 return 0;
1048}
1049
Mugunthan V N560037b2016-07-18 15:11:01 +05301050static const struct udevice_id omap_i2c_ids[] = {
Vignesh R3f51de32018-12-07 14:50:41 +01001051 { .compatible = "ti,omap3-i2c", .data = OMAP_I2C_REV_V1 },
1052 { .compatible = "ti,omap4-i2c", .data = OMAP_I2C_REV_V2 },
Mugunthan V N560037b2016-07-18 15:11:01 +05301053 { }
1054};
Adam Ford1f098462018-08-20 20:24:35 -05001055#endif
1056
1057static const struct dm_i2c_ops omap_i2c_ops = {
1058 .xfer = omap_i2c_xfer,
1059 .probe_chip = omap_i2c_probe_chip,
1060 .set_bus_speed = omap_i2c_set_bus_speed,
1061};
Mugunthan V N560037b2016-07-18 15:11:01 +05301062
1063U_BOOT_DRIVER(i2c_omap) = {
1064 .name = "i2c_omap",
1065 .id = UCLASS_I2C,
Simon Glass3580f6d2021-08-07 07:24:03 -06001066#if CONFIG_IS_ENABLED(OF_REAL)
Mugunthan V N560037b2016-07-18 15:11:01 +05301067 .of_match = omap_i2c_ids,
Simon Glassaad29ae2020-12-03 16:55:21 -07001068 .of_to_plat = omap_i2c_of_to_plat,
Simon Glassb75b15b2020-12-03 16:55:23 -07001069 .plat_auto = sizeof(struct omap_i2c_plat),
Adam Ford1f098462018-08-20 20:24:35 -05001070#endif
Mugunthan V N560037b2016-07-18 15:11:01 +05301071 .probe = omap_i2c_probe,
Simon Glass8a2b47f2020-12-03 16:55:17 -07001072 .priv_auto = sizeof(struct omap_i2c),
Mugunthan V N560037b2016-07-18 15:11:01 +05301073 .ops = &omap_i2c_ops,
Bin Menga61b9622018-10-24 06:36:31 -07001074#if !CONFIG_IS_ENABLED(OF_CONTROL)
Mugunthan V N560037b2016-07-18 15:11:01 +05301075 .flags = DM_FLAG_PRE_RELOC,
Bin Menga61b9622018-10-24 06:36:31 -07001076#endif
Mugunthan V N560037b2016-07-18 15:11:01 +05301077};
1078
1079#endif /* CONFIG_DM_I2C */