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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Chin Liang Seecb350602014-03-04 22:13:53 -06002/*
Ley Foon Tanec6f8822017-04-26 02:44:33 +08003 * Copyright (C) 2013-2017 Altera Corporation <www.altera.com>
Chin Liang Seecb350602014-03-04 22:13:53 -06004 */
5
Ley Foon Tanec6f8822017-04-26 02:44:33 +08006#ifndef _CLOCK_MANAGER_H_
7#define _CLOCK_MANAGER_H_
Chin Liang Seecb350602014-03-04 22:13:53 -06008
Ley Foon Tan26695912019-11-08 10:38:21 +08009phys_addr_t socfpga_get_clkmgr_addr(void);
10
Simon Glass559f1a82020-05-10 11:40:12 -060011#ifndef __ASSEMBLY__
Ley Foon Tanec6f8822017-04-26 02:44:33 +080012void cm_wait_for_lock(u32 mask);
13int cm_wait_for_fsm(void);
14void cm_print_clock_quick_summary(void);
Pavel Machek7c8d5a62014-09-08 14:08:45 +020015#endif
16
Ley Foon Tanec6f8822017-04-26 02:44:33 +080017#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
18#include <asm/arch/clock_manager_gen5.h>
Ley Foon Tanca40f292017-04-26 02:44:39 +080019#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
20#include <asm/arch/clock_manager_arria10.h>
Ley Foon Tan6751e7d2018-05-18 22:05:22 +080021#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
22#include <asm/arch/clock_manager_s10.h>
Ley Foon Tanb7d95b72019-11-27 15:55:23 +080023#elif defined(CONFIG_TARGET_SOCFPGA_AGILEX)
24#include <asm/arch/clock_manager_agilex.h>
Ley Foon Tanec6f8822017-04-26 02:44:33 +080025#endif
Ley Foon Tanca40f292017-04-26 02:44:39 +080026
Chin Liang Seecb350602014-03-04 22:13:53 -060027#endif /* _CLOCK_MANAGER_H_ */