Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 2 | /* |
Jerry Huang | ed41367 | 2011-01-06 23:42:19 -0600 | [diff] [blame] | 3 | * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc |
Yangbo Lu | 8abc043 | 2020-05-19 11:06:43 +0800 | [diff] [blame] | 4 | * Copyright 2019-2020 NXP |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 5 | * Andy Fleming |
| 6 | * |
| 7 | * Based vaguely on the pxa mmc code: |
| 8 | * (C) Copyright 2003 |
| 9 | * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 10 | */ |
| 11 | |
| 12 | #include <config.h> |
| 13 | #include <common.h> |
| 14 | #include <command.h> |
Simon Glass | 6333448 | 2019-11-14 12:57:39 -0700 | [diff] [blame] | 15 | #include <cpu_func.h> |
Jaehoon Chung | 7825d20 | 2016-07-19 16:33:36 +0900 | [diff] [blame] | 16 | #include <errno.h> |
Anton Vorontsov | f751a3c | 2009-06-10 00:25:29 +0400 | [diff] [blame] | 17 | #include <hwconfig.h> |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 18 | #include <mmc.h> |
| 19 | #include <part.h> |
| 20 | #include <malloc.h> |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 21 | #include <fsl_esdhc.h> |
Anton Vorontsov | f751a3c | 2009-06-10 00:25:29 +0400 | [diff] [blame] | 22 | #include <fdt_support.h> |
Simon Glass | 274e0b0 | 2020-05-10 11:39:56 -0600 | [diff] [blame] | 23 | #include <asm/cache.h> |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 24 | #include <asm/io.h> |
Peng Fan | a4d36f7 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 25 | #include <dm.h> |
Simon Glass | 9bc1564 | 2020-02-03 07:36:16 -0700 | [diff] [blame] | 26 | #include <dm/device_compat.h> |
Simon Glass | 4dcacfc | 2020-05-10 11:40:13 -0600 | [diff] [blame] | 27 | #include <linux/bitops.h> |
Simon Glass | dbd7954 | 2020-05-10 11:40:11 -0600 | [diff] [blame] | 28 | #include <linux/delay.h> |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 29 | |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 30 | DECLARE_GLOBAL_DATA_PTR; |
| 31 | |
| 32 | struct fsl_esdhc { |
Haijun.Zhang | d49eb9e | 2013-10-30 11:37:55 +0800 | [diff] [blame] | 33 | uint dsaddr; /* SDMA system address register */ |
| 34 | uint blkattr; /* Block attributes register */ |
| 35 | uint cmdarg; /* Command argument register */ |
| 36 | uint xfertyp; /* Transfer type register */ |
| 37 | uint cmdrsp0; /* Command response 0 register */ |
| 38 | uint cmdrsp1; /* Command response 1 register */ |
| 39 | uint cmdrsp2; /* Command response 2 register */ |
| 40 | uint cmdrsp3; /* Command response 3 register */ |
| 41 | uint datport; /* Buffer data port register */ |
| 42 | uint prsstat; /* Present state register */ |
| 43 | uint proctl; /* Protocol control register */ |
| 44 | uint sysctl; /* System Control Register */ |
| 45 | uint irqstat; /* Interrupt status register */ |
| 46 | uint irqstaten; /* Interrupt status enable register */ |
| 47 | uint irqsigen; /* Interrupt signal enable register */ |
| 48 | uint autoc12err; /* Auto CMD error status register */ |
| 49 | uint hostcapblt; /* Host controller capabilities register */ |
| 50 | uint wml; /* Watermark level register */ |
Yangbo Lu | 62b56b3 | 2019-06-21 11:42:29 +0800 | [diff] [blame] | 51 | char reserved1[8]; /* reserved */ |
Haijun.Zhang | d49eb9e | 2013-10-30 11:37:55 +0800 | [diff] [blame] | 52 | uint fevt; /* Force event register */ |
| 53 | uint admaes; /* ADMA error status register */ |
| 54 | uint adsaddr; /* ADMA system address register */ |
Yangbo Lu | 62b56b3 | 2019-06-21 11:42:29 +0800 | [diff] [blame] | 55 | char reserved2[160]; |
Haijun.Zhang | d49eb9e | 2013-10-30 11:37:55 +0800 | [diff] [blame] | 56 | uint hostver; /* Host controller version register */ |
Yangbo Lu | 62b56b3 | 2019-06-21 11:42:29 +0800 | [diff] [blame] | 57 | char reserved3[4]; /* reserved */ |
Peng Fan | b9b4236 | 2018-01-21 19:00:22 +0800 | [diff] [blame] | 58 | uint dmaerraddr; /* DMA error address register */ |
Yangbo Lu | 62b56b3 | 2019-06-21 11:42:29 +0800 | [diff] [blame] | 59 | char reserved4[4]; /* reserved */ |
Peng Fan | b9b4236 | 2018-01-21 19:00:22 +0800 | [diff] [blame] | 60 | uint dmaerrattr; /* DMA error attribute register */ |
Yangbo Lu | 62b56b3 | 2019-06-21 11:42:29 +0800 | [diff] [blame] | 61 | char reserved5[4]; /* reserved */ |
Haijun.Zhang | d49eb9e | 2013-10-30 11:37:55 +0800 | [diff] [blame] | 62 | uint hostcapblt2; /* Host controller capabilities register 2 */ |
Yangbo Lu | 62b56b3 | 2019-06-21 11:42:29 +0800 | [diff] [blame] | 63 | char reserved6[756]; /* reserved */ |
| 64 | uint esdhcctl; /* eSDHC control register */ |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 65 | }; |
| 66 | |
Simon Glass | fa02ca5 | 2017-07-29 11:35:21 -0600 | [diff] [blame] | 67 | struct fsl_esdhc_plat { |
| 68 | struct mmc_config cfg; |
| 69 | struct mmc mmc; |
| 70 | }; |
| 71 | |
Peng Fan | a4d36f7 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 72 | /** |
| 73 | * struct fsl_esdhc_priv |
| 74 | * |
| 75 | * @esdhc_regs: registers of the sdhc controller |
| 76 | * @sdhc_clk: Current clk of the sdhc controller |
| 77 | * @bus_width: bus width, 1bit, 4bit or 8bit |
| 78 | * @cfg: mmc config |
| 79 | * @mmc: mmc |
| 80 | * Following is used when Driver Model is enabled for MMC |
| 81 | * @dev: pointer for the device |
Peng Fan | a4d36f7 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 82 | * @cd_gpio: gpio for card detection |
Peng Fan | 01eb1c4 | 2016-06-15 10:53:02 +0800 | [diff] [blame] | 83 | * @wp_gpio: gpio for write protection |
Peng Fan | a4d36f7 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 84 | */ |
| 85 | struct fsl_esdhc_priv { |
| 86 | struct fsl_esdhc *esdhc_regs; |
| 87 | unsigned int sdhc_clk; |
Yangbo Lu | 1ca7a9f | 2019-12-19 18:59:30 +0800 | [diff] [blame] | 88 | bool is_sdhc_per_clk; |
Peng Fan | c414270 | 2018-01-21 19:00:24 +0800 | [diff] [blame] | 89 | unsigned int clock; |
Yangbo Lu | 77f2632 | 2019-10-21 18:09:07 +0800 | [diff] [blame] | 90 | #if !CONFIG_IS_ENABLED(DM_MMC) |
Peng Fan | a4d36f7 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 91 | struct mmc *mmc; |
Simon Glass | 407025d | 2017-07-29 11:35:24 -0600 | [diff] [blame] | 92 | #endif |
Peng Fan | a4d36f7 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 93 | struct udevice *dev; |
Peng Fan | a4d36f7 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 94 | }; |
| 95 | |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 96 | /* Return the XFERTYP flags for a given command and data packet */ |
Kim Phillips | f9e0b60 | 2012-10-29 13:34:44 +0000 | [diff] [blame] | 97 | static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data) |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 98 | { |
| 99 | uint xfertyp = 0; |
| 100 | |
| 101 | if (data) { |
Dipen Dudhat | 5c72f35 | 2009-10-05 15:41:58 +0530 | [diff] [blame] | 102 | xfertyp |= XFERTYP_DPSEL; |
| 103 | #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO |
| 104 | xfertyp |= XFERTYP_DMAEN; |
| 105 | #endif |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 106 | if (data->blocks > 1) { |
| 107 | xfertyp |= XFERTYP_MSBSEL; |
| 108 | xfertyp |= XFERTYP_BCEN; |
Jerry Huang | ed41367 | 2011-01-06 23:42:19 -0600 | [diff] [blame] | 109 | #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
| 110 | xfertyp |= XFERTYP_AC12EN; |
| 111 | #endif |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 112 | } |
| 113 | |
| 114 | if (data->flags & MMC_DATA_READ) |
| 115 | xfertyp |= XFERTYP_DTDSEL; |
| 116 | } |
| 117 | |
| 118 | if (cmd->resp_type & MMC_RSP_CRC) |
| 119 | xfertyp |= XFERTYP_CCCEN; |
| 120 | if (cmd->resp_type & MMC_RSP_OPCODE) |
| 121 | xfertyp |= XFERTYP_CICEN; |
| 122 | if (cmd->resp_type & MMC_RSP_136) |
| 123 | xfertyp |= XFERTYP_RSPTYP_136; |
| 124 | else if (cmd->resp_type & MMC_RSP_BUSY) |
| 125 | xfertyp |= XFERTYP_RSPTYP_48_BUSY; |
| 126 | else if (cmd->resp_type & MMC_RSP_PRESENT) |
| 127 | xfertyp |= XFERTYP_RSPTYP_48; |
| 128 | |
Jason Liu | bef0ff0 | 2011-03-22 01:32:31 +0000 | [diff] [blame] | 129 | if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) |
| 130 | xfertyp |= XFERTYP_CMDTYP_ABORT; |
Yangbo Lu | b73a3d6 | 2016-01-21 17:33:19 +0800 | [diff] [blame] | 131 | |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 132 | return XFERTYP_CMD(cmd->cmdidx) | xfertyp; |
| 133 | } |
| 134 | |
Dipen Dudhat | 5c72f35 | 2009-10-05 15:41:58 +0530 | [diff] [blame] | 135 | #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO |
| 136 | /* |
| 137 | * PIO Read/Write Mode reduce the performace as DMA is not used in this mode. |
| 138 | */ |
Simon Glass | 1d177d4 | 2017-07-29 11:35:17 -0600 | [diff] [blame] | 139 | static void esdhc_pio_read_write(struct fsl_esdhc_priv *priv, |
| 140 | struct mmc_data *data) |
Dipen Dudhat | 5c72f35 | 2009-10-05 15:41:58 +0530 | [diff] [blame] | 141 | { |
Peng Fan | a4d36f7 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 142 | struct fsl_esdhc *regs = priv->esdhc_regs; |
Dipen Dudhat | 5c72f35 | 2009-10-05 15:41:58 +0530 | [diff] [blame] | 143 | uint blocks; |
| 144 | char *buffer; |
| 145 | uint databuf; |
| 146 | uint size; |
| 147 | uint irqstat; |
Benoît Thébaudeau | 2a7b6f5 | 2017-10-29 22:08:58 +0100 | [diff] [blame] | 148 | ulong start; |
Dipen Dudhat | 5c72f35 | 2009-10-05 15:41:58 +0530 | [diff] [blame] | 149 | |
| 150 | if (data->flags & MMC_DATA_READ) { |
| 151 | blocks = data->blocks; |
| 152 | buffer = data->dest; |
| 153 | while (blocks) { |
Benoît Thébaudeau | 2a7b6f5 | 2017-10-29 22:08:58 +0100 | [diff] [blame] | 154 | start = get_timer(0); |
Dipen Dudhat | 5c72f35 | 2009-10-05 15:41:58 +0530 | [diff] [blame] | 155 | size = data->blocksize; |
| 156 | irqstat = esdhc_read32(®s->irqstat); |
Benoît Thébaudeau | 2a7b6f5 | 2017-10-29 22:08:58 +0100 | [diff] [blame] | 157 | while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BREN)) { |
| 158 | if (get_timer(start) > PIO_TIMEOUT) { |
| 159 | printf("\nData Read Failed in PIO Mode."); |
| 160 | return; |
| 161 | } |
Dipen Dudhat | 5c72f35 | 2009-10-05 15:41:58 +0530 | [diff] [blame] | 162 | } |
| 163 | while (size && (!(irqstat & IRQSTAT_TC))) { |
| 164 | udelay(100); /* Wait before last byte transfer complete */ |
| 165 | irqstat = esdhc_read32(®s->irqstat); |
| 166 | databuf = in_le32(®s->datport); |
| 167 | *((uint *)buffer) = databuf; |
| 168 | buffer += 4; |
| 169 | size -= 4; |
| 170 | } |
| 171 | blocks--; |
| 172 | } |
| 173 | } else { |
| 174 | blocks = data->blocks; |
Wolfgang Denk | a40545c | 2010-05-09 23:52:59 +0200 | [diff] [blame] | 175 | buffer = (char *)data->src; |
Dipen Dudhat | 5c72f35 | 2009-10-05 15:41:58 +0530 | [diff] [blame] | 176 | while (blocks) { |
Benoît Thébaudeau | 2a7b6f5 | 2017-10-29 22:08:58 +0100 | [diff] [blame] | 177 | start = get_timer(0); |
Dipen Dudhat | 5c72f35 | 2009-10-05 15:41:58 +0530 | [diff] [blame] | 178 | size = data->blocksize; |
| 179 | irqstat = esdhc_read32(®s->irqstat); |
Benoît Thébaudeau | 2a7b6f5 | 2017-10-29 22:08:58 +0100 | [diff] [blame] | 180 | while (!(esdhc_read32(®s->prsstat) & PRSSTAT_BWEN)) { |
| 181 | if (get_timer(start) > PIO_TIMEOUT) { |
| 182 | printf("\nData Write Failed in PIO Mode."); |
| 183 | return; |
| 184 | } |
Dipen Dudhat | 5c72f35 | 2009-10-05 15:41:58 +0530 | [diff] [blame] | 185 | } |
| 186 | while (size && (!(irqstat & IRQSTAT_TC))) { |
| 187 | udelay(100); /* Wait before last byte transfer complete */ |
| 188 | databuf = *((uint *)buffer); |
| 189 | buffer += 4; |
| 190 | size -= 4; |
| 191 | irqstat = esdhc_read32(®s->irqstat); |
| 192 | out_le32(®s->datport, databuf); |
| 193 | } |
| 194 | blocks--; |
| 195 | } |
| 196 | } |
| 197 | } |
| 198 | #endif |
| 199 | |
Simon Glass | 1d177d4 | 2017-07-29 11:35:17 -0600 | [diff] [blame] | 200 | static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc, |
| 201 | struct mmc_data *data) |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 202 | { |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 203 | int timeout; |
Peng Fan | a4d36f7 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 204 | struct fsl_esdhc *regs = priv->esdhc_regs; |
Yangbo Lu | 62b56b3 | 2019-06-21 11:42:29 +0800 | [diff] [blame] | 205 | #if defined(CONFIG_FSL_LAYERSCAPE) |
Yangbo Lu | d0e295d | 2015-03-20 19:28:31 -0700 | [diff] [blame] | 206 | dma_addr_t addr; |
| 207 | #endif |
Wolfgang Denk | a40545c | 2010-05-09 23:52:59 +0200 | [diff] [blame] | 208 | uint wml_value; |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 209 | |
| 210 | wml_value = data->blocksize/4; |
| 211 | |
| 212 | if (data->flags & MMC_DATA_READ) { |
Priyanka Jain | 0244963 | 2011-02-09 09:24:10 +0530 | [diff] [blame] | 213 | if (wml_value > WML_RD_WML_MAX) |
| 214 | wml_value = WML_RD_WML_MAX_VAL; |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 215 | |
Roy Zang | e5853af | 2010-02-09 18:23:33 +0800 | [diff] [blame] | 216 | esdhc_clrsetbits32(®s->wml, WML_RD_WML_MASK, wml_value); |
Ye.Li | 33a56b1 | 2014-02-20 18:00:57 +0800 | [diff] [blame] | 217 | #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO |
Yangbo Lu | 62b56b3 | 2019-06-21 11:42:29 +0800 | [diff] [blame] | 218 | #if defined(CONFIG_FSL_LAYERSCAPE) |
Yangbo Lu | d0e295d | 2015-03-20 19:28:31 -0700 | [diff] [blame] | 219 | addr = virt_to_phys((void *)(data->dest)); |
| 220 | if (upper_32_bits(addr)) |
| 221 | printf("Error found for upper 32 bits\n"); |
| 222 | else |
| 223 | esdhc_write32(®s->dsaddr, lower_32_bits(addr)); |
| 224 | #else |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 225 | esdhc_write32(®s->dsaddr, (u32)data->dest); |
Ye.Li | 33a56b1 | 2014-02-20 18:00:57 +0800 | [diff] [blame] | 226 | #endif |
Yangbo Lu | d0e295d | 2015-03-20 19:28:31 -0700 | [diff] [blame] | 227 | #endif |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 228 | } else { |
Ye.Li | 33a56b1 | 2014-02-20 18:00:57 +0800 | [diff] [blame] | 229 | #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO |
Eric Nelson | 30e9cad | 2012-04-25 14:28:48 +0000 | [diff] [blame] | 230 | flush_dcache_range((ulong)data->src, |
| 231 | (ulong)data->src+data->blocks |
| 232 | *data->blocksize); |
Ye.Li | 33a56b1 | 2014-02-20 18:00:57 +0800 | [diff] [blame] | 233 | #endif |
Priyanka Jain | 0244963 | 2011-02-09 09:24:10 +0530 | [diff] [blame] | 234 | if (wml_value > WML_WR_WML_MAX) |
| 235 | wml_value = WML_WR_WML_MAX_VAL; |
Yangbo Lu | f3bcc83 | 2019-10-31 18:54:25 +0800 | [diff] [blame] | 236 | |
| 237 | if (!(esdhc_read32(®s->prsstat) & PRSSTAT_WPSPL)) { |
| 238 | printf("Can not write to locked SD card.\n"); |
| 239 | return -EINVAL; |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 240 | } |
Roy Zang | e5853af | 2010-02-09 18:23:33 +0800 | [diff] [blame] | 241 | |
| 242 | esdhc_clrsetbits32(®s->wml, WML_WR_WML_MASK, |
| 243 | wml_value << 16); |
Ye.Li | 33a56b1 | 2014-02-20 18:00:57 +0800 | [diff] [blame] | 244 | #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO |
Yangbo Lu | 62b56b3 | 2019-06-21 11:42:29 +0800 | [diff] [blame] | 245 | #if defined(CONFIG_FSL_LAYERSCAPE) |
Yangbo Lu | d0e295d | 2015-03-20 19:28:31 -0700 | [diff] [blame] | 246 | addr = virt_to_phys((void *)(data->src)); |
| 247 | if (upper_32_bits(addr)) |
| 248 | printf("Error found for upper 32 bits\n"); |
| 249 | else |
| 250 | esdhc_write32(®s->dsaddr, lower_32_bits(addr)); |
| 251 | #else |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 252 | esdhc_write32(®s->dsaddr, (u32)data->src); |
Ye.Li | 33a56b1 | 2014-02-20 18:00:57 +0800 | [diff] [blame] | 253 | #endif |
Yangbo Lu | d0e295d | 2015-03-20 19:28:31 -0700 | [diff] [blame] | 254 | #endif |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 255 | } |
| 256 | |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 257 | esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize); |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 258 | |
| 259 | /* Calculate the timeout period for data transactions */ |
Priyanka Jain | c51b40d | 2011-03-03 09:18:56 +0530 | [diff] [blame] | 260 | /* |
| 261 | * 1)Timeout period = (2^(timeout+13)) SD Clock cycles |
| 262 | * 2)Timeout period should be minimum 0.250sec as per SD Card spec |
| 263 | * So, Number of SD Clock cycles for 0.25sec should be minimum |
| 264 | * (SD Clock/sec * 0.25 sec) SD Clock cycles |
Andrew Gabbasov | d5b4866 | 2014-03-24 02:40:41 -0500 | [diff] [blame] | 265 | * = (mmc->clock * 1/4) SD Clock cycles |
Priyanka Jain | c51b40d | 2011-03-03 09:18:56 +0530 | [diff] [blame] | 266 | * As 1) >= 2) |
Andrew Gabbasov | d5b4866 | 2014-03-24 02:40:41 -0500 | [diff] [blame] | 267 | * => (2^(timeout+13)) >= mmc->clock * 1/4 |
Priyanka Jain | c51b40d | 2011-03-03 09:18:56 +0530 | [diff] [blame] | 268 | * Taking log2 both the sides |
Andrew Gabbasov | d5b4866 | 2014-03-24 02:40:41 -0500 | [diff] [blame] | 269 | * => timeout + 13 >= log2(mmc->clock/4) |
Priyanka Jain | c51b40d | 2011-03-03 09:18:56 +0530 | [diff] [blame] | 270 | * Rounding up to next power of 2 |
Andrew Gabbasov | d5b4866 | 2014-03-24 02:40:41 -0500 | [diff] [blame] | 271 | * => timeout + 13 = log2(mmc->clock/4) + 1 |
| 272 | * => timeout + 13 = fls(mmc->clock/4) |
Yangbo Lu | 9d7f321 | 2015-12-30 14:19:30 +0800 | [diff] [blame] | 273 | * |
| 274 | * However, the MMC spec "It is strongly recommended for hosts to |
| 275 | * implement more than 500ms timeout value even if the card |
| 276 | * indicates the 250ms maximum busy length." Even the previous |
| 277 | * value of 300ms is known to be insufficient for some cards. |
| 278 | * So, we use |
| 279 | * => timeout + 13 = fls(mmc->clock/2) |
Priyanka Jain | c51b40d | 2011-03-03 09:18:56 +0530 | [diff] [blame] | 280 | */ |
Yangbo Lu | 9d7f321 | 2015-12-30 14:19:30 +0800 | [diff] [blame] | 281 | timeout = fls(mmc->clock/2); |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 282 | timeout -= 13; |
| 283 | |
| 284 | if (timeout > 14) |
| 285 | timeout = 14; |
| 286 | |
| 287 | if (timeout < 0) |
| 288 | timeout = 0; |
| 289 | |
Kumar Gala | 9a878d5 | 2011-01-29 15:36:10 -0600 | [diff] [blame] | 290 | #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001 |
| 291 | if ((timeout == 4) || (timeout == 8) || (timeout == 12)) |
| 292 | timeout++; |
| 293 | #endif |
| 294 | |
Haijun.Zhang | edeb83a | 2014-03-18 17:04:23 +0800 | [diff] [blame] | 295 | #ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE |
| 296 | timeout = 0xE; |
| 297 | #endif |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 298 | esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16); |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 299 | |
| 300 | return 0; |
| 301 | } |
| 302 | |
Eric Nelson | 30e9cad | 2012-04-25 14:28:48 +0000 | [diff] [blame] | 303 | static void check_and_invalidate_dcache_range |
| 304 | (struct mmc_cmd *cmd, |
| 305 | struct mmc_data *data) { |
Yangbo Lu | d0e295d | 2015-03-20 19:28:31 -0700 | [diff] [blame] | 306 | unsigned start = 0; |
Yangbo Lu | e7702c6 | 2016-05-12 19:12:58 +0800 | [diff] [blame] | 307 | unsigned end = 0; |
Eric Nelson | 30e9cad | 2012-04-25 14:28:48 +0000 | [diff] [blame] | 308 | unsigned size = roundup(ARCH_DMA_MINALIGN, |
| 309 | data->blocks*data->blocksize); |
Yangbo Lu | 62b56b3 | 2019-06-21 11:42:29 +0800 | [diff] [blame] | 310 | #if defined(CONFIG_FSL_LAYERSCAPE) |
Yangbo Lu | d0e295d | 2015-03-20 19:28:31 -0700 | [diff] [blame] | 311 | dma_addr_t addr; |
| 312 | |
| 313 | addr = virt_to_phys((void *)(data->dest)); |
| 314 | if (upper_32_bits(addr)) |
| 315 | printf("Error found for upper 32 bits\n"); |
| 316 | else |
| 317 | start = lower_32_bits(addr); |
Yangbo Lu | e7702c6 | 2016-05-12 19:12:58 +0800 | [diff] [blame] | 318 | #else |
| 319 | start = (unsigned)data->dest; |
Yangbo Lu | d0e295d | 2015-03-20 19:28:31 -0700 | [diff] [blame] | 320 | #endif |
Yangbo Lu | e7702c6 | 2016-05-12 19:12:58 +0800 | [diff] [blame] | 321 | end = start + size; |
Eric Nelson | 30e9cad | 2012-04-25 14:28:48 +0000 | [diff] [blame] | 322 | invalidate_dcache_range(start, end); |
| 323 | } |
Angelo Dureghello | 520a669 | 2019-01-19 10:40:38 +0100 | [diff] [blame] | 324 | |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 325 | /* |
| 326 | * Sends a command out on the bus. Takes the mmc pointer, |
| 327 | * a command pointer, and an optional data pointer. |
| 328 | */ |
Simon Glass | 6aa55dc | 2017-07-29 11:35:18 -0600 | [diff] [blame] | 329 | static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc, |
| 330 | struct mmc_cmd *cmd, struct mmc_data *data) |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 331 | { |
Andrew Gabbasov | a04a6e0 | 2014-03-24 02:41:06 -0500 | [diff] [blame] | 332 | int err = 0; |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 333 | uint xfertyp; |
| 334 | uint irqstat; |
Peng Fan | c414270 | 2018-01-21 19:00:24 +0800 | [diff] [blame] | 335 | u32 flags = IRQSTAT_CC | IRQSTAT_CTOE; |
Peng Fan | a4d36f7 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 336 | struct fsl_esdhc *regs = priv->esdhc_regs; |
Fabio Estevam | 7300ef5 | 2018-11-19 10:31:53 -0200 | [diff] [blame] | 337 | unsigned long start; |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 338 | |
Jerry Huang | ed41367 | 2011-01-06 23:42:19 -0600 | [diff] [blame] | 339 | #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111 |
| 340 | if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) |
| 341 | return 0; |
| 342 | #endif |
| 343 | |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 344 | esdhc_write32(®s->irqstat, -1); |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 345 | |
| 346 | sync(); |
| 347 | |
| 348 | /* Wait for the bus to be idle */ |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 349 | while ((esdhc_read32(®s->prsstat) & PRSSTAT_CICHB) || |
| 350 | (esdhc_read32(®s->prsstat) & PRSSTAT_CIDHB)) |
| 351 | ; |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 352 | |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 353 | while (esdhc_read32(®s->prsstat) & PRSSTAT_DLA) |
| 354 | ; |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 355 | |
| 356 | /* Wait at least 8 SD clock cycles before the next command */ |
| 357 | /* |
| 358 | * Note: This is way more than 8 cycles, but 1ms seems to |
| 359 | * resolve timing issues with some cards |
| 360 | */ |
| 361 | udelay(1000); |
| 362 | |
| 363 | /* Set up for a data transfer if we have one */ |
| 364 | if (data) { |
Simon Glass | 1d177d4 | 2017-07-29 11:35:17 -0600 | [diff] [blame] | 365 | err = esdhc_setup_data(priv, mmc, data); |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 366 | if(err) |
| 367 | return err; |
Peng Fan | 9cb5e99 | 2015-06-25 10:32:26 +0800 | [diff] [blame] | 368 | |
| 369 | if (data->flags & MMC_DATA_READ) |
| 370 | check_and_invalidate_dcache_range(cmd, data); |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 371 | } |
| 372 | |
| 373 | /* Figure out the transfer arguments */ |
| 374 | xfertyp = esdhc_xfertyp(cmd, data); |
| 375 | |
Andrew Gabbasov | 4816b7a | 2013-06-11 10:34:22 -0500 | [diff] [blame] | 376 | /* Mask all irqs */ |
| 377 | esdhc_write32(®s->irqsigen, 0); |
| 378 | |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 379 | /* Send the command */ |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 380 | esdhc_write32(®s->cmdarg, cmd->cmdarg); |
| 381 | esdhc_write32(®s->xfertyp, xfertyp); |
Dirk Behme | d8552d6 | 2012-03-26 03:13:05 +0000 | [diff] [blame] | 382 | |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 383 | /* Wait for the command to complete */ |
Fabio Estevam | 7300ef5 | 2018-11-19 10:31:53 -0200 | [diff] [blame] | 384 | start = get_timer(0); |
| 385 | while (!(esdhc_read32(®s->irqstat) & flags)) { |
| 386 | if (get_timer(start) > 1000) { |
| 387 | err = -ETIMEDOUT; |
| 388 | goto out; |
| 389 | } |
| 390 | } |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 391 | |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 392 | irqstat = esdhc_read32(®s->irqstat); |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 393 | |
Andrew Gabbasov | a04a6e0 | 2014-03-24 02:41:06 -0500 | [diff] [blame] | 394 | if (irqstat & CMD_ERR) { |
Jaehoon Chung | 7825d20 | 2016-07-19 16:33:36 +0900 | [diff] [blame] | 395 | err = -ECOMM; |
Andrew Gabbasov | a04a6e0 | 2014-03-24 02:41:06 -0500 | [diff] [blame] | 396 | goto out; |
Dirk Behme | d8552d6 | 2012-03-26 03:13:05 +0000 | [diff] [blame] | 397 | } |
| 398 | |
Andrew Gabbasov | a04a6e0 | 2014-03-24 02:41:06 -0500 | [diff] [blame] | 399 | if (irqstat & IRQSTAT_CTOE) { |
Jaehoon Chung | 7825d20 | 2016-07-19 16:33:36 +0900 | [diff] [blame] | 400 | err = -ETIMEDOUT; |
Andrew Gabbasov | a04a6e0 | 2014-03-24 02:41:06 -0500 | [diff] [blame] | 401 | goto out; |
| 402 | } |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 403 | |
Dirk Behme | d8552d6 | 2012-03-26 03:13:05 +0000 | [diff] [blame] | 404 | /* Workaround for ESDHC errata ENGcm03648 */ |
| 405 | if (!data && (cmd->resp_type & MMC_RSP_BUSY)) { |
Yangbo Lu | 3ffa851 | 2015-04-15 10:13:12 +0800 | [diff] [blame] | 406 | int timeout = 6000; |
Dirk Behme | d8552d6 | 2012-03-26 03:13:05 +0000 | [diff] [blame] | 407 | |
Yangbo Lu | 3ffa851 | 2015-04-15 10:13:12 +0800 | [diff] [blame] | 408 | /* Poll on DATA0 line for cmd with busy signal for 600 ms */ |
Dirk Behme | d8552d6 | 2012-03-26 03:13:05 +0000 | [diff] [blame] | 409 | while (timeout > 0 && !(esdhc_read32(®s->prsstat) & |
| 410 | PRSSTAT_DAT0)) { |
| 411 | udelay(100); |
| 412 | timeout--; |
| 413 | } |
| 414 | |
| 415 | if (timeout <= 0) { |
| 416 | printf("Timeout waiting for DAT0 to go high!\n"); |
Jaehoon Chung | 7825d20 | 2016-07-19 16:33:36 +0900 | [diff] [blame] | 417 | err = -ETIMEDOUT; |
Andrew Gabbasov | a04a6e0 | 2014-03-24 02:41:06 -0500 | [diff] [blame] | 418 | goto out; |
Dirk Behme | d8552d6 | 2012-03-26 03:13:05 +0000 | [diff] [blame] | 419 | } |
| 420 | } |
| 421 | |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 422 | /* Copy the response to the response buffer */ |
| 423 | if (cmd->resp_type & MMC_RSP_136) { |
| 424 | u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0; |
| 425 | |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 426 | cmdrsp3 = esdhc_read32(®s->cmdrsp3); |
| 427 | cmdrsp2 = esdhc_read32(®s->cmdrsp2); |
| 428 | cmdrsp1 = esdhc_read32(®s->cmdrsp1); |
| 429 | cmdrsp0 = esdhc_read32(®s->cmdrsp0); |
Rabin Vincent | b6eed94 | 2009-04-05 13:30:56 +0530 | [diff] [blame] | 430 | cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24); |
| 431 | cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24); |
| 432 | cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24); |
| 433 | cmd->response[3] = (cmdrsp0 << 8); |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 434 | } else |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 435 | cmd->response[0] = esdhc_read32(®s->cmdrsp0); |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 436 | |
| 437 | /* Wait until all of the blocks are transferred */ |
| 438 | if (data) { |
Dipen Dudhat | 5c72f35 | 2009-10-05 15:41:58 +0530 | [diff] [blame] | 439 | #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO |
Simon Glass | 1d177d4 | 2017-07-29 11:35:17 -0600 | [diff] [blame] | 440 | esdhc_pio_read_write(priv, data); |
Dipen Dudhat | 5c72f35 | 2009-10-05 15:41:58 +0530 | [diff] [blame] | 441 | #else |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 442 | do { |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 443 | irqstat = esdhc_read32(®s->irqstat); |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 444 | |
Andrew Gabbasov | a04a6e0 | 2014-03-24 02:41:06 -0500 | [diff] [blame] | 445 | if (irqstat & IRQSTAT_DTOE) { |
Jaehoon Chung | 7825d20 | 2016-07-19 16:33:36 +0900 | [diff] [blame] | 446 | err = -ETIMEDOUT; |
Andrew Gabbasov | a04a6e0 | 2014-03-24 02:41:06 -0500 | [diff] [blame] | 447 | goto out; |
| 448 | } |
Frans Meulenbroeks | 010ba98 | 2010-07-31 04:45:18 +0000 | [diff] [blame] | 449 | |
Andrew Gabbasov | a04a6e0 | 2014-03-24 02:41:06 -0500 | [diff] [blame] | 450 | if (irqstat & DATA_ERR) { |
Jaehoon Chung | 7825d20 | 2016-07-19 16:33:36 +0900 | [diff] [blame] | 451 | err = -ECOMM; |
Andrew Gabbasov | a04a6e0 | 2014-03-24 02:41:06 -0500 | [diff] [blame] | 452 | goto out; |
| 453 | } |
Yinbo Zhu | 101d3ef | 2019-07-16 15:09:11 +0800 | [diff] [blame] | 454 | } while ((irqstat & DATA_COMPLETE) != DATA_COMPLETE); |
Ye.Li | 33a56b1 | 2014-02-20 18:00:57 +0800 | [diff] [blame] | 455 | |
Peng Fan | 9cb5e99 | 2015-06-25 10:32:26 +0800 | [diff] [blame] | 456 | /* |
| 457 | * Need invalidate the dcache here again to avoid any |
| 458 | * cache-fill during the DMA operations such as the |
| 459 | * speculative pre-fetching etc. |
| 460 | */ |
Angelo Dureghello | 520a669 | 2019-01-19 10:40:38 +0100 | [diff] [blame] | 461 | if (data->flags & MMC_DATA_READ) { |
Eric Nelson | 70e6869 | 2013-04-03 12:31:56 +0000 | [diff] [blame] | 462 | check_and_invalidate_dcache_range(cmd, data); |
Angelo Dureghello | 520a669 | 2019-01-19 10:40:38 +0100 | [diff] [blame] | 463 | } |
Ye.Li | 33a56b1 | 2014-02-20 18:00:57 +0800 | [diff] [blame] | 464 | #endif |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 465 | } |
| 466 | |
Andrew Gabbasov | a04a6e0 | 2014-03-24 02:41:06 -0500 | [diff] [blame] | 467 | out: |
| 468 | /* Reset CMD and DATA portions on error */ |
| 469 | if (err) { |
| 470 | esdhc_write32(®s->sysctl, esdhc_read32(®s->sysctl) | |
| 471 | SYSCTL_RSTC); |
| 472 | while (esdhc_read32(®s->sysctl) & SYSCTL_RSTC) |
| 473 | ; |
| 474 | |
| 475 | if (data) { |
| 476 | esdhc_write32(®s->sysctl, |
| 477 | esdhc_read32(®s->sysctl) | |
| 478 | SYSCTL_RSTD); |
| 479 | while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTD)) |
| 480 | ; |
| 481 | } |
| 482 | } |
| 483 | |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 484 | esdhc_write32(®s->irqstat, -1); |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 485 | |
Andrew Gabbasov | a04a6e0 | 2014-03-24 02:41:06 -0500 | [diff] [blame] | 486 | return err; |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 487 | } |
| 488 | |
Simon Glass | 1d177d4 | 2017-07-29 11:35:17 -0600 | [diff] [blame] | 489 | static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock) |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 490 | { |
Benoît Thébaudeau | 22464e0 | 2018-01-16 22:44:18 +0100 | [diff] [blame] | 491 | struct fsl_esdhc *regs = priv->esdhc_regs; |
Benoît Thébaudeau | e16e922 | 2017-05-03 11:59:03 +0200 | [diff] [blame] | 492 | int div = 1; |
Benoît Thébaudeau | e16e922 | 2017-05-03 11:59:03 +0200 | [diff] [blame] | 493 | int pre_div = 2; |
Yinbo Zhu | 101d3ef | 2019-07-16 15:09:11 +0800 | [diff] [blame] | 494 | unsigned int sdhc_clk = priv->sdhc_clk; |
| 495 | u32 time_out; |
| 496 | u32 value; |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 497 | uint clk; |
| 498 | |
Pantelis Antoniou | 2c85046 | 2014-03-11 19:34:20 +0200 | [diff] [blame] | 499 | if (clock < mmc->cfg->f_min) |
| 500 | clock = mmc->cfg->f_min; |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 501 | |
Yangbo Lu | 4ee9b86 | 2019-10-21 18:09:09 +0800 | [diff] [blame] | 502 | while (sdhc_clk / (16 * pre_div) > clock && pre_div < 256) |
Lukasz Majewski | 2a52183 | 2019-05-07 17:47:28 +0200 | [diff] [blame] | 503 | pre_div *= 2; |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 504 | |
Yangbo Lu | 4ee9b86 | 2019-10-21 18:09:09 +0800 | [diff] [blame] | 505 | while (sdhc_clk / (div * pre_div) > clock && div < 16) |
Lukasz Majewski | 2a52183 | 2019-05-07 17:47:28 +0200 | [diff] [blame] | 506 | div++; |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 507 | |
Benoît Thébaudeau | e16e922 | 2017-05-03 11:59:03 +0200 | [diff] [blame] | 508 | pre_div >>= 1; |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 509 | div -= 1; |
| 510 | |
| 511 | clk = (pre_div << 8) | (div << 4); |
| 512 | |
Kumar Gala | 09876a3 | 2010-03-18 15:51:05 -0500 | [diff] [blame] | 513 | esdhc_clrbits32(®s->sysctl, SYSCTL_CKEN); |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 514 | |
| 515 | esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk); |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 516 | |
Yinbo Zhu | 101d3ef | 2019-07-16 15:09:11 +0800 | [diff] [blame] | 517 | time_out = 20; |
| 518 | value = PRSSTAT_SDSTB; |
| 519 | while (!(esdhc_read32(®s->prsstat) & value)) { |
| 520 | if (time_out == 0) { |
| 521 | printf("fsl_esdhc: Internal clock never stabilised.\n"); |
| 522 | break; |
| 523 | } |
| 524 | time_out--; |
| 525 | mdelay(1); |
| 526 | } |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 527 | |
Eric Nelson | c8e615c | 2015-12-04 12:32:48 -0700 | [diff] [blame] | 528 | esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN); |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 529 | } |
| 530 | |
Simon Glass | 1d177d4 | 2017-07-29 11:35:17 -0600 | [diff] [blame] | 531 | static void esdhc_clock_control(struct fsl_esdhc_priv *priv, bool enable) |
Yangbo Lu | 163beec | 2015-04-22 13:57:40 +0800 | [diff] [blame] | 532 | { |
Peng Fan | a4d36f7 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 533 | struct fsl_esdhc *regs = priv->esdhc_regs; |
Yangbo Lu | 163beec | 2015-04-22 13:57:40 +0800 | [diff] [blame] | 534 | u32 value; |
| 535 | u32 time_out; |
| 536 | |
| 537 | value = esdhc_read32(®s->sysctl); |
| 538 | |
| 539 | if (enable) |
| 540 | value |= SYSCTL_CKEN; |
| 541 | else |
| 542 | value &= ~SYSCTL_CKEN; |
| 543 | |
| 544 | esdhc_write32(®s->sysctl, value); |
| 545 | |
| 546 | time_out = 20; |
| 547 | value = PRSSTAT_SDSTB; |
| 548 | while (!(esdhc_read32(®s->prsstat) & value)) { |
| 549 | if (time_out == 0) { |
| 550 | printf("fsl_esdhc: Internal clock never stabilised.\n"); |
| 551 | break; |
| 552 | } |
| 553 | time_out--; |
| 554 | mdelay(1); |
| 555 | } |
Peng Fan | c414270 | 2018-01-21 19:00:24 +0800 | [diff] [blame] | 556 | } |
Yangbo Lu | 163beec | 2015-04-22 13:57:40 +0800 | [diff] [blame] | 557 | |
Simon Glass | 6aa55dc | 2017-07-29 11:35:18 -0600 | [diff] [blame] | 558 | static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc) |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 559 | { |
Peng Fan | a4d36f7 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 560 | struct fsl_esdhc *regs = priv->esdhc_regs; |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 561 | |
Yangbo Lu | 1ca7a9f | 2019-12-19 18:59:30 +0800 | [diff] [blame] | 562 | if (priv->is_sdhc_per_clk) { |
| 563 | /* Select to use peripheral clock */ |
| 564 | esdhc_clock_control(priv, false); |
| 565 | esdhc_setbits32(®s->esdhcctl, ESDHCCTL_PCS); |
| 566 | esdhc_clock_control(priv, true); |
| 567 | } |
| 568 | |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 569 | /* Set the clock speed */ |
Peng Fan | c414270 | 2018-01-21 19:00:24 +0800 | [diff] [blame] | 570 | if (priv->clock != mmc->clock) |
| 571 | set_sysctl(priv, mmc, mmc->clock); |
| 572 | |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 573 | /* Set the bus width */ |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 574 | esdhc_clrbits32(®s->proctl, PROCTL_DTW_4 | PROCTL_DTW_8); |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 575 | |
| 576 | if (mmc->bus_width == 4) |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 577 | esdhc_setbits32(®s->proctl, PROCTL_DTW_4); |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 578 | else if (mmc->bus_width == 8) |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 579 | esdhc_setbits32(®s->proctl, PROCTL_DTW_8); |
| 580 | |
Jaehoon Chung | b6cd1d3 | 2016-12-30 15:30:16 +0900 | [diff] [blame] | 581 | return 0; |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 582 | } |
| 583 | |
Rasmus Villemoes | a6d1f1a | 2020-01-30 12:06:45 +0000 | [diff] [blame] | 584 | static void esdhc_enable_cache_snooping(struct fsl_esdhc *regs) |
| 585 | { |
| 586 | #ifdef CONFIG_ARCH_MPC830X |
| 587 | immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; |
| 588 | sysconf83xx_t *sysconf = &immr->sysconf; |
| 589 | |
| 590 | setbits_be32(&sysconf->sdhccr, 0x02000000); |
| 591 | #else |
| 592 | esdhc_write32(®s->esdhcctl, 0x00000040); |
| 593 | #endif |
| 594 | } |
| 595 | |
Simon Glass | 6aa55dc | 2017-07-29 11:35:18 -0600 | [diff] [blame] | 596 | static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc) |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 597 | { |
Peng Fan | a4d36f7 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 598 | struct fsl_esdhc *regs = priv->esdhc_regs; |
Simon Glass | 0c3ef22 | 2017-07-29 11:35:20 -0600 | [diff] [blame] | 599 | ulong start; |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 600 | |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 601 | /* Reset the entire host controller */ |
Dirk Behme | dbe6725 | 2013-07-15 15:44:29 +0200 | [diff] [blame] | 602 | esdhc_setbits32(®s->sysctl, SYSCTL_RSTA); |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 603 | |
| 604 | /* Wait until the controller is available */ |
Simon Glass | 0c3ef22 | 2017-07-29 11:35:20 -0600 | [diff] [blame] | 605 | start = get_timer(0); |
| 606 | while ((esdhc_read32(®s->sysctl) & SYSCTL_RSTA)) { |
| 607 | if (get_timer(start) > 1000) |
| 608 | return -ETIMEDOUT; |
| 609 | } |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 610 | |
Rasmus Villemoes | a6d1f1a | 2020-01-30 12:06:45 +0000 | [diff] [blame] | 611 | esdhc_enable_cache_snooping(regs); |
P.V.Suresh | 7b1868b | 2010-12-04 10:37:23 +0530 | [diff] [blame] | 612 | |
Dirk Behme | dbe6725 | 2013-07-15 15:44:29 +0200 | [diff] [blame] | 613 | esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN); |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 614 | |
| 615 | /* Set the initial clock speed */ |
Jaehoon Chung | 239cb2f | 2018-01-26 19:25:29 +0900 | [diff] [blame] | 616 | mmc_set_clock(mmc, 400000, MMC_CLK_ENABLE); |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 617 | |
| 618 | /* Disable the BRR and BWR bits in IRQSTAT */ |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 619 | esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR); |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 620 | |
| 621 | /* Put the PROCTL reg back to the default */ |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 622 | esdhc_write32(®s->proctl, PROCTL_INIT); |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 623 | |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 624 | /* Set timout to the maximum value */ |
| 625 | esdhc_clrsetbits32(®s->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16); |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 626 | |
Thierry Reding | 8cee4c98 | 2012-01-02 01:15:38 +0000 | [diff] [blame] | 627 | return 0; |
| 628 | } |
| 629 | |
Simon Glass | 6aa55dc | 2017-07-29 11:35:18 -0600 | [diff] [blame] | 630 | static int esdhc_getcd_common(struct fsl_esdhc_priv *priv) |
Thierry Reding | 8cee4c98 | 2012-01-02 01:15:38 +0000 | [diff] [blame] | 631 | { |
Peng Fan | a4d36f7 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 632 | struct fsl_esdhc *regs = priv->esdhc_regs; |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 633 | |
Haijun.Zhang | 05f5854 | 2014-01-10 13:52:17 +0800 | [diff] [blame] | 634 | #ifdef CONFIG_ESDHC_DETECT_QUIRK |
| 635 | if (CONFIG_ESDHC_DETECT_QUIRK) |
| 636 | return 1; |
| 637 | #endif |
Yangbo Lu | 8abc043 | 2020-05-19 11:06:43 +0800 | [diff] [blame] | 638 | if (esdhc_read32(®s->prsstat) & PRSSTAT_CINS) |
| 639 | return 1; |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 640 | |
Yangbo Lu | 8abc043 | 2020-05-19 11:06:43 +0800 | [diff] [blame] | 641 | return 0; |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 642 | } |
| 643 | |
Yangbo Lu | b64dc8d | 2019-10-31 18:54:23 +0800 | [diff] [blame] | 644 | static void fsl_esdhc_get_cfg_common(struct fsl_esdhc_priv *priv, |
| 645 | struct mmc_config *cfg) |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 646 | { |
Yangbo Lu | b64dc8d | 2019-10-31 18:54:23 +0800 | [diff] [blame] | 647 | struct fsl_esdhc *regs = priv->esdhc_regs; |
Yangbo Lu | 63267b4 | 2019-10-31 18:54:21 +0800 | [diff] [blame] | 648 | u32 caps; |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 649 | |
Wang Huan | c929213 | 2014-09-05 13:52:40 +0800 | [diff] [blame] | 650 | caps = esdhc_read32(®s->hostcapblt); |
Roy Zang | 3935661 | 2011-01-07 00:06:47 -0600 | [diff] [blame] | 651 | #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135 |
Yangbo Lu | 63267b4 | 2019-10-31 18:54:21 +0800 | [diff] [blame] | 652 | caps &= ~(HOSTCAPBLT_SRS | HOSTCAPBLT_VS18 | HOSTCAPBLT_VS30); |
Roy Zang | 3935661 | 2011-01-07 00:06:47 -0600 | [diff] [blame] | 653 | #endif |
Haijun.Zhang | 8a065e9 | 2013-10-31 09:38:19 +0800 | [diff] [blame] | 654 | #ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 |
Yangbo Lu | 63267b4 | 2019-10-31 18:54:21 +0800 | [diff] [blame] | 655 | caps |= HOSTCAPBLT_VS33; |
Haijun.Zhang | 8a065e9 | 2013-10-31 09:38:19 +0800 | [diff] [blame] | 656 | #endif |
Yangbo Lu | 63267b4 | 2019-10-31 18:54:21 +0800 | [diff] [blame] | 657 | if (caps & HOSTCAPBLT_VS18) |
| 658 | cfg->voltages |= MMC_VDD_165_195; |
| 659 | if (caps & HOSTCAPBLT_VS30) |
| 660 | cfg->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31; |
| 661 | if (caps & HOSTCAPBLT_VS33) |
| 662 | cfg->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34; |
Li Yang | d4933f2 | 2010-11-25 17:06:09 +0000 | [diff] [blame] | 663 | |
Simon Glass | fa02ca5 | 2017-07-29 11:35:21 -0600 | [diff] [blame] | 664 | cfg->name = "FSL_SDHC"; |
Abbas Raza | e6bf977 | 2013-03-25 09:13:34 +0000 | [diff] [blame] | 665 | |
Yangbo Lu | 63267b4 | 2019-10-31 18:54:21 +0800 | [diff] [blame] | 666 | if (caps & HOSTCAPBLT_HSS) |
Simon Glass | fa02ca5 | 2017-07-29 11:35:21 -0600 | [diff] [blame] | 667 | cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; |
Andy Fleming | e52ffb8 | 2008-10-30 16:47:16 -0500 | [diff] [blame] | 668 | |
Simon Glass | fa02ca5 | 2017-07-29 11:35:21 -0600 | [diff] [blame] | 669 | cfg->f_min = 400000; |
Peng Fan | c414270 | 2018-01-21 19:00:24 +0800 | [diff] [blame] | 670 | cfg->f_max = min(priv->sdhc_clk, (u32)200000000); |
Simon Glass | fa02ca5 | 2017-07-29 11:35:21 -0600 | [diff] [blame] | 671 | cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT; |
Peng Fan | a4d36f7 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 672 | } |
Anton Vorontsov | f751a3c | 2009-06-10 00:25:29 +0400 | [diff] [blame] | 673 | |
Yangbo Lu | b124f8a | 2015-04-22 13:57:00 +0800 | [diff] [blame] | 674 | #ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT |
| 675 | void mmc_adapter_card_type_ident(void) |
| 676 | { |
| 677 | u8 card_id; |
| 678 | u8 value; |
| 679 | |
| 680 | card_id = QIXIS_READ(present) & QIXIS_SDID_MASK; |
| 681 | gd->arch.sdhc_adapter = card_id; |
| 682 | |
| 683 | switch (card_id) { |
| 684 | case QIXIS_ESDHC_ADAPTER_TYPE_EMMC45: |
Yangbo Lu | 81eacd6 | 2015-09-17 10:27:12 +0800 | [diff] [blame] | 685 | value = QIXIS_READ(brdcfg[5]); |
| 686 | value |= (QIXIS_DAT4 | QIXIS_DAT5_6_7); |
| 687 | QIXIS_WRITE(brdcfg[5], value); |
Yangbo Lu | b124f8a | 2015-04-22 13:57:00 +0800 | [diff] [blame] | 688 | break; |
| 689 | case QIXIS_ESDHC_ADAPTER_TYPE_SDMMC_LEGACY: |
Yangbo Lu | c6799ce | 2015-09-17 10:27:48 +0800 | [diff] [blame] | 690 | value = QIXIS_READ(pwr_ctl[1]); |
| 691 | value |= QIXIS_EVDD_BY_SDHC_VS; |
| 692 | QIXIS_WRITE(pwr_ctl[1], value); |
Yangbo Lu | b124f8a | 2015-04-22 13:57:00 +0800 | [diff] [blame] | 693 | break; |
| 694 | case QIXIS_ESDHC_ADAPTER_TYPE_EMMC44: |
| 695 | value = QIXIS_READ(brdcfg[5]); |
| 696 | value |= (QIXIS_SDCLKIN | QIXIS_SDCLKOUT); |
| 697 | QIXIS_WRITE(brdcfg[5], value); |
| 698 | break; |
| 699 | case QIXIS_ESDHC_ADAPTER_TYPE_RSV: |
| 700 | break; |
| 701 | case QIXIS_ESDHC_ADAPTER_TYPE_MMC: |
| 702 | break; |
| 703 | case QIXIS_ESDHC_ADAPTER_TYPE_SD: |
| 704 | break; |
| 705 | case QIXIS_ESDHC_NO_ADAPTER: |
| 706 | break; |
| 707 | default: |
| 708 | break; |
| 709 | } |
| 710 | } |
| 711 | #endif |
| 712 | |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 713 | #ifdef CONFIG_OF_LIBFDT |
Yangbo Lu | d84139c | 2017-01-17 10:43:54 +0800 | [diff] [blame] | 714 | __weak int esdhc_status_fixup(void *blob, const char *compat) |
Anton Vorontsov | f751a3c | 2009-06-10 00:25:29 +0400 | [diff] [blame] | 715 | { |
Chenhui Zhao | 025eab0 | 2011-01-04 17:23:05 +0800 | [diff] [blame] | 716 | #ifdef CONFIG_FSL_ESDHC_PIN_MUX |
Anton Vorontsov | f751a3c | 2009-06-10 00:25:29 +0400 | [diff] [blame] | 717 | if (!hwconfig("esdhc")) { |
Chenhui Zhao | 025eab0 | 2011-01-04 17:23:05 +0800 | [diff] [blame] | 718 | do_fixup_by_compat(blob, compat, "status", "disabled", |
Yangbo Lu | d84139c | 2017-01-17 10:43:54 +0800 | [diff] [blame] | 719 | sizeof("disabled"), 1); |
| 720 | return 1; |
Anton Vorontsov | f751a3c | 2009-06-10 00:25:29 +0400 | [diff] [blame] | 721 | } |
Chenhui Zhao | 025eab0 | 2011-01-04 17:23:05 +0800 | [diff] [blame] | 722 | #endif |
Yangbo Lu | d84139c | 2017-01-17 10:43:54 +0800 | [diff] [blame] | 723 | return 0; |
| 724 | } |
| 725 | |
Yangbo Lu | ce88402 | 2020-05-19 11:06:44 +0800 | [diff] [blame] | 726 | #ifdef CONFIG_FSL_ESDHC_33V_IO_RELIABILITY_WORKAROUND |
| 727 | static int fsl_esdhc_get_cd(struct udevice *dev); |
| 728 | |
| 729 | static void esdhc_disable_for_no_card(void *blob) |
| 730 | { |
| 731 | struct udevice *dev; |
| 732 | |
| 733 | for (uclass_first_device(UCLASS_MMC, &dev); |
| 734 | dev; |
| 735 | uclass_next_device(&dev)) { |
| 736 | char esdhc_path[50]; |
| 737 | |
| 738 | if (fsl_esdhc_get_cd(dev)) |
| 739 | continue; |
| 740 | |
| 741 | snprintf(esdhc_path, sizeof(esdhc_path), "/soc/esdhc@%lx", |
| 742 | (unsigned long)dev_read_addr(dev)); |
| 743 | do_fixup_by_path(blob, esdhc_path, "status", "disabled", |
| 744 | sizeof("disabled"), 1); |
| 745 | } |
| 746 | } |
| 747 | #endif |
| 748 | |
Yangbo Lu | d84139c | 2017-01-17 10:43:54 +0800 | [diff] [blame] | 749 | void fdt_fixup_esdhc(void *blob, bd_t *bd) |
| 750 | { |
| 751 | const char *compat = "fsl,esdhc"; |
| 752 | |
| 753 | if (esdhc_status_fixup(blob, compat)) |
| 754 | return; |
Yangbo Lu | ce88402 | 2020-05-19 11:06:44 +0800 | [diff] [blame] | 755 | #ifdef CONFIG_FSL_ESDHC_33V_IO_RELIABILITY_WORKAROUND |
| 756 | esdhc_disable_for_no_card(blob); |
| 757 | #endif |
Anton Vorontsov | f751a3c | 2009-06-10 00:25:29 +0400 | [diff] [blame] | 758 | do_fixup_by_compat_u32(blob, compat, "clock-frequency", |
Simon Glass | 9e247d1 | 2012-12-13 20:49:05 +0000 | [diff] [blame] | 759 | gd->arch.sdhc_clk, 1); |
Anton Vorontsov | f751a3c | 2009-06-10 00:25:29 +0400 | [diff] [blame] | 760 | } |
Stefano Babic | ff7a5ca | 2010-02-05 15:11:27 +0100 | [diff] [blame] | 761 | #endif |
Peng Fan | a4d36f7 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 762 | |
Yangbo Lu | 4fc9333 | 2019-10-31 18:54:26 +0800 | [diff] [blame] | 763 | #if !CONFIG_IS_ENABLED(DM_MMC) |
| 764 | static int esdhc_getcd(struct mmc *mmc) |
| 765 | { |
| 766 | struct fsl_esdhc_priv *priv = mmc->priv; |
| 767 | |
| 768 | return esdhc_getcd_common(priv); |
| 769 | } |
| 770 | |
| 771 | static int esdhc_init(struct mmc *mmc) |
| 772 | { |
| 773 | struct fsl_esdhc_priv *priv = mmc->priv; |
| 774 | |
| 775 | return esdhc_init_common(priv, mmc); |
| 776 | } |
| 777 | |
| 778 | static int esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, |
| 779 | struct mmc_data *data) |
| 780 | { |
| 781 | struct fsl_esdhc_priv *priv = mmc->priv; |
| 782 | |
| 783 | return esdhc_send_cmd_common(priv, mmc, cmd, data); |
| 784 | } |
| 785 | |
| 786 | static int esdhc_set_ios(struct mmc *mmc) |
| 787 | { |
| 788 | struct fsl_esdhc_priv *priv = mmc->priv; |
| 789 | |
| 790 | return esdhc_set_ios_common(priv, mmc); |
| 791 | } |
| 792 | |
| 793 | static const struct mmc_ops esdhc_ops = { |
| 794 | .getcd = esdhc_getcd, |
| 795 | .init = esdhc_init, |
| 796 | .send_cmd = esdhc_send_cmd, |
| 797 | .set_ios = esdhc_set_ios, |
| 798 | }; |
| 799 | |
| 800 | int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) |
| 801 | { |
| 802 | struct fsl_esdhc_plat *plat; |
| 803 | struct fsl_esdhc_priv *priv; |
| 804 | struct mmc_config *mmc_cfg; |
| 805 | struct mmc *mmc; |
| 806 | |
| 807 | if (!cfg) |
| 808 | return -EINVAL; |
| 809 | |
| 810 | priv = calloc(sizeof(struct fsl_esdhc_priv), 1); |
| 811 | if (!priv) |
| 812 | return -ENOMEM; |
| 813 | plat = calloc(sizeof(struct fsl_esdhc_plat), 1); |
| 814 | if (!plat) { |
| 815 | free(priv); |
| 816 | return -ENOMEM; |
| 817 | } |
| 818 | |
| 819 | priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base); |
| 820 | priv->sdhc_clk = cfg->sdhc_clk; |
Yangbo Lu | 1ca7a9f | 2019-12-19 18:59:30 +0800 | [diff] [blame] | 821 | if (gd->arch.sdhc_per_clk) |
| 822 | priv->is_sdhc_per_clk = true; |
Yangbo Lu | 4fc9333 | 2019-10-31 18:54:26 +0800 | [diff] [blame] | 823 | |
| 824 | mmc_cfg = &plat->cfg; |
| 825 | |
| 826 | if (cfg->max_bus_width == 8) { |
| 827 | mmc_cfg->host_caps |= MMC_MODE_1BIT | MMC_MODE_4BIT | |
| 828 | MMC_MODE_8BIT; |
| 829 | } else if (cfg->max_bus_width == 4) { |
| 830 | mmc_cfg->host_caps |= MMC_MODE_1BIT | MMC_MODE_4BIT; |
| 831 | } else if (cfg->max_bus_width == 1) { |
| 832 | mmc_cfg->host_caps |= MMC_MODE_1BIT; |
| 833 | } else { |
| 834 | mmc_cfg->host_caps |= MMC_MODE_1BIT | MMC_MODE_4BIT | |
| 835 | MMC_MODE_8BIT; |
| 836 | printf("No max bus width provided. Assume 8-bit supported.\n"); |
| 837 | } |
| 838 | |
| 839 | #ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK |
| 840 | if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK) |
| 841 | mmc_cfg->host_caps &= ~MMC_MODE_8BIT; |
| 842 | #endif |
| 843 | mmc_cfg->ops = &esdhc_ops; |
| 844 | |
| 845 | fsl_esdhc_get_cfg_common(priv, mmc_cfg); |
| 846 | |
| 847 | mmc = mmc_create(mmc_cfg, priv); |
| 848 | if (!mmc) |
| 849 | return -EIO; |
| 850 | |
| 851 | priv->mmc = mmc; |
| 852 | return 0; |
| 853 | } |
| 854 | |
| 855 | int fsl_esdhc_mmc_init(bd_t *bis) |
| 856 | { |
| 857 | struct fsl_esdhc_cfg *cfg; |
| 858 | |
| 859 | cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1); |
| 860 | cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR; |
Yangbo Lu | 1ca7a9f | 2019-12-19 18:59:30 +0800 | [diff] [blame] | 861 | /* Prefer peripheral clock which provides higher frequency. */ |
| 862 | if (gd->arch.sdhc_per_clk) |
| 863 | cfg->sdhc_clk = gd->arch.sdhc_per_clk; |
| 864 | else |
| 865 | cfg->sdhc_clk = gd->arch.sdhc_clk; |
Yangbo Lu | 4fc9333 | 2019-10-31 18:54:26 +0800 | [diff] [blame] | 866 | return fsl_esdhc_initialize(bis, cfg); |
| 867 | } |
| 868 | #else /* DM_MMC */ |
Peng Fan | a4d36f7 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 869 | static int fsl_esdhc_probe(struct udevice *dev) |
| 870 | { |
| 871 | struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); |
Simon Glass | fa02ca5 | 2017-07-29 11:35:21 -0600 | [diff] [blame] | 872 | struct fsl_esdhc_plat *plat = dev_get_platdata(dev); |
Peng Fan | a4d36f7 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 873 | struct fsl_esdhc_priv *priv = dev_get_priv(dev); |
Peng Fan | a4d36f7 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 874 | fdt_addr_t addr; |
Simon Glass | 407025d | 2017-07-29 11:35:24 -0600 | [diff] [blame] | 875 | struct mmc *mmc; |
Yangbo Lu | ce88402 | 2020-05-19 11:06:44 +0800 | [diff] [blame] | 876 | int ret; |
Peng Fan | a4d36f7 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 877 | |
Simon Glass | 80e9df4 | 2017-07-29 11:35:23 -0600 | [diff] [blame] | 878 | addr = dev_read_addr(dev); |
Peng Fan | a4d36f7 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 879 | if (addr == FDT_ADDR_T_NONE) |
| 880 | return -EINVAL; |
Yinbo Zhu | 583d5e9 | 2019-04-11 11:01:50 +0000 | [diff] [blame] | 881 | #ifdef CONFIG_PPC |
| 882 | priv->esdhc_regs = (struct fsl_esdhc *)lower_32_bits(addr); |
| 883 | #else |
Peng Fan | a4d36f7 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 884 | priv->esdhc_regs = (struct fsl_esdhc *)addr; |
Yinbo Zhu | 583d5e9 | 2019-04-11 11:01:50 +0000 | [diff] [blame] | 885 | #endif |
Peng Fan | a4d36f7 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 886 | priv->dev = dev; |
| 887 | |
Yangbo Lu | 1ca7a9f | 2019-12-19 18:59:30 +0800 | [diff] [blame] | 888 | if (gd->arch.sdhc_per_clk) { |
| 889 | priv->sdhc_clk = gd->arch.sdhc_per_clk; |
| 890 | priv->is_sdhc_per_clk = true; |
| 891 | } else { |
| 892 | priv->sdhc_clk = gd->arch.sdhc_clk; |
| 893 | } |
| 894 | |
Yangbo Lu | b8626e4 | 2019-11-12 19:28:36 +0800 | [diff] [blame] | 895 | if (priv->sdhc_clk <= 0) { |
| 896 | dev_err(dev, "Unable to get clk for %s\n", dev->name); |
| 897 | return -EINVAL; |
Peng Fan | a4d36f7 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 898 | } |
| 899 | |
Yangbo Lu | b64dc8d | 2019-10-31 18:54:23 +0800 | [diff] [blame] | 900 | fsl_esdhc_get_cfg_common(priv, &plat->cfg); |
Peng Fan | a4d36f7 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 901 | |
Yinbo Zhu | 101d3ef | 2019-07-16 15:09:11 +0800 | [diff] [blame] | 902 | mmc_of_parse(dev, &plat->cfg); |
| 903 | |
Simon Glass | 407025d | 2017-07-29 11:35:24 -0600 | [diff] [blame] | 904 | mmc = &plat->mmc; |
| 905 | mmc->cfg = &plat->cfg; |
| 906 | mmc->dev = dev; |
Yangbo Lu | 4cc119b | 2019-05-23 11:05:46 +0800 | [diff] [blame] | 907 | |
Simon Glass | 407025d | 2017-07-29 11:35:24 -0600 | [diff] [blame] | 908 | upriv->mmc = mmc; |
Peng Fan | a4d36f7 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 909 | |
Yangbo Lu | ce88402 | 2020-05-19 11:06:44 +0800 | [diff] [blame] | 910 | ret = esdhc_init_common(priv, mmc); |
| 911 | if (ret) |
| 912 | return ret; |
| 913 | |
| 914 | #ifdef CONFIG_FSL_ESDHC_33V_IO_RELIABILITY_WORKAROUND |
| 915 | if (!fsl_esdhc_get_cd(dev)) |
| 916 | esdhc_setbits32(&priv->esdhc_regs->proctl, PROCTL_VOLT_SEL); |
| 917 | #endif |
| 918 | return 0; |
Peng Fan | a4d36f7 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 919 | } |
| 920 | |
Simon Glass | 407025d | 2017-07-29 11:35:24 -0600 | [diff] [blame] | 921 | static int fsl_esdhc_get_cd(struct udevice *dev) |
| 922 | { |
Yangbo Lu | 9fed28d | 2019-10-31 18:54:24 +0800 | [diff] [blame] | 923 | struct fsl_esdhc_plat *plat = dev_get_platdata(dev); |
Simon Glass | 407025d | 2017-07-29 11:35:24 -0600 | [diff] [blame] | 924 | struct fsl_esdhc_priv *priv = dev_get_priv(dev); |
| 925 | |
Yangbo Lu | 9fed28d | 2019-10-31 18:54:24 +0800 | [diff] [blame] | 926 | if (plat->cfg.host_caps & MMC_CAP_NONREMOVABLE) |
| 927 | return 1; |
| 928 | |
Simon Glass | 407025d | 2017-07-29 11:35:24 -0600 | [diff] [blame] | 929 | return esdhc_getcd_common(priv); |
| 930 | } |
| 931 | |
| 932 | static int fsl_esdhc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, |
| 933 | struct mmc_data *data) |
| 934 | { |
| 935 | struct fsl_esdhc_plat *plat = dev_get_platdata(dev); |
| 936 | struct fsl_esdhc_priv *priv = dev_get_priv(dev); |
| 937 | |
| 938 | return esdhc_send_cmd_common(priv, &plat->mmc, cmd, data); |
| 939 | } |
| 940 | |
| 941 | static int fsl_esdhc_set_ios(struct udevice *dev) |
| 942 | { |
| 943 | struct fsl_esdhc_plat *plat = dev_get_platdata(dev); |
| 944 | struct fsl_esdhc_priv *priv = dev_get_priv(dev); |
| 945 | |
| 946 | return esdhc_set_ios_common(priv, &plat->mmc); |
| 947 | } |
| 948 | |
| 949 | static const struct dm_mmc_ops fsl_esdhc_ops = { |
| 950 | .get_cd = fsl_esdhc_get_cd, |
| 951 | .send_cmd = fsl_esdhc_send_cmd, |
| 952 | .set_ios = fsl_esdhc_set_ios, |
Yinbo Zhu | 101d3ef | 2019-07-16 15:09:11 +0800 | [diff] [blame] | 953 | #ifdef MMC_SUPPORTS_TUNING |
| 954 | .execute_tuning = fsl_esdhc_execute_tuning, |
| 955 | #endif |
Simon Glass | 407025d | 2017-07-29 11:35:24 -0600 | [diff] [blame] | 956 | }; |
Simon Glass | 407025d | 2017-07-29 11:35:24 -0600 | [diff] [blame] | 957 | |
Peng Fan | a4d36f7 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 958 | static const struct udevice_id fsl_esdhc_ids[] = { |
Yangbo Lu | 2a99b60 | 2016-12-07 11:54:31 +0800 | [diff] [blame] | 959 | { .compatible = "fsl,esdhc", }, |
Peng Fan | a4d36f7 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 960 | { /* sentinel */ } |
| 961 | }; |
| 962 | |
Simon Glass | 407025d | 2017-07-29 11:35:24 -0600 | [diff] [blame] | 963 | static int fsl_esdhc_bind(struct udevice *dev) |
| 964 | { |
| 965 | struct fsl_esdhc_plat *plat = dev_get_platdata(dev); |
| 966 | |
| 967 | return mmc_bind(dev, &plat->mmc, &plat->cfg); |
| 968 | } |
Simon Glass | 407025d | 2017-07-29 11:35:24 -0600 | [diff] [blame] | 969 | |
Peng Fan | a4d36f7 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 970 | U_BOOT_DRIVER(fsl_esdhc) = { |
| 971 | .name = "fsl-esdhc-mmc", |
| 972 | .id = UCLASS_MMC, |
| 973 | .of_match = fsl_esdhc_ids, |
Simon Glass | 407025d | 2017-07-29 11:35:24 -0600 | [diff] [blame] | 974 | .ops = &fsl_esdhc_ops, |
Simon Glass | 407025d | 2017-07-29 11:35:24 -0600 | [diff] [blame] | 975 | .bind = fsl_esdhc_bind, |
Peng Fan | a4d36f7 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 976 | .probe = fsl_esdhc_probe, |
Simon Glass | fa02ca5 | 2017-07-29 11:35:21 -0600 | [diff] [blame] | 977 | .platdata_auto_alloc_size = sizeof(struct fsl_esdhc_plat), |
Peng Fan | a4d36f7 | 2016-03-25 14:16:56 +0800 | [diff] [blame] | 978 | .priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv), |
| 979 | }; |
| 980 | #endif |