commit 2a521834487693f18331aa856adc920104a1a074
author Lukasz Majewski <lukma@denx.de> Tue May 07 17:47:28 2019 +0200
committer Peng Fan <peng.fan@nxp.com> Mon May 20 11:34:27 2019 +0800
tree f4c6d202d0097a6adc6529b00f478490d58e5d7d
parent c30b8224516aa13d6eb4b943c552b2cb71dde3cb

Revert "mmc: fsl_esdhc: fix sd/mmc ddr mode clock setting issue"

This reverts commit 72a89e0da5ac6a4ab929b15a2b656f04f50767f6, which
causes the imx53 HSC to hang as the eMMC is not working properly anymore.

The exact error message:
MMC write: dev # 0, block # 2, count 927 ... mmc write failed
0 blocks written: ERROR

imx53 is not using the DDR mode.

Debugging of pre_div and div generation showed that those values are
generated in a way, which is not matching the ones from working setup.

As the original patch was performing code refactoring, let's revert this
change, so all imx53 boards would work again.

Signed-off-by: Lukasz Majewski <lukma@denx.de>

drivers/mmc/fsl_esdhc.c

diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 1b7de74..377b267 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -621,31 +621,18 @@
 #else
 	int pre_div = 2;
 #endif
+	int ddr_pre_div = mmc->ddr_mode ? 2 : 1;
 	int sdhc_clk = priv->sdhc_clk;
 	uint clk;
 
-	/*
-	 * For ddr mode, usdhc need to enable DDR mode first, after select
-	 * this DDR mode, usdhc will automatically divide the usdhc clock
-	 */
-	if (mmc->ddr_mode) {
-		writel(readl(&regs->mixctrl) | MIX_CTRL_DDREN, &regs->mixctrl);
-		sdhc_clk >>= 1;
-	}
-
 	if (clock < mmc->cfg->f_min)
 		clock = mmc->cfg->f_min;
 
-	if (sdhc_clk / 16 > clock) {
-		for (; pre_div < 256; pre_div *= 2)
-			if ((sdhc_clk / pre_div) <= (clock * 16))
-				break;
-	} else
-		pre_div = 1;
+	while (sdhc_clk / (16 * pre_div * ddr_pre_div) > clock && pre_div < 256)
+		pre_div *= 2;
 
-	for (div = 1; div <= 16; div++)
-		if ((sdhc_clk / (div * pre_div)) <= clock)
-			break;
+	while (sdhc_clk / (div * pre_div * ddr_pre_div) > clock && div < 16)
+		div++;
 
 	pre_div >>= 1;
 	div -= 1;