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git01.mediatek.com / filogic / uboot / 41aacdd714e650abd803909abb46911a61aa219b / . / configs / chromebook_minnie_defconfig
blob: 086b6a592945d4e1f6ae9df99a315c0d9ad946ba [file] [log] [blame]
Simon Glasse51b2e72016-11-13 14:24:54 -0700[diff] [blame]1CONFIG_ARM=y
2CONFIG_ARCH_ROCKCHIP=y
Tom Rini07edfae2018-02-03 12:10:38 -0500[diff] [blame]3CONFIG_SYS_TEXT_BASE=0x00100000
Simon Glasse51b2e72016-11-13 14:24:54 -0700[diff] [blame]4CONFIG_SYS_MALLOC_F_LEN=0x2000
Simon Glasse51b2e72016-11-13 14:24:54 -0700[diff] [blame]5CONFIG_ROCKCHIP_RK3288=y
Tom Rini9834b902017-03-13 13:48:42 -0400[diff] [blame]6# CONFIG_SPL_MMC_SUPPORT is not set
Simon Glasse51b2e72016-11-13 14:24:54 -0700[diff] [blame]7CONFIG_TARGET_CHROMEBOOK_MINNIE=y
Tom Rinie0056d72018-06-04 11:57:37 -0400[diff] [blame]8CONFIG_DEBUG_UART_BASE=0xff690000
9CONFIG_DEBUG_UART_CLOCK=24000000
10CONFIG_SPL_STACK_R_ADDR=0x80000
Simon Glasse51b2e72016-11-13 14:24:54 -0700[diff] [blame]11CONFIG_SPL_SPI_FLASH_SUPPORT=y
12CONFIG_SPL_SPI_SUPPORT=y
Simon Glasse51b2e72016-11-13 14:24:54 -0700[diff] [blame]13CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-minnie"
Tom Rini256aa742017-06-19 09:47:40 -0400[diff] [blame]14CONFIG_DEBUG_UART=y
Tom Rinif2260382018-08-16 08:16:24 -0400[diff] [blame]15CONFIG_NR_DRAM_BANKS=1
Tom Rinib5bf5622017-08-25 17:50:27 -0400[diff] [blame]16# CONFIG_ANDROID_BOOT_IMAGE is not set
Simon Glasse51b2e72016-11-13 14:24:54 -0700[diff] [blame]17CONFIG_SILENT_CONSOLE=y
Klaus Goger2b6b4f22018-05-25 23:45:05 +0200[diff] [blame]18CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-minnie.dtb"
Simon Glasse51b2e72016-11-13 14:24:54 -0700[diff] [blame]19# CONFIG_DISPLAY_CPUINFO is not set
Mario Sixf7055442018-03-28 14:38:17 +0200[diff] [blame]20CONFIG_DISPLAY_BOARDINFO_LATE=y
Simon Glasse51b2e72016-11-13 14:24:54 -0700[diff] [blame]21CONFIG_SPL_STACK_R=y
22CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
Marek Vasute2542252018-04-07 16:05:27 +0200[diff] [blame]23CONFIG_SPL_SPI_LOAD=y
Tom Rini78873cd2017-08-14 19:58:53 -0400[diff] [blame]24CONFIG_CMD_GPIO=y
Patrick Delaunay73287092017-01-27 11:00:42 +0100[diff] [blame]25CONFIG_CMD_GPT=y
Tom Rini78873cd2017-08-14 19:58:53 -0400[diff] [blame]26CONFIG_CMD_I2C=y
Simon Glasse51b2e72016-11-13 14:24:54 -0700[diff] [blame]27CONFIG_CMD_MMC=y
28CONFIG_CMD_SF=y
Simon Glass86b1b652017-08-04 16:34:46 -0600[diff] [blame]29CONFIG_CMD_SF_TEST=y
Tom Rini78873cd2017-08-14 19:58:53 -0400[diff] [blame]30CONFIG_CMD_SPI=y
Eddie Caib3501fe2017-12-15 08:17:13 +0800[diff] [blame]31CONFIG_CMD_USB=y
Simon Glasse51b2e72016-11-13 14:24:54 -0700[diff] [blame]32# CONFIG_CMD_SETEXPR is not set
Simon Glasse51b2e72016-11-13 14:24:54 -0700[diff] [blame]33CONFIG_CMD_CACHE=y
34CONFIG_CMD_TIME=y
35CONFIG_CMD_PMIC=y
36CONFIG_CMD_REGULATOR=y
Patrick Delaunayf7e07722017-01-27 11:00:37 +0100[diff] [blame]37# CONFIG_SPL_DOS_PARTITION is not set
Patrick Delaunay8a4f2bd2017-01-27 11:00:41 +0100[diff] [blame]38# CONFIG_SPL_EFI_PARTITION is not set
Patrick Delaunay73287092017-01-27 11:00:42 +0100[diff] [blame]39CONFIG_SPL_PARTITION_UUIDS=y
Simon Glasse51b2e72016-11-13 14:24:54 -0700[diff] [blame]40CONFIG_SPL_OF_CONTROL=y
41CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
Masahiro Yamada74f09b82016-12-07 22:10:25 +0900[diff] [blame]42CONFIG_SPL_OF_PLATDATA=y
Simon Glasse51b2e72016-11-13 14:24:54 -0700[diff] [blame]43CONFIG_REGMAP=y
44CONFIG_SPL_REGMAP=y
45CONFIG_SYSCON=y
46CONFIG_SPL_SYSCON=y
47# CONFIG_SPL_SIMPLE_BUS is not set
48CONFIG_CLK=y
49CONFIG_SPL_CLK=y
Alex Kiernane80d2942018-05-29 15:30:55 +0000[diff] [blame]50CONFIG_FASTBOOT_FLASH=y
51CONFIG_FASTBOOT_FLASH_MMC_DEV=0
52CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
Simon Glasse51b2e72016-11-13 14:24:54 -0700[diff] [blame]53CONFIG_ROCKCHIP_GPIO=y
54CONFIG_I2C_CROS_EC_TUNNEL=y
55CONFIG_SYS_I2C_ROCKCHIP=y
56CONFIG_I2C_MUX=y
57CONFIG_DM_KEYBOARD=y
58CONFIG_CROS_EC_KEYB=y
59CONFIG_CROS_EC=y
60CONFIG_CROS_EC_SPI=y
61CONFIG_PWRSEQ=y
Masahiro Yamada7942e912017-01-10 13:32:04 +0900[diff] [blame]62CONFIG_MMC_DW=y
Masahiro Yamadadc607f82017-01-10 13:32:03 +0900[diff] [blame]63CONFIG_MMC_DW_ROCKCHIP=y
Simon Glasse51b2e72016-11-13 14:24:54 -0700[diff] [blame]64CONFIG_PINCTRL=y
65CONFIG_SPL_PINCTRL=y
66# CONFIG_SPL_PINCTRL_FULL is not set
Philipp Tomsicha1dcf3c2017-04-19 16:46:37 +0200[diff] [blame]67CONFIG_PINCTRL_ROCKCHIP_RK3288=y
Simon Glasse51b2e72016-11-13 14:24:54 -0700[diff] [blame]68CONFIG_DM_PMIC=y
69# CONFIG_SPL_PMIC_CHILDREN is not set
Jacob Chen614704b2017-05-02 14:54:52 +0800[diff] [blame]70CONFIG_PMIC_RK8XX=y
Simon Glasse51b2e72016-11-13 14:24:54 -0700[diff] [blame]71CONFIG_DM_REGULATOR_FIXED=y
Jacob Chen614704b2017-05-02 14:54:52 +0800[diff] [blame]72CONFIG_REGULATOR_RK8XX=y
Simon Glasse51b2e72016-11-13 14:24:54 -0700[diff] [blame]73CONFIG_PWM_ROCKCHIP=y
74CONFIG_RAM=y
75CONFIG_SPL_RAM=y
Simon Glasse51b2e72016-11-13 14:24:54 -0700[diff] [blame]76CONFIG_DEBUG_UART_SHIFT=2
Simon Glasse51b2e72016-11-13 14:24:54 -0700[diff] [blame]77CONFIG_ROCKCHIP_SERIAL=y
78CONFIG_ROCKCHIP_SPI=y
79CONFIG_SYSRESET=y
Tom Rini504997e2017-08-25 17:50:26 -0400[diff] [blame]80CONFIG_USB=y
Adam Fordd4183d62018-01-02 10:39:52 -0600[diff] [blame]81CONFIG_ROCKCHIP_USB2_PHY=y
Tom Rini6c3798f2018-02-10 20:27:45 -0500[diff] [blame]82CONFIG_USB_STORAGE=y
Tom Rini504997e2017-08-25 17:50:26 -0400[diff] [blame]83CONFIG_USB_GADGET=y
Maxime Ripard7f78b9d2017-09-07 08:58:08 +0200[diff] [blame]84CONFIG_USB_GADGET_MANUFACTURER="Rockchip"
85CONFIG_USB_GADGET_VENDOR_NUM=0x2207
86CONFIG_USB_GADGET_PRODUCT_NUM=0x320a
Tom Rini504997e2017-08-25 17:50:26 -0400[diff] [blame]87CONFIG_USB_GADGET_DWC2_OTG=y
Lukasz Majewskie364e4b2018-01-29 19:25:54 +0100[diff] [blame]88CONFIG_USB_FUNCTION_MASS_STORAGE=y
Simon Glasse51b2e72016-11-13 14:24:54 -0700[diff] [blame]89CONFIG_DM_VIDEO=y
90CONFIG_DISPLAY=y
91CONFIG_VIDEO_ROCKCHIP=y
eric.gao@rock-chips.com735ddea2017-04-17 22:24:23 +0800[diff] [blame]92CONFIG_DISPLAY_ROCKCHIP_EDP=y
Tom Rini256aa742017-06-19 09:47:40 -0400[diff] [blame]93CONFIG_DISPLAY_ROCKCHIP_HDMI=y
Simon Glasse51b2e72016-11-13 14:24:54 -0700[diff] [blame]94CONFIG_CONSOLE_SCROLL_LINES=10
95CONFIG_USE_TINY_PRINTF=y
96CONFIG_CMD_DHRYSTONE=y
97CONFIG_ERRNO_STR=y
Simon Glasse51b2e72016-11-13 14:24:54 -0700[diff] [blame]98# CONFIG_SPL_OF_LIBFDT is not set