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git01.mediatek.com / filogic / uboot / 504997e7253969358b7a35b0c6fa6e3c7b9999eb / . / configs / chromebook_minnie_defconfig
blob: b281618298ccf6c2c8aa81f90c73a215356f2b6c [file] [log] [blame]
Simon Glasse51b2e72016-11-13 14:24:54 -0700[diff] [blame]1CONFIG_ARM=y
2CONFIG_ARCH_ROCKCHIP=y
3CONFIG_SYS_MALLOC_F_LEN=0x2000
Simon Glasse51b2e72016-11-13 14:24:54 -0700[diff] [blame]4CONFIG_ROCKCHIP_RK3288=y
Tom Rini9834b902017-03-13 13:48:42 -0400[diff] [blame]5# CONFIG_SPL_MMC_SUPPORT is not set
Simon Glasse51b2e72016-11-13 14:24:54 -0700[diff] [blame]6CONFIG_TARGET_CHROMEBOOK_MINNIE=y
7CONFIG_SPL_SPI_FLASH_SUPPORT=y
8CONFIG_SPL_SPI_SUPPORT=y
9CONFIG_SPL_STACK_R_ADDR=0x80000
10CONFIG_DEFAULT_DEVICE_TREE="rk3288-veyron-minnie"
Tom Rini256aa742017-06-19 09:47:40 -0400[diff] [blame]11CONFIG_DEBUG_UART=y
Simon Glasse51b2e72016-11-13 14:24:54 -0700[diff] [blame]12CONFIG_SILENT_CONSOLE=y
13# CONFIG_DISPLAY_CPUINFO is not set
14CONFIG_SPL_STACK_R=y
15CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000
Simon Glasse51b2e72016-11-13 14:24:54 -0700[diff] [blame]16# CONFIG_CMD_IMLS is not set
Tom Rini78873cd2017-08-14 19:58:53 -0400[diff] [blame]17CONFIG_CMD_GPIO=y
Patrick Delaunay73287092017-01-27 11:00:42 +0100[diff] [blame]18CONFIG_CMD_GPT=y
Tom Rini78873cd2017-08-14 19:58:53 -0400[diff] [blame]19CONFIG_CMD_I2C=y
Simon Glasse51b2e72016-11-13 14:24:54 -0700[diff] [blame]20CONFIG_CMD_MMC=y
21CONFIG_CMD_SF=y
Simon Glass86b1b652017-08-04 16:34:46 -0600[diff] [blame]22CONFIG_CMD_SF_TEST=y
Tom Rini78873cd2017-08-14 19:58:53 -0400[diff] [blame]23CONFIG_CMD_SPI=y
Simon Glasse51b2e72016-11-13 14:24:54 -0700[diff] [blame]24# CONFIG_CMD_SETEXPR is not set
Simon Glasse51b2e72016-11-13 14:24:54 -0700[diff] [blame]25CONFIG_CMD_CACHE=y
26CONFIG_CMD_TIME=y
27CONFIG_CMD_PMIC=y
28CONFIG_CMD_REGULATOR=y
Patrick Delaunayf7e07722017-01-27 11:00:37 +0100[diff] [blame]29# CONFIG_SPL_DOS_PARTITION is not set
Patrick Delaunay21d3bce2017-01-27 11:00:38 +0100[diff] [blame]30# CONFIG_SPL_ISO_PARTITION is not set
Patrick Delaunay8a4f2bd2017-01-27 11:00:41 +0100[diff] [blame]31# CONFIG_SPL_EFI_PARTITION is not set
Patrick Delaunay73287092017-01-27 11:00:42 +0100[diff] [blame]32CONFIG_SPL_PARTITION_UUIDS=y
Simon Glasse51b2e72016-11-13 14:24:54 -0700[diff] [blame]33CONFIG_SPL_OF_CONTROL=y
34CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents"
Masahiro Yamada74f09b82016-12-07 22:10:25 +0900[diff] [blame]35CONFIG_SPL_OF_PLATDATA=y
Simon Glasse51b2e72016-11-13 14:24:54 -0700[diff] [blame]36CONFIG_REGMAP=y
37CONFIG_SPL_REGMAP=y
38CONFIG_SYSCON=y
39CONFIG_SPL_SYSCON=y
40# CONFIG_SPL_SIMPLE_BUS is not set
41CONFIG_CLK=y
42CONFIG_SPL_CLK=y
43CONFIG_ROCKCHIP_GPIO=y
44CONFIG_I2C_CROS_EC_TUNNEL=y
45CONFIG_SYS_I2C_ROCKCHIP=y
46CONFIG_I2C_MUX=y
47CONFIG_DM_KEYBOARD=y
48CONFIG_CROS_EC_KEYB=y
49CONFIG_CROS_EC=y
50CONFIG_CROS_EC_SPI=y
51CONFIG_PWRSEQ=y
Masahiro Yamada7942e912017-01-10 13:32:04 +0900[diff] [blame]52CONFIG_MMC_DW=y
Masahiro Yamadadc607f82017-01-10 13:32:03 +0900[diff] [blame]53CONFIG_MMC_DW_ROCKCHIP=y
Simon Glasse51b2e72016-11-13 14:24:54 -0700[diff] [blame]54CONFIG_PINCTRL=y
55CONFIG_SPL_PINCTRL=y
56# CONFIG_SPL_PINCTRL_FULL is not set
Philipp Tomsicha1dcf3c2017-04-19 16:46:37 +0200[diff] [blame]57CONFIG_PINCTRL_ROCKCHIP_RK3288=y
Simon Glasse51b2e72016-11-13 14:24:54 -0700[diff] [blame]58CONFIG_DM_PMIC=y
59# CONFIG_SPL_PMIC_CHILDREN is not set
Jacob Chen614704b2017-05-02 14:54:52 +0800[diff] [blame]60CONFIG_PMIC_RK8XX=y
Simon Glasse51b2e72016-11-13 14:24:54 -0700[diff] [blame]61CONFIG_DM_REGULATOR_FIXED=y
Jacob Chen614704b2017-05-02 14:54:52 +0800[diff] [blame]62CONFIG_REGULATOR_RK8XX=y
Simon Glasse51b2e72016-11-13 14:24:54 -0700[diff] [blame]63CONFIG_PWM_ROCKCHIP=y
64CONFIG_RAM=y
65CONFIG_SPL_RAM=y
Simon Glasse51b2e72016-11-13 14:24:54 -0700[diff] [blame]66CONFIG_DEBUG_UART_BASE=0xff690000
67CONFIG_DEBUG_UART_CLOCK=24000000
68CONFIG_DEBUG_UART_SHIFT=2
69CONFIG_SYS_NS16550=y
70CONFIG_ROCKCHIP_SERIAL=y
71CONFIG_ROCKCHIP_SPI=y
72CONFIG_SYSRESET=y
Tom Rini504997e2017-08-25 17:50:26 -0400[diff] [blame^]73CONFIG_USB=y
74CONFIG_USB_GADGET=y
75CONFIG_USB_GADGET_DWC2_OTG=y
76CONFIG_USB_GADGET_DOWNLOAD=y
77CONFIG_G_DNL_MANUFACTURER="Rockchip"
78CONFIG_G_DNL_VENDOR_NUM=0x2207
79CONFIG_G_DNL_PRODUCT_NUM=0x320a
Simon Glasse51b2e72016-11-13 14:24:54 -0700[diff] [blame]80CONFIG_DM_VIDEO=y
81CONFIG_DISPLAY=y
82CONFIG_VIDEO_ROCKCHIP=y
eric.gao@rock-chips.com735ddea2017-04-17 22:24:23 +0800[diff] [blame]83CONFIG_DISPLAY_ROCKCHIP_EDP=y
Tom Rini256aa742017-06-19 09:47:40 -0400[diff] [blame]84CONFIG_DISPLAY_ROCKCHIP_HDMI=y
Simon Glasse51b2e72016-11-13 14:24:54 -0700[diff] [blame]85CONFIG_CONSOLE_SCROLL_LINES=10
86CONFIG_USE_TINY_PRINTF=y
87CONFIG_CMD_DHRYSTONE=y
88CONFIG_ERRNO_STR=y
Simon Glasse51b2e72016-11-13 14:24:54 -0700[diff] [blame]89# CONFIG_SPL_OF_LIBFDT is not set