blob: 58493a825982b471c65e5413b29ffcfe66566b8d [file] [log] [blame]
Stefan Bosch5ed5ad42020-07-10 19:07:36 +02001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2016 Nexell Co., Ltd.
4 *
5 * Author: junghyun, kim <jhkim@nexell.co.kr>
6 */
7
8#include <config.h>
Stefan Bosch5ed5ad42020-07-10 19:07:36 +02009#include <errno.h>
10
11#include <asm/arch/nexell.h>
12#include <asm/arch/tieoff.h>
13#include <asm/arch/reset.h>
14#include <asm/arch/display.h>
15
16#include "soc/s5pxx18_soc_mipi.h"
17#include "soc/s5pxx18_soc_disptop.h"
18#include "soc/s5pxx18_soc_disptop_clk.h"
19
20#define PLLPMS_1000MHZ 0x33E8
21#define BANDCTL_1000MHZ 0xF
22#define PLLPMS_960MHZ 0x2280
23#define BANDCTL_960MHZ 0xF
24#define PLLPMS_900MHZ 0x2258
25#define BANDCTL_900MHZ 0xE
26#define PLLPMS_840MHZ 0x2230
27#define BANDCTL_840MHZ 0xD
28#define PLLPMS_750MHZ 0x43E8
29#define BANDCTL_750MHZ 0xC
30#define PLLPMS_660MHZ 0x21B8
31#define BANDCTL_660MHZ 0xB
32#define PLLPMS_600MHZ 0x2190
33#define BANDCTL_600MHZ 0xA
34#define PLLPMS_540MHZ 0x2168
35#define BANDCTL_540MHZ 0x9
36#define PLLPMS_512MHZ 0x03200
37#define BANDCTL_512MHZ 0x9
38#define PLLPMS_480MHZ 0x2281
39#define BANDCTL_480MHZ 0x8
40#define PLLPMS_420MHZ 0x2231
41#define BANDCTL_420MHZ 0x7
42#define PLLPMS_402MHZ 0x2219
43#define BANDCTL_402MHZ 0x7
44#define PLLPMS_330MHZ 0x21B9
45#define BANDCTL_330MHZ 0x6
46#define PLLPMS_300MHZ 0x2191
47#define BANDCTL_300MHZ 0x5
48#define PLLPMS_210MHZ 0x2232
49#define BANDCTL_210MHZ 0x4
50#define PLLPMS_180MHZ 0x21E2
51#define BANDCTL_180MHZ 0x3
52#define PLLPMS_150MHZ 0x2192
53#define BANDCTL_150MHZ 0x2
54#define PLLPMS_100MHZ 0x3323
55#define BANDCTL_100MHZ 0x1
56#define PLLPMS_80MHZ 0x3283
57#define BANDCTL_80MHZ 0x0
58
59#define MIPI_INDEX 0
60#define MIPI_EXC_PRE_VALUE 1
61#define MIPI_DSI_IRQ_MASK 29
62
63#define __io_address(a) (void *)(uintptr_t)(a)
64
65struct mipi_xfer_msg {
66 u8 id, data[2];
67 u16 flags;
68 const u8 *tx_buf;
69 u16 tx_len;
70 u8 *rx_buf;
71 u16 rx_len;
72};
73
74static void mipi_reset(void)
75{
76 /* tieoff */
77 nx_tieoff_set(NX_TIEOFF_MIPI0_NX_DPSRAM_1R1W_EMAA, 3);
78 nx_tieoff_set(NX_TIEOFF_MIPI0_NX_DPSRAM_1R1W_EMAB, 3);
79
80 /* reset */
81 nx_rstcon_setrst(RESET_ID_MIPI, RSTCON_ASSERT);
82 nx_rstcon_setrst(RESET_ID_MIPI_DSI, RSTCON_ASSERT);
83 nx_rstcon_setrst(RESET_ID_MIPI_CSI, RSTCON_ASSERT);
84 nx_rstcon_setrst(RESET_ID_MIPI_PHY_S, RSTCON_ASSERT);
85 nx_rstcon_setrst(RESET_ID_MIPI_PHY_M, RSTCON_ASSERT);
86
87 nx_rstcon_setrst(RESET_ID_MIPI, RSTCON_NEGATE);
88 nx_rstcon_setrst(RESET_ID_MIPI_DSI, RSTCON_NEGATE);
89 nx_rstcon_setrst(RESET_ID_MIPI_PHY_S, RSTCON_NEGATE);
90 nx_rstcon_setrst(RESET_ID_MIPI_PHY_M, RSTCON_NEGATE);
91}
92
93static void mipi_init(void)
94{
95 int clkid = DP_CLOCK_MIPI;
96 void *base;
97
98 /*
99 * neet to reset before open
100 */
101 mipi_reset();
102
103 base = __io_address(nx_disp_top_clkgen_get_physical_address(clkid));
104 nx_disp_top_clkgen_set_base_address(clkid, base);
105 nx_disp_top_clkgen_set_clock_pclk_mode(clkid, nx_pclkmode_always);
106
107 base = __io_address(nx_mipi_get_physical_address(0));
108 nx_mipi_set_base_address(0, base);
109}
110
111static int mipi_get_phy_pll(int bitrate, unsigned int *pllpms,
112 unsigned int *bandctl)
113{
114 unsigned int pms, ctl;
115
116 switch (bitrate) {
117 case 1000:
118 pms = PLLPMS_1000MHZ;
119 ctl = BANDCTL_1000MHZ;
120 break;
121 case 960:
122 pms = PLLPMS_960MHZ;
123 ctl = BANDCTL_960MHZ;
124 break;
125 case 900:
126 pms = PLLPMS_900MHZ;
127 ctl = BANDCTL_900MHZ;
128 break;
129 case 840:
130 pms = PLLPMS_840MHZ;
131 ctl = BANDCTL_840MHZ;
132 break;
133 case 750:
134 pms = PLLPMS_750MHZ;
135 ctl = BANDCTL_750MHZ;
136 break;
137 case 660:
138 pms = PLLPMS_660MHZ;
139 ctl = BANDCTL_660MHZ;
140 break;
141 case 600:
142 pms = PLLPMS_600MHZ;
143 ctl = BANDCTL_600MHZ;
144 break;
145 case 540:
146 pms = PLLPMS_540MHZ;
147 ctl = BANDCTL_540MHZ;
148 break;
149 case 512:
150 pms = PLLPMS_512MHZ;
151 ctl = BANDCTL_512MHZ;
152 break;
153 case 480:
154 pms = PLLPMS_480MHZ;
155 ctl = BANDCTL_480MHZ;
156 break;
157 case 420:
158 pms = PLLPMS_420MHZ;
159 ctl = BANDCTL_420MHZ;
160 break;
161 case 402:
162 pms = PLLPMS_402MHZ;
163 ctl = BANDCTL_402MHZ;
164 break;
165 case 330:
166 pms = PLLPMS_330MHZ;
167 ctl = BANDCTL_330MHZ;
168 break;
169 case 300:
170 pms = PLLPMS_300MHZ;
171 ctl = BANDCTL_300MHZ;
172 break;
173 case 210:
174 pms = PLLPMS_210MHZ;
175 ctl = BANDCTL_210MHZ;
176 break;
177 case 180:
178 pms = PLLPMS_180MHZ;
179 ctl = BANDCTL_180MHZ;
180 break;
181 case 150:
182 pms = PLLPMS_150MHZ;
183 ctl = BANDCTL_150MHZ;
184 break;
185 case 100:
186 pms = PLLPMS_100MHZ;
187 ctl = BANDCTL_100MHZ;
188 break;
189 case 80:
190 pms = PLLPMS_80MHZ;
191 ctl = BANDCTL_80MHZ;
192 break;
193 default:
194 return -EINVAL;
195 }
196
197 *pllpms = pms;
198 *bandctl = ctl;
199
200 return 0;
201}
202
203static int mipi_prepare(int module, int input,
204 struct dp_sync_info *sync, struct dp_ctrl_info *ctrl,
205 struct dp_mipi_dev *mipi)
206{
207 int index = MIPI_INDEX;
208 u32 esc_pre_value = MIPI_EXC_PRE_VALUE;
209 int lpm = mipi->lpm_trans;
210 int ret = 0;
211
212 ret = mipi_get_phy_pll(mipi->hs_bitrate,
213 &mipi->hs_pllpms, &mipi->hs_bandctl);
214 if (ret < 0)
215 return ret;
216
217 ret = mipi_get_phy_pll(mipi->lp_bitrate,
218 &mipi->lp_pllpms, &mipi->lp_bandctl);
219 if (ret < 0)
220 return ret;
221
222 debug("%s: mipi lp:%dmhz:0x%x:0x%x, hs:%dmhz:0x%x:0x%x, %s trans\n",
223 __func__, mipi->lp_bitrate, mipi->lp_pllpms, mipi->lp_bandctl,
224 mipi->hs_bitrate, mipi->hs_pllpms, mipi->hs_bandctl,
225 lpm ? "low" : "high");
226
227 if (lpm)
228 nx_mipi_dsi_set_pll(index, 1, 0xFFFFFFFF,
229 mipi->lp_pllpms, mipi->lp_bandctl, 0, 0);
230 else
231 nx_mipi_dsi_set_pll(index, 1, 0xFFFFFFFF,
232 mipi->hs_pllpms, mipi->hs_bandctl, 0, 0);
233
234#ifdef CONFIG_ARCH_S5P4418
235 /*
236 * disable the escape clock generating prescaler
237 * before soft reset.
238 */
239 nx_mipi_dsi_set_clock(index, 0, 0, 1, 1, 1, 0, 0, 0, 0, 10);
240 mdelay(1);
241#endif
242
243 nx_mipi_dsi_software_reset(index);
244 nx_mipi_dsi_set_clock(index, 0, 0, 1, 1, 1, 0, 0, 0, 1, esc_pre_value);
245 nx_mipi_dsi_set_phy(index, 0, 1, 1, 0, 0, 0, 0, 0);
246
247 if (lpm)
248 nx_mipi_dsi_set_escape_lp(index, nx_mipi_dsi_lpmode_lp,
249 nx_mipi_dsi_lpmode_lp);
250 else
251 nx_mipi_dsi_set_escape_lp(index, nx_mipi_dsi_lpmode_hs,
252 nx_mipi_dsi_lpmode_hs);
253 mdelay(20);
254
255 return 0;
256}
257
258static int mipi_enable(int module, int input,
259 struct dp_sync_info *sync, struct dp_ctrl_info *ctrl,
260 struct dp_mipi_dev *mipi)
261{
262 struct mipi_dsi_device *dsi = &mipi->dsi;
263 int clkid = DP_CLOCK_MIPI;
264 int index = MIPI_INDEX;
265 int width = sync->h_active_len;
266 int height = sync->v_active_len;
267 int HFP = sync->h_front_porch;
268 int HBP = sync->h_back_porch;
269 int HS = sync->h_sync_width;
270 int VFP = sync->v_front_porch;
271 int VBP = sync->v_back_porch;
272 int VS = sync->v_sync_width;
273 int en_prescaler = 1;
274 u32 esc_pre_value = MIPI_EXC_PRE_VALUE;
275
276 int txhsclock = 1;
277 int lpm = mipi->lpm_trans;
278 bool command_mode = mipi->command_mode;
279
280 enum nx_mipi_dsi_format dsi_format;
281 int data_len = dsi->lanes - 1;
282 bool burst = dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST ? true : false;
283 bool eot_enable = dsi->mode_flags & MIPI_DSI_MODE_EOT_PACKET ?
284 false : true;
285
286 /*
287 * disable the escape clock generating prescaler
288 * before soft reset.
289 */
290#ifdef CONFIG_ARCH_S5P4418
291 en_prescaler = 0;
292#endif
293
294 debug("%s: mode:%s, lanes.%d\n", __func__,
295 command_mode ? "command" : "video", data_len + 1);
296
297 if (lpm)
298 nx_mipi_dsi_set_escape_lp(index,
299 nx_mipi_dsi_lpmode_hs,
300 nx_mipi_dsi_lpmode_hs);
301
302 nx_mipi_dsi_set_pll(index, 1, 0xFFFFFFFF,
303 mipi->hs_pllpms, mipi->hs_bandctl, 0, 0);
304 mdelay(1);
305
306 nx_mipi_dsi_set_clock(index, 0, 0, 1, 1, 1, 0, 0, 0, en_prescaler, 10);
307 mdelay(1);
308
309 nx_mipi_dsi_software_reset(index);
310 nx_mipi_dsi_set_clock(index, txhsclock, 0, 1,
311 1, 1, 0, 0, 0, 1, esc_pre_value);
312
313 switch (data_len) {
314 case 0: /* 1 lane */
315 nx_mipi_dsi_set_phy(index, data_len, 1, 1, 0, 0, 0, 0, 0);
316 break;
317 case 1: /* 2 lane */
318 nx_mipi_dsi_set_phy(index, data_len, 1, 1, 1, 0, 0, 0, 0);
319 break;
320 case 2: /* 3 lane */
321 nx_mipi_dsi_set_phy(index, data_len, 1, 1, 1, 1, 0, 0, 0);
322 break;
323 case 3: /* 3 lane */
324 nx_mipi_dsi_set_phy(index, data_len, 1, 1, 1, 1, 1, 0, 0);
325 break;
326 default:
327 printf("%s: not support data lanes %d\n",
328 __func__, data_len + 1);
329 return -EINVAL;
330 }
331
332 switch (dsi->format) {
333 case MIPI_DSI_FMT_RGB565:
334 dsi_format = nx_mipi_dsi_format_rgb565;
335 break;
336 case MIPI_DSI_FMT_RGB666:
337 dsi_format = nx_mipi_dsi_format_rgb666;
338 break;
339 case MIPI_DSI_FMT_RGB666_PACKED:
340 dsi_format = nx_mipi_dsi_format_rgb666_packed;
341 break;
342 case MIPI_DSI_FMT_RGB888:
343 dsi_format = nx_mipi_dsi_format_rgb888;
344 break;
345 default:
346 printf("%s: not support format %d\n", __func__, dsi->format);
347 return -EINVAL;
348 }
349
350 nx_mipi_dsi_set_config_video_mode(index, 1, 0, burst,
351 nx_mipi_dsi_syncmode_event,
352 eot_enable, 1, 1, 1, 1, 0, dsi_format,
353 HFP, HBP, HS, VFP, VBP, VS, 0);
354
355 nx_mipi_dsi_set_size(index, width, height);
356
357 /* set mux */
358 nx_disp_top_set_mipimux(1, module);
359
360 /* 0 is spdif, 1 is mipi vclk */
361 nx_disp_top_clkgen_set_clock_source(clkid, 1, ctrl->clk_src_lv0);
362 nx_disp_top_clkgen_set_clock_divisor(clkid, 1,
363 ctrl->clk_div_lv1 *
364 ctrl->clk_div_lv0);
365
366 /* SPDIF and MIPI */
367 nx_disp_top_clkgen_set_clock_divisor_enable(clkid, 1);
368
369 /* START: CLKGEN, MIPI is started in setup function */
370 nx_disp_top_clkgen_set_clock_divisor_enable(clkid, true);
371 nx_mipi_dsi_set_enable(index, true);
372
373 return 0;
374}
375
376static int nx_mipi_transfer_tx(struct mipi_dsi_device *dsi,
377 struct mipi_xfer_msg *xfer)
378{
379 const u8 *txb;
380 int size, index = 0;
381 u32 data;
382
383 if (xfer->tx_len > DSI_TX_FIFO_SIZE)
384 printf("warn: tx %d size over fifo %d\n",
385 (int)xfer->tx_len, DSI_TX_FIFO_SIZE);
386
387 /* write payload */
388 size = xfer->tx_len;
389 txb = xfer->tx_buf;
390
391 while (size >= 4) {
392 data = (txb[3] << 24) | (txb[2] << 16) |
393 (txb[1] << 8) | (txb[0]);
394 nx_mipi_dsi_write_payload(index, data);
395 txb += 4, size -= 4;
396 data = 0;
397 }
398
399 switch (size) {
400 case 3:
401 data |= txb[2] << 16;
402 case 2:
403 data |= txb[1] << 8;
404 case 1:
405 data |= txb[0];
406 nx_mipi_dsi_write_payload(index, data);
407 break;
408 case 0:
409 break; /* no payload */
410 }
411
412 /* write packet hdr */
413 data = (xfer->data[1] << 16) | (xfer->data[0] << 8) | xfer->id;
414
415 nx_mipi_dsi_write_pkheader(index, data);
416
417 return 0;
418}
419
420static int nx_mipi_transfer_done(struct mipi_dsi_device *dsi)
421{
422 int index = 0, count = 100;
423 u32 value;
424
425 do {
426 mdelay(1);
427 value = nx_mipi_dsi_read_fifo_status(index);
428 if (((1 << 22) & value))
429 break;
430 } while (count-- > 0);
431
432 if (count < 0)
433 return -EINVAL;
434
435 return 0;
436}
437
438static int nx_mipi_transfer_rx(struct mipi_dsi_device *dsi,
439 struct mipi_xfer_msg *xfer)
440{
441 u8 *rxb = xfer->rx_buf;
442 int index = 0, rx_len = 0;
443 u32 data, count = 0;
444 u16 size;
445 int err = -EINVAL;
446
447 nx_mipi_dsi_clear_interrupt_pending(index, 18);
448
449 while (1) {
450 /* Completes receiving data. */
451 if (nx_mipi_dsi_get_interrupt_pending(index, 18))
452 break;
453
454 mdelay(1);
455
456 if (count > 500) {
457 printf("%s: error recevice data\n", __func__);
458 err = -EINVAL;
459 goto clear_fifo;
460 } else {
461 count++;
462 }
463 }
464
465 data = nx_mipi_dsi_read_fifo(index);
466
467 switch (data & 0x3f) {
468 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE:
469 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
470 if (xfer->rx_len >= 2) {
471 rxb[1] = data >> 16;
472 rx_len++;
473 }
474
475 /* Fall through */
476 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE:
477 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
478 rxb[0] = data >> 8;
479 rx_len++;
480 xfer->rx_len = rx_len;
481 err = rx_len;
482 goto clear_fifo;
483
484 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
485 printf("DSI Error Report: 0x%04x\n", (data >> 8) & 0xffff);
486 err = rx_len;
487 goto clear_fifo;
488 }
489
490 size = (data >> 8) & 0xffff;
491
492 if (size > xfer->rx_len)
493 size = xfer->rx_len;
494 else if (size < xfer->rx_len)
495 xfer->rx_len = size;
496
497 size = xfer->rx_len - rx_len;
498 rx_len += size;
499
500 /* Receive payload */
501 while (size >= 4) {
502 data = nx_mipi_dsi_read_fifo(index);
503 rxb[0] = (data >> 0) & 0xff;
504 rxb[1] = (data >> 8) & 0xff;
505 rxb[2] = (data >> 16) & 0xff;
506 rxb[3] = (data >> 24) & 0xff;
507 rxb += 4, size -= 4;
508 }
509
510 if (size) {
511 data = nx_mipi_dsi_read_fifo(index);
512 switch (size) {
513 case 3:
514 rxb[2] = (data >> 16) & 0xff;
515 case 2:
516 rxb[1] = (data >> 8) & 0xff;
517 case 1:
518 rxb[0] = data & 0xff;
519 }
520 }
521
522 if (rx_len == xfer->rx_len)
523 err = rx_len;
524
525clear_fifo:
526 size = DSI_RX_FIFO_SIZE / 4;
527 do {
528 data = nx_mipi_dsi_read_fifo(index);
529 if (data == DSI_RX_FIFO_EMPTY)
530 break;
531 } while (--size);
532
533 return err;
534}
535
536#define IS_SHORT(t) (9 > ((t) & 0x0f))
537
538static int nx_mipi_transfer(struct mipi_dsi_device *dsi,
539 const struct mipi_dsi_msg *msg)
540{
541 struct mipi_xfer_msg xfer;
542 int err;
543
544 if (!msg->tx_len)
545 return -EINVAL;
546
547 /* set id */
548 xfer.id = msg->type | (msg->channel << 6);
549
550 /* short type msg */
551 if (IS_SHORT(msg->type)) {
552 const char *txb = msg->tx_buf;
553
554 if (msg->tx_len > 2)
555 return -EINVAL;
556
557 xfer.tx_len = 0; /* no payload */
558 xfer.data[0] = txb[0];
559 xfer.data[1] = (msg->tx_len == 2) ? txb[1] : 0;
560 xfer.tx_buf = NULL;
561 } else {
562 xfer.tx_len = msg->tx_len;
563 xfer.data[0] = msg->tx_len & 0xff;
564 xfer.data[1] = msg->tx_len >> 8;
565 xfer.tx_buf = msg->tx_buf;
566 }
567
568 xfer.rx_len = msg->rx_len;
569 xfer.rx_buf = msg->rx_buf;
570 xfer.flags = msg->flags;
571
572 err = nx_mipi_transfer_tx(dsi, &xfer);
573
574 if (xfer.rx_len)
575 err = nx_mipi_transfer_rx(dsi, &xfer);
576
577 nx_mipi_transfer_done(dsi);
578
579 return err;
580}
581
582static ssize_t nx_mipi_write_buffer(struct mipi_dsi_device *dsi,
583 const void *data, size_t len)
584{
585 struct mipi_dsi_msg msg = {
586 .channel = dsi->channel,
587 .tx_buf = data,
588 .tx_len = len
589 };
590
591 switch (len) {
592 case 0:
593 return -EINVAL;
594 case 1:
595 msg.type = MIPI_DSI_DCS_SHORT_WRITE;
596 break;
597 case 2:
598 msg.type = MIPI_DSI_DCS_SHORT_WRITE_PARAM;
599 break;
600 default:
601 msg.type = MIPI_DSI_DCS_LONG_WRITE;
602 break;
603 }
604
605 if (dsi->mode_flags & MIPI_DSI_MODE_LPM)
606 msg.flags |= MIPI_DSI_MSG_USE_LPM;
607
608 return nx_mipi_transfer(dsi, &msg);
609}
610
611__weak int nx_mipi_dsi_lcd_bind(struct mipi_dsi_device *dsi)
612{
613 return 0;
614}
615
616/*
617 * disply
618 * MIPI DSI Setting
619 * (1) Initiallize MIPI(DSIM,DPHY,PLL)
620 * (2) Initiallize LCD
621 * (3) ReInitiallize MIPI(DSIM only)
622 * (4) Turn on display(MLC,DPC,...)
623 */
624void nx_mipi_display(int module,
625 struct dp_sync_info *sync, struct dp_ctrl_info *ctrl,
626 struct dp_plane_top *top, struct dp_plane_info *planes,
627 struct dp_mipi_dev *dev)
628{
629 struct dp_plane_info *plane = planes;
630 struct mipi_dsi_device *dsi = &dev->dsi;
631 int input = module == 0 ? DP_DEVICE_DP0 : DP_DEVICE_DP1;
632 int count = top->plane_num;
633 int i = 0, ret;
634
635 printf("MIPI: dp.%d\n", module);
636
637 /* map mipi-dsi write callback func */
638 dsi->write_buffer = nx_mipi_write_buffer;
639
640 ret = nx_mipi_dsi_lcd_bind(dsi);
641 if (ret) {
642 printf("Error: bind mipi-dsi lcd driver !\n");
643 return;
644 }
645
646 dp_control_init(module);
647 dp_plane_init(module);
648
649 mipi_init();
650
651 /* set plane */
652 dp_plane_screen_setup(module, top);
653
654 for (i = 0; count > i; i++, plane++) {
655 if (!plane->enable)
656 continue;
657 dp_plane_layer_setup(module, plane);
658 dp_plane_layer_enable(module, plane, 1);
659 }
660 dp_plane_screen_enable(module, 1);
661
662 /* set mipi */
663 mipi_prepare(module, input, sync, ctrl, dev);
664
665 if (dsi->ops && dsi->ops->prepare)
666 dsi->ops->prepare(dsi);
667
668 if (dsi->ops && dsi->ops->enable)
669 dsi->ops->enable(dsi);
670
671 mipi_enable(module, input, sync, ctrl, dev);
672
673 /* set dp control */
674 dp_control_setup(module, sync, ctrl);
675 dp_control_enable(module, 1);
676}