Stefan Mavrodiev | 5d71604 | 2018-02-06 15:14:33 +0200 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2017 Whitebox Systems / Northend Systems B.V. |
| 3 | * S.J.R. van Schaik <stephan@whiteboxsystems.nl> |
| 4 | * M.B.W. Wajer <merlijn@whiteboxsystems.nl> |
| 5 | * |
| 6 | * (C) Copyright 2017 Olimex Ltd.. |
| 7 | * Stefan Mavrodiev <stefan@olimex.com> |
| 8 | * |
| 9 | * Based on linux spi driver. Original copyright follows: |
| 10 | * linux/drivers/spi/spi-sun4i.c |
| 11 | * |
| 12 | * Copyright (C) 2012 - 2014 Allwinner Tech |
| 13 | * Pan Nan <pannan@allwinnertech.com> |
| 14 | * |
| 15 | * Copyright (C) 2014 Maxime Ripard |
| 16 | * Maxime Ripard <maxime.ripard@free-electrons.com> |
| 17 | * |
| 18 | * SPDX-License-Identifier: GPL-2.0+ |
| 19 | */ |
| 20 | |
Jagan Teki | 97b3d5a | 2019-02-27 20:02:10 +0530 | [diff] [blame] | 21 | #include <clk.h> |
Stefan Mavrodiev | 5d71604 | 2018-02-06 15:14:33 +0200 | [diff] [blame] | 22 | #include <dm.h> |
Simon Glass | 0f2af88 | 2020-05-10 11:40:05 -0600 | [diff] [blame] | 23 | #include <log.h> |
Stefan Mavrodiev | 5d71604 | 2018-02-06 15:14:33 +0200 | [diff] [blame] | 24 | #include <spi.h> |
| 25 | #include <errno.h> |
| 26 | #include <fdt_support.h> |
Jagan Teki | f69b425 | 2019-02-27 20:02:11 +0530 | [diff] [blame] | 27 | #include <reset.h> |
Stefan Mavrodiev | 5d71604 | 2018-02-06 15:14:33 +0200 | [diff] [blame] | 28 | #include <wait_bit.h> |
Simon Glass | 3ba929a | 2020-10-30 21:38:53 -0600 | [diff] [blame] | 29 | #include <asm/global_data.h> |
Simon Glass | 9bc1564 | 2020-02-03 07:36:16 -0700 | [diff] [blame] | 30 | #include <dm/device_compat.h> |
Simon Glass | 4dcacfc | 2020-05-10 11:40:13 -0600 | [diff] [blame] | 31 | #include <linux/bitops.h> |
Stefan Mavrodiev | 5d71604 | 2018-02-06 15:14:33 +0200 | [diff] [blame] | 32 | |
| 33 | #include <asm/bitops.h> |
Stefan Mavrodiev | 5d71604 | 2018-02-06 15:14:33 +0200 | [diff] [blame] | 34 | #include <asm/io.h> |
| 35 | |
Jagan Teki | 66220da | 2019-02-27 20:02:05 +0530 | [diff] [blame] | 36 | #include <linux/iopoll.h> |
| 37 | |
Jagan Teki | 3f53a58 | 2019-02-27 20:02:12 +0530 | [diff] [blame] | 38 | DECLARE_GLOBAL_DATA_PTR; |
Stefan Mavrodiev | 5d71604 | 2018-02-06 15:14:33 +0200 | [diff] [blame] | 39 | |
Jagan Teki | 3f53a58 | 2019-02-27 20:02:12 +0530 | [diff] [blame] | 40 | /* sun4i spi registers */ |
| 41 | #define SUN4I_RXDATA_REG 0x00 |
| 42 | #define SUN4I_TXDATA_REG 0x04 |
| 43 | #define SUN4I_CTL_REG 0x08 |
| 44 | #define SUN4I_CLK_CTL_REG 0x1c |
| 45 | #define SUN4I_BURST_CNT_REG 0x20 |
| 46 | #define SUN4I_XMIT_CNT_REG 0x24 |
| 47 | #define SUN4I_FIFO_STA_REG 0x28 |
Stefan Mavrodiev | 5d71604 | 2018-02-06 15:14:33 +0200 | [diff] [blame] | 48 | |
Jagan Teki | f69b425 | 2019-02-27 20:02:11 +0530 | [diff] [blame] | 49 | /* sun6i spi registers */ |
| 50 | #define SUN6I_GBL_CTL_REG 0x04 |
| 51 | #define SUN6I_TFR_CTL_REG 0x08 |
| 52 | #define SUN6I_FIFO_CTL_REG 0x18 |
| 53 | #define SUN6I_FIFO_STA_REG 0x1c |
| 54 | #define SUN6I_CLK_CTL_REG 0x24 |
| 55 | #define SUN6I_BURST_CNT_REG 0x30 |
| 56 | #define SUN6I_XMIT_CNT_REG 0x34 |
| 57 | #define SUN6I_BURST_CTL_REG 0x38 |
| 58 | #define SUN6I_TXDATA_REG 0x200 |
| 59 | #define SUN6I_RXDATA_REG 0x300 |
| 60 | |
Jagan Teki | 3f53a58 | 2019-02-27 20:02:12 +0530 | [diff] [blame] | 61 | /* sun spi bits */ |
| 62 | #define SUN4I_CTL_ENABLE BIT(0) |
| 63 | #define SUN4I_CTL_MASTER BIT(1) |
| 64 | #define SUN4I_CLK_CTL_CDR2_MASK 0xff |
| 65 | #define SUN4I_CLK_CTL_CDR2(div) ((div) & SUN4I_CLK_CTL_CDR2_MASK) |
| 66 | #define SUN4I_CLK_CTL_CDR1_MASK 0xf |
| 67 | #define SUN4I_CLK_CTL_CDR1(div) (((div) & SUN4I_CLK_CTL_CDR1_MASK) << 8) |
| 68 | #define SUN4I_CLK_CTL_DRS BIT(12) |
| 69 | #define SUN4I_MAX_XFER_SIZE 0xffffff |
| 70 | #define SUN4I_BURST_CNT(cnt) ((cnt) & SUN4I_MAX_XFER_SIZE) |
| 71 | #define SUN4I_XMIT_CNT(cnt) ((cnt) & SUN4I_MAX_XFER_SIZE) |
| 72 | #define SUN4I_FIFO_STA_RF_CNT_BITS 0 |
| 73 | |
Andre Przywara | 4d3521ce | 2022-04-26 23:58:53 +0100 | [diff] [blame] | 74 | #ifdef CONFIG_MACH_SUNIV |
| 75 | /* the AHB clock, which we programmed to be 1/3 of PLL_PERIPH@600MHz */ |
| 76 | #define SUNXI_INPUT_CLOCK 200000000 /* 200 MHz */ |
| 77 | #define SUN4I_SPI_MAX_RATE (SUNXI_INPUT_CLOCK / 2) |
| 78 | #else |
Andre Przywara | 2783568 | 2022-05-03 02:06:37 +0100 | [diff] [blame] | 79 | /* the SPI mod clock, defaulting to be 1/1 of the HOSC@24MHz */ |
| 80 | #define SUNXI_INPUT_CLOCK 24000000 /* 24 MHz */ |
| 81 | #define SUN4I_SPI_MAX_RATE SUNXI_INPUT_CLOCK |
Andre Przywara | 4d3521ce | 2022-04-26 23:58:53 +0100 | [diff] [blame] | 82 | #endif |
Jagan Teki | 3f53a58 | 2019-02-27 20:02:12 +0530 | [diff] [blame] | 83 | #define SUN4I_SPI_MIN_RATE 3000 |
| 84 | #define SUN4I_SPI_DEFAULT_RATE 1000000 |
Icenowy Zheng | a244be6 | 2022-06-28 14:49:24 +0800 | [diff] [blame] | 85 | #define SUN4I_SPI_TIMEOUT_MS 1000 |
Stefan Mavrodiev | 5d71604 | 2018-02-06 15:14:33 +0200 | [diff] [blame] | 86 | |
Jagan Teki | 3f53a58 | 2019-02-27 20:02:12 +0530 | [diff] [blame] | 87 | #define SPI_REG(priv, reg) ((priv)->base + \ |
Jagan Teki | c25058c | 2019-02-27 20:02:08 +0530 | [diff] [blame] | 88 | (priv)->variant->regs[reg]) |
| 89 | #define SPI_BIT(priv, bit) ((priv)->variant->bits[bit]) |
| 90 | #define SPI_CS(priv, cs) (((cs) << SPI_BIT(priv, SPI_TCR_CS_SEL)) & \ |
| 91 | SPI_BIT(priv, SPI_TCR_CS_MASK)) |
| 92 | |
| 93 | /* sun spi register set */ |
| 94 | enum sun4i_spi_regs { |
| 95 | SPI_GCR, |
| 96 | SPI_TCR, |
| 97 | SPI_FCR, |
| 98 | SPI_FSR, |
| 99 | SPI_CCR, |
| 100 | SPI_BC, |
| 101 | SPI_TC, |
| 102 | SPI_BCTL, |
| 103 | SPI_TXD, |
| 104 | SPI_RXD, |
| 105 | }; |
| 106 | |
| 107 | /* sun spi register bits */ |
| 108 | enum sun4i_spi_bits { |
| 109 | SPI_GCR_TP, |
Jagan Teki | f69b425 | 2019-02-27 20:02:11 +0530 | [diff] [blame] | 110 | SPI_GCR_SRST, |
Jagan Teki | c25058c | 2019-02-27 20:02:08 +0530 | [diff] [blame] | 111 | SPI_TCR_CPHA, |
| 112 | SPI_TCR_CPOL, |
| 113 | SPI_TCR_CS_ACTIVE_LOW, |
| 114 | SPI_TCR_CS_SEL, |
| 115 | SPI_TCR_CS_MASK, |
| 116 | SPI_TCR_XCH, |
| 117 | SPI_TCR_CS_MANUAL, |
| 118 | SPI_TCR_CS_LEVEL, |
Maksim Kiselev | 4d9267e | 2023-11-11 16:33:08 +0300 | [diff] [blame] | 119 | SPI_TCR_SDC, |
| 120 | SPI_TCR_SDM, |
Jagan Teki | c25058c | 2019-02-27 20:02:08 +0530 | [diff] [blame] | 121 | SPI_FCR_TF_RST, |
| 122 | SPI_FCR_RF_RST, |
| 123 | SPI_FSR_RF_CNT_MASK, |
Stefan Mavrodiev | 5d71604 | 2018-02-06 15:14:33 +0200 | [diff] [blame] | 124 | }; |
| 125 | |
Jagan Teki | c25058c | 2019-02-27 20:02:08 +0530 | [diff] [blame] | 126 | struct sun4i_spi_variant { |
| 127 | const unsigned long *regs; |
| 128 | const u32 *bits; |
Jagan Teki | c12eb6a | 2019-02-27 20:02:09 +0530 | [diff] [blame] | 129 | u32 fifo_depth; |
Jagan Teki | f69b425 | 2019-02-27 20:02:11 +0530 | [diff] [blame] | 130 | bool has_soft_reset; |
| 131 | bool has_burst_ctl; |
Maksim Kiselev | 4d9267e | 2023-11-11 16:33:08 +0300 | [diff] [blame] | 132 | bool has_clk_ctl; |
Jagan Teki | c25058c | 2019-02-27 20:02:08 +0530 | [diff] [blame] | 133 | }; |
| 134 | |
Simon Glass | b75b15b | 2020-12-03 16:55:23 -0700 | [diff] [blame] | 135 | struct sun4i_spi_plat { |
Jagan Teki | c25058c | 2019-02-27 20:02:08 +0530 | [diff] [blame] | 136 | struct sun4i_spi_variant *variant; |
Jagan Teki | 3f53a58 | 2019-02-27 20:02:12 +0530 | [diff] [blame] | 137 | u32 base; |
Stefan Mavrodiev | 5d71604 | 2018-02-06 15:14:33 +0200 | [diff] [blame] | 138 | u32 max_hz; |
| 139 | }; |
| 140 | |
| 141 | struct sun4i_spi_priv { |
Jagan Teki | c25058c | 2019-02-27 20:02:08 +0530 | [diff] [blame] | 142 | struct sun4i_spi_variant *variant; |
Jagan Teki | 97b3d5a | 2019-02-27 20:02:10 +0530 | [diff] [blame] | 143 | struct clk clk_ahb, clk_mod; |
Jagan Teki | f69b425 | 2019-02-27 20:02:11 +0530 | [diff] [blame] | 144 | struct reset_ctl reset; |
Jagan Teki | 3f53a58 | 2019-02-27 20:02:12 +0530 | [diff] [blame] | 145 | u32 base; |
Stefan Mavrodiev | 5d71604 | 2018-02-06 15:14:33 +0200 | [diff] [blame] | 146 | u32 freq; |
| 147 | u32 mode; |
| 148 | |
| 149 | const u8 *tx_buf; |
| 150 | u8 *rx_buf; |
| 151 | }; |
| 152 | |
Stefan Mavrodiev | 5d71604 | 2018-02-06 15:14:33 +0200 | [diff] [blame] | 153 | static inline void sun4i_spi_drain_fifo(struct sun4i_spi_priv *priv, int len) |
| 154 | { |
| 155 | u8 byte; |
| 156 | |
| 157 | while (len--) { |
Jagan Teki | c25058c | 2019-02-27 20:02:08 +0530 | [diff] [blame] | 158 | byte = readb(SPI_REG(priv, SPI_RXD)); |
Stefan Mavrodiev | 165db62 | 2018-12-05 14:27:57 +0200 | [diff] [blame] | 159 | if (priv->rx_buf) |
| 160 | *priv->rx_buf++ = byte; |
Stefan Mavrodiev | 5d71604 | 2018-02-06 15:14:33 +0200 | [diff] [blame] | 161 | } |
| 162 | } |
| 163 | |
| 164 | static inline void sun4i_spi_fill_fifo(struct sun4i_spi_priv *priv, int len) |
| 165 | { |
| 166 | u8 byte; |
| 167 | |
| 168 | while (len--) { |
| 169 | byte = priv->tx_buf ? *priv->tx_buf++ : 0; |
Jagan Teki | c25058c | 2019-02-27 20:02:08 +0530 | [diff] [blame] | 170 | writeb(byte, SPI_REG(priv, SPI_TXD)); |
Stefan Mavrodiev | 5d71604 | 2018-02-06 15:14:33 +0200 | [diff] [blame] | 171 | } |
| 172 | } |
| 173 | |
| 174 | static void sun4i_spi_set_cs(struct udevice *bus, u8 cs, bool enable) |
| 175 | { |
| 176 | struct sun4i_spi_priv *priv = dev_get_priv(bus); |
| 177 | u32 reg; |
| 178 | |
Jagan Teki | c25058c | 2019-02-27 20:02:08 +0530 | [diff] [blame] | 179 | reg = readl(SPI_REG(priv, SPI_TCR)); |
Stefan Mavrodiev | 5d71604 | 2018-02-06 15:14:33 +0200 | [diff] [blame] | 180 | |
Jagan Teki | c25058c | 2019-02-27 20:02:08 +0530 | [diff] [blame] | 181 | reg &= ~SPI_BIT(priv, SPI_TCR_CS_MASK); |
| 182 | reg |= SPI_CS(priv, cs); |
Stefan Mavrodiev | 5d71604 | 2018-02-06 15:14:33 +0200 | [diff] [blame] | 183 | |
| 184 | if (enable) |
Jagan Teki | c25058c | 2019-02-27 20:02:08 +0530 | [diff] [blame] | 185 | reg &= ~SPI_BIT(priv, SPI_TCR_CS_LEVEL); |
Stefan Mavrodiev | 5d71604 | 2018-02-06 15:14:33 +0200 | [diff] [blame] | 186 | else |
Jagan Teki | c25058c | 2019-02-27 20:02:08 +0530 | [diff] [blame] | 187 | reg |= SPI_BIT(priv, SPI_TCR_CS_LEVEL); |
Stefan Mavrodiev | 5d71604 | 2018-02-06 15:14:33 +0200 | [diff] [blame] | 188 | |
Jagan Teki | c25058c | 2019-02-27 20:02:08 +0530 | [diff] [blame] | 189 | writel(reg, SPI_REG(priv, SPI_TCR)); |
Stefan Mavrodiev | 5d71604 | 2018-02-06 15:14:33 +0200 | [diff] [blame] | 190 | } |
| 191 | |
Jagan Teki | 97b3d5a | 2019-02-27 20:02:10 +0530 | [diff] [blame] | 192 | static inline int sun4i_spi_set_clock(struct udevice *dev, bool enable) |
Stefan Mavrodiev | 5d71604 | 2018-02-06 15:14:33 +0200 | [diff] [blame] | 193 | { |
Jagan Teki | 97b3d5a | 2019-02-27 20:02:10 +0530 | [diff] [blame] | 194 | struct sun4i_spi_priv *priv = dev_get_priv(dev); |
| 195 | int ret; |
| 196 | |
| 197 | if (!enable) { |
| 198 | clk_disable(&priv->clk_ahb); |
| 199 | clk_disable(&priv->clk_mod); |
Jagan Teki | f69b425 | 2019-02-27 20:02:11 +0530 | [diff] [blame] | 200 | if (reset_valid(&priv->reset)) |
| 201 | reset_assert(&priv->reset); |
Jagan Teki | 97b3d5a | 2019-02-27 20:02:10 +0530 | [diff] [blame] | 202 | return 0; |
| 203 | } |
| 204 | |
| 205 | ret = clk_enable(&priv->clk_ahb); |
| 206 | if (ret) { |
| 207 | dev_err(dev, "failed to enable ahb clock (ret=%d)\n", ret); |
| 208 | return ret; |
| 209 | } |
| 210 | |
| 211 | ret = clk_enable(&priv->clk_mod); |
| 212 | if (ret) { |
| 213 | dev_err(dev, "failed to enable mod clock (ret=%d)\n", ret); |
| 214 | goto err_ahb; |
| 215 | } |
Stefan Mavrodiev | 5d71604 | 2018-02-06 15:14:33 +0200 | [diff] [blame] | 216 | |
Jagan Teki | f69b425 | 2019-02-27 20:02:11 +0530 | [diff] [blame] | 217 | if (reset_valid(&priv->reset)) { |
| 218 | ret = reset_deassert(&priv->reset); |
| 219 | if (ret) { |
| 220 | dev_err(dev, "failed to deassert reset\n"); |
| 221 | goto err_mod; |
| 222 | } |
| 223 | } |
| 224 | |
Jagan Teki | 97b3d5a | 2019-02-27 20:02:10 +0530 | [diff] [blame] | 225 | return 0; |
| 226 | |
Jagan Teki | f69b425 | 2019-02-27 20:02:11 +0530 | [diff] [blame] | 227 | err_mod: |
| 228 | clk_disable(&priv->clk_mod); |
Jagan Teki | 97b3d5a | 2019-02-27 20:02:10 +0530 | [diff] [blame] | 229 | err_ahb: |
| 230 | clk_disable(&priv->clk_ahb); |
| 231 | return ret; |
Stefan Mavrodiev | 5d71604 | 2018-02-06 15:14:33 +0200 | [diff] [blame] | 232 | } |
| 233 | |
Andre Przywara | 62a24e1 | 2022-05-03 00:07:16 +0100 | [diff] [blame] | 234 | static void sun4i_spi_set_speed_mode(struct udevice *dev) |
| 235 | { |
| 236 | struct sun4i_spi_priv *priv = dev_get_priv(dev); |
| 237 | unsigned int div; |
| 238 | u32 reg; |
| 239 | |
| 240 | /* |
| 241 | * Setup clock divider. |
| 242 | * |
| 243 | * We have two choices there. Either we can use the clock |
| 244 | * divide rate 1, which is calculated thanks to this formula: |
| 245 | * SPI_CLK = MOD_CLK / (2 ^ (cdr + 1)) |
| 246 | * Or we can use CDR2, which is calculated with the formula: |
| 247 | * SPI_CLK = MOD_CLK / (2 * (cdr + 1)) |
| 248 | * Whether we use the former or the latter is set through the |
| 249 | * DRS bit. |
| 250 | * |
| 251 | * First try CDR2, and if we can't reach the expected |
| 252 | * frequency, fall back to CDR1. |
| 253 | */ |
| 254 | |
Andre Przywara | 2783568 | 2022-05-03 02:06:37 +0100 | [diff] [blame] | 255 | div = DIV_ROUND_UP(SUNXI_INPUT_CLOCK, priv->freq); |
Andre Przywara | 62a24e1 | 2022-05-03 00:07:16 +0100 | [diff] [blame] | 256 | reg = readl(SPI_REG(priv, SPI_CCR)); |
| 257 | |
Andre Przywara | 2783568 | 2022-05-03 02:06:37 +0100 | [diff] [blame] | 258 | if ((div / 2) <= (SUN4I_CLK_CTL_CDR2_MASK + 1)) { |
| 259 | div /= 2; |
Andre Przywara | 62a24e1 | 2022-05-03 00:07:16 +0100 | [diff] [blame] | 260 | if (div > 0) |
| 261 | div--; |
| 262 | |
| 263 | reg &= ~(SUN4I_CLK_CTL_CDR2_MASK | SUN4I_CLK_CTL_DRS); |
| 264 | reg |= SUN4I_CLK_CTL_CDR2(div) | SUN4I_CLK_CTL_DRS; |
| 265 | } else { |
Andre Przywara | 2783568 | 2022-05-03 02:06:37 +0100 | [diff] [blame] | 266 | div = fls(div - 1); |
Andre Przywara | 4d3521ce | 2022-04-26 23:58:53 +0100 | [diff] [blame] | 267 | /* The F1C100s encodes the divider as 2^(n+1) */ |
| 268 | if (IS_ENABLED(CONFIG_MACH_SUNIV)) |
| 269 | div--; |
Andre Przywara | 62a24e1 | 2022-05-03 00:07:16 +0100 | [diff] [blame] | 270 | reg &= ~((SUN4I_CLK_CTL_CDR1_MASK << 8) | SUN4I_CLK_CTL_DRS); |
| 271 | reg |= SUN4I_CLK_CTL_CDR1(div); |
| 272 | } |
| 273 | |
| 274 | writel(reg, SPI_REG(priv, SPI_CCR)); |
| 275 | |
| 276 | reg = readl(SPI_REG(priv, SPI_TCR)); |
| 277 | reg &= ~(SPI_BIT(priv, SPI_TCR_CPOL) | SPI_BIT(priv, SPI_TCR_CPHA)); |
| 278 | |
| 279 | if (priv->mode & SPI_CPOL) |
| 280 | reg |= SPI_BIT(priv, SPI_TCR_CPOL); |
| 281 | |
| 282 | if (priv->mode & SPI_CPHA) |
| 283 | reg |= SPI_BIT(priv, SPI_TCR_CPHA); |
| 284 | |
| 285 | writel(reg, SPI_REG(priv, SPI_TCR)); |
| 286 | } |
| 287 | |
Stefan Mavrodiev | 5d71604 | 2018-02-06 15:14:33 +0200 | [diff] [blame] | 288 | static int sun4i_spi_claim_bus(struct udevice *dev) |
| 289 | { |
| 290 | struct sun4i_spi_priv *priv = dev_get_priv(dev->parent); |
Jagan Teki | 97b3d5a | 2019-02-27 20:02:10 +0530 | [diff] [blame] | 291 | int ret; |
| 292 | |
| 293 | ret = sun4i_spi_set_clock(dev->parent, true); |
| 294 | if (ret) |
| 295 | return ret; |
Stefan Mavrodiev | 5d71604 | 2018-02-06 15:14:33 +0200 | [diff] [blame] | 296 | |
Jagan Teki | c25058c | 2019-02-27 20:02:08 +0530 | [diff] [blame] | 297 | setbits_le32(SPI_REG(priv, SPI_GCR), SUN4I_CTL_ENABLE | |
| 298 | SUN4I_CTL_MASTER | SPI_BIT(priv, SPI_GCR_TP)); |
| 299 | |
Jagan Teki | f69b425 | 2019-02-27 20:02:11 +0530 | [diff] [blame] | 300 | if (priv->variant->has_soft_reset) |
| 301 | setbits_le32(SPI_REG(priv, SPI_GCR), |
| 302 | SPI_BIT(priv, SPI_GCR_SRST)); |
| 303 | |
Jagan Teki | c25058c | 2019-02-27 20:02:08 +0530 | [diff] [blame] | 304 | setbits_le32(SPI_REG(priv, SPI_TCR), SPI_BIT(priv, SPI_TCR_CS_MANUAL) | |
| 305 | SPI_BIT(priv, SPI_TCR_CS_ACTIVE_LOW)); |
Jagan Teki | f9b7012 | 2019-02-27 20:02:07 +0530 | [diff] [blame] | 306 | |
Maksim Kiselev | 4d9267e | 2023-11-11 16:33:08 +0300 | [diff] [blame] | 307 | if (priv->variant->has_clk_ctl) { |
| 308 | sun4i_spi_set_speed_mode(dev->parent); |
| 309 | } else { |
| 310 | /* |
| 311 | * At this moment there is no ability to change input clock. |
| 312 | * Therefore, we can only use default HOSC@24MHz clock and |
| 313 | * set SPI sampling mode to normal |
| 314 | */ |
| 315 | clrsetbits_le32(SPI_REG(priv, SPI_TCR), |
| 316 | SPI_BIT(priv, SPI_TCR_SDC) | |
| 317 | SPI_BIT(priv, SPI_TCR_SDM), |
| 318 | SPI_BIT(priv, SPI_TCR_SDM)); |
| 319 | } |
Andre Przywara | 62a24e1 | 2022-05-03 00:07:16 +0100 | [diff] [blame] | 320 | |
Stefan Mavrodiev | 5d71604 | 2018-02-06 15:14:33 +0200 | [diff] [blame] | 321 | return 0; |
| 322 | } |
| 323 | |
| 324 | static int sun4i_spi_release_bus(struct udevice *dev) |
| 325 | { |
| 326 | struct sun4i_spi_priv *priv = dev_get_priv(dev->parent); |
Stefan Mavrodiev | 5d71604 | 2018-02-06 15:14:33 +0200 | [diff] [blame] | 327 | |
Jagan Teki | c25058c | 2019-02-27 20:02:08 +0530 | [diff] [blame] | 328 | clrbits_le32(SPI_REG(priv, SPI_GCR), SUN4I_CTL_ENABLE); |
Stefan Mavrodiev | 5d71604 | 2018-02-06 15:14:33 +0200 | [diff] [blame] | 329 | |
Jagan Teki | 97b3d5a | 2019-02-27 20:02:10 +0530 | [diff] [blame] | 330 | sun4i_spi_set_clock(dev->parent, false); |
| 331 | |
Stefan Mavrodiev | 5d71604 | 2018-02-06 15:14:33 +0200 | [diff] [blame] | 332 | return 0; |
| 333 | } |
| 334 | |
| 335 | static int sun4i_spi_xfer(struct udevice *dev, unsigned int bitlen, |
| 336 | const void *dout, void *din, unsigned long flags) |
| 337 | { |
| 338 | struct udevice *bus = dev->parent; |
| 339 | struct sun4i_spi_priv *priv = dev_get_priv(bus); |
Simon Glass | b75b15b | 2020-12-03 16:55:23 -0700 | [diff] [blame] | 340 | struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev); |
Stefan Mavrodiev | 5d71604 | 2018-02-06 15:14:33 +0200 | [diff] [blame] | 341 | |
| 342 | u32 len = bitlen / 8; |
Stefan Mavrodiev | 5d71604 | 2018-02-06 15:14:33 +0200 | [diff] [blame] | 343 | u8 nbytes; |
| 344 | int ret; |
| 345 | |
| 346 | priv->tx_buf = dout; |
| 347 | priv->rx_buf = din; |
| 348 | |
| 349 | if (bitlen % 8) { |
| 350 | debug("%s: non byte-aligned SPI transfer.\n", __func__); |
| 351 | return -ENAVAIL; |
| 352 | } |
| 353 | |
| 354 | if (flags & SPI_XFER_BEGIN) |
| 355 | sun4i_spi_set_cs(bus, slave_plat->cs, true); |
| 356 | |
Stefan Mavrodiev | 5d71604 | 2018-02-06 15:14:33 +0200 | [diff] [blame] | 357 | /* Reset FIFOs */ |
Jagan Teki | c25058c | 2019-02-27 20:02:08 +0530 | [diff] [blame] | 358 | setbits_le32(SPI_REG(priv, SPI_FCR), SPI_BIT(priv, SPI_FCR_RF_RST) | |
| 359 | SPI_BIT(priv, SPI_FCR_TF_RST)); |
Stefan Mavrodiev | 5d71604 | 2018-02-06 15:14:33 +0200 | [diff] [blame] | 360 | |
| 361 | while (len) { |
| 362 | /* Setup the transfer now... */ |
Jagan Teki | c12eb6a | 2019-02-27 20:02:09 +0530 | [diff] [blame] | 363 | nbytes = min(len, (priv->variant->fifo_depth - 1)); |
Stefan Mavrodiev | 5d71604 | 2018-02-06 15:14:33 +0200 | [diff] [blame] | 364 | |
| 365 | /* Setup the counters */ |
Jagan Teki | c25058c | 2019-02-27 20:02:08 +0530 | [diff] [blame] | 366 | writel(SUN4I_BURST_CNT(nbytes), SPI_REG(priv, SPI_BC)); |
| 367 | writel(SUN4I_XMIT_CNT(nbytes), SPI_REG(priv, SPI_TC)); |
Stefan Mavrodiev | 5d71604 | 2018-02-06 15:14:33 +0200 | [diff] [blame] | 368 | |
Jagan Teki | f69b425 | 2019-02-27 20:02:11 +0530 | [diff] [blame] | 369 | if (priv->variant->has_burst_ctl) |
| 370 | writel(SUN4I_BURST_CNT(nbytes), |
| 371 | SPI_REG(priv, SPI_BCTL)); |
| 372 | |
Stefan Mavrodiev | 5d71604 | 2018-02-06 15:14:33 +0200 | [diff] [blame] | 373 | /* Fill the TX FIFO */ |
| 374 | sun4i_spi_fill_fifo(priv, nbytes); |
| 375 | |
| 376 | /* Start the transfer */ |
Jagan Teki | c25058c | 2019-02-27 20:02:08 +0530 | [diff] [blame] | 377 | setbits_le32(SPI_REG(priv, SPI_TCR), |
| 378 | SPI_BIT(priv, SPI_TCR_XCH)); |
Stefan Mavrodiev | 5d71604 | 2018-02-06 15:14:33 +0200 | [diff] [blame] | 379 | |
Icenowy Zheng | a244be6 | 2022-06-28 14:49:24 +0800 | [diff] [blame] | 380 | /* Wait for the transfer to be done */ |
| 381 | ret = wait_for_bit_le32((const void *)SPI_REG(priv, SPI_TCR), |
| 382 | SPI_BIT(priv, SPI_TCR_XCH), |
| 383 | false, SUN4I_SPI_TIMEOUT_MS, false); |
Jagan Teki | 66220da | 2019-02-27 20:02:05 +0530 | [diff] [blame] | 384 | if (ret < 0) { |
Stefan Mavrodiev | 5d71604 | 2018-02-06 15:14:33 +0200 | [diff] [blame] | 385 | printf("ERROR: sun4i_spi: Timeout transferring data\n"); |
| 386 | sun4i_spi_set_cs(bus, slave_plat->cs, false); |
| 387 | return ret; |
| 388 | } |
| 389 | |
| 390 | /* Drain the RX FIFO */ |
| 391 | sun4i_spi_drain_fifo(priv, nbytes); |
| 392 | |
| 393 | len -= nbytes; |
| 394 | } |
| 395 | |
| 396 | if (flags & SPI_XFER_END) |
| 397 | sun4i_spi_set_cs(bus, slave_plat->cs, false); |
| 398 | |
| 399 | return 0; |
| 400 | } |
| 401 | |
| 402 | static int sun4i_spi_set_speed(struct udevice *dev, uint speed) |
| 403 | { |
Simon Glass | b75b15b | 2020-12-03 16:55:23 -0700 | [diff] [blame] | 404 | struct sun4i_spi_plat *plat = dev_get_plat(dev); |
Stefan Mavrodiev | 5d71604 | 2018-02-06 15:14:33 +0200 | [diff] [blame] | 405 | struct sun4i_spi_priv *priv = dev_get_priv(dev); |
Stefan Mavrodiev | 5d71604 | 2018-02-06 15:14:33 +0200 | [diff] [blame] | 406 | |
| 407 | if (speed > plat->max_hz) |
| 408 | speed = plat->max_hz; |
| 409 | |
| 410 | if (speed < SUN4I_SPI_MIN_RATE) |
| 411 | speed = SUN4I_SPI_MIN_RATE; |
Stefan Mavrodiev | 5d71604 | 2018-02-06 15:14:33 +0200 | [diff] [blame] | 412 | |
| 413 | priv->freq = speed; |
Stefan Mavrodiev | 5d71604 | 2018-02-06 15:14:33 +0200 | [diff] [blame] | 414 | |
| 415 | return 0; |
| 416 | } |
| 417 | |
| 418 | static int sun4i_spi_set_mode(struct udevice *dev, uint mode) |
| 419 | { |
| 420 | struct sun4i_spi_priv *priv = dev_get_priv(dev); |
Stefan Mavrodiev | 5d71604 | 2018-02-06 15:14:33 +0200 | [diff] [blame] | 421 | |
| 422 | priv->mode = mode; |
Stefan Mavrodiev | 5d71604 | 2018-02-06 15:14:33 +0200 | [diff] [blame] | 423 | |
| 424 | return 0; |
| 425 | } |
| 426 | |
| 427 | static const struct dm_spi_ops sun4i_spi_ops = { |
| 428 | .claim_bus = sun4i_spi_claim_bus, |
| 429 | .release_bus = sun4i_spi_release_bus, |
| 430 | .xfer = sun4i_spi_xfer, |
| 431 | .set_speed = sun4i_spi_set_speed, |
| 432 | .set_mode = sun4i_spi_set_mode, |
| 433 | }; |
| 434 | |
Jagan Teki | 3f53a58 | 2019-02-27 20:02:12 +0530 | [diff] [blame] | 435 | static int sun4i_spi_probe(struct udevice *bus) |
| 436 | { |
Simon Glass | b75b15b | 2020-12-03 16:55:23 -0700 | [diff] [blame] | 437 | struct sun4i_spi_plat *plat = dev_get_plat(bus); |
Jagan Teki | 3f53a58 | 2019-02-27 20:02:12 +0530 | [diff] [blame] | 438 | struct sun4i_spi_priv *priv = dev_get_priv(bus); |
| 439 | int ret; |
| 440 | |
| 441 | ret = clk_get_by_name(bus, "ahb", &priv->clk_ahb); |
| 442 | if (ret) { |
Sean Anderson | 64474dd | 2020-09-15 10:45:11 -0400 | [diff] [blame] | 443 | dev_err(bus, "failed to get ahb clock\n"); |
Jagan Teki | 3f53a58 | 2019-02-27 20:02:12 +0530 | [diff] [blame] | 444 | return ret; |
| 445 | } |
| 446 | |
| 447 | ret = clk_get_by_name(bus, "mod", &priv->clk_mod); |
| 448 | if (ret) { |
Sean Anderson | 64474dd | 2020-09-15 10:45:11 -0400 | [diff] [blame] | 449 | dev_err(bus, "failed to get mod clock\n"); |
Jagan Teki | 3f53a58 | 2019-02-27 20:02:12 +0530 | [diff] [blame] | 450 | return ret; |
| 451 | } |
| 452 | |
| 453 | ret = reset_get_by_index(bus, 0, &priv->reset); |
| 454 | if (ret && ret != -ENOENT) { |
Sean Anderson | 64474dd | 2020-09-15 10:45:11 -0400 | [diff] [blame] | 455 | dev_err(bus, "failed to get reset\n"); |
Jagan Teki | 3f53a58 | 2019-02-27 20:02:12 +0530 | [diff] [blame] | 456 | return ret; |
| 457 | } |
| 458 | |
Jagan Teki | 3f53a58 | 2019-02-27 20:02:12 +0530 | [diff] [blame] | 459 | priv->variant = plat->variant; |
| 460 | priv->base = plat->base; |
| 461 | priv->freq = plat->max_hz; |
| 462 | |
| 463 | return 0; |
| 464 | } |
| 465 | |
Simon Glass | aad29ae | 2020-12-03 16:55:21 -0700 | [diff] [blame] | 466 | static int sun4i_spi_of_to_plat(struct udevice *bus) |
Jagan Teki | 3f53a58 | 2019-02-27 20:02:12 +0530 | [diff] [blame] | 467 | { |
Simon Glass | b75b15b | 2020-12-03 16:55:23 -0700 | [diff] [blame] | 468 | struct sun4i_spi_plat *plat = dev_get_plat(bus); |
Jagan Teki | 3f53a58 | 2019-02-27 20:02:12 +0530 | [diff] [blame] | 469 | int node = dev_of_offset(bus); |
| 470 | |
Masahiro Yamada | a89b4de | 2020-07-17 14:36:48 +0900 | [diff] [blame] | 471 | plat->base = dev_read_addr(bus); |
Jagan Teki | 3f53a58 | 2019-02-27 20:02:12 +0530 | [diff] [blame] | 472 | plat->variant = (struct sun4i_spi_variant *)dev_get_driver_data(bus); |
| 473 | plat->max_hz = fdtdec_get_int(gd->fdt_blob, node, |
| 474 | "spi-max-frequency", |
| 475 | SUN4I_SPI_DEFAULT_RATE); |
| 476 | |
| 477 | if (plat->max_hz > SUN4I_SPI_MAX_RATE) |
| 478 | plat->max_hz = SUN4I_SPI_MAX_RATE; |
| 479 | |
| 480 | return 0; |
| 481 | } |
| 482 | |
Jagan Teki | c25058c | 2019-02-27 20:02:08 +0530 | [diff] [blame] | 483 | static const unsigned long sun4i_spi_regs[] = { |
| 484 | [SPI_GCR] = SUN4I_CTL_REG, |
| 485 | [SPI_TCR] = SUN4I_CTL_REG, |
| 486 | [SPI_FCR] = SUN4I_CTL_REG, |
| 487 | [SPI_FSR] = SUN4I_FIFO_STA_REG, |
| 488 | [SPI_CCR] = SUN4I_CLK_CTL_REG, |
| 489 | [SPI_BC] = SUN4I_BURST_CNT_REG, |
| 490 | [SPI_TC] = SUN4I_XMIT_CNT_REG, |
| 491 | [SPI_TXD] = SUN4I_TXDATA_REG, |
| 492 | [SPI_RXD] = SUN4I_RXDATA_REG, |
| 493 | }; |
| 494 | |
| 495 | static const u32 sun4i_spi_bits[] = { |
| 496 | [SPI_GCR_TP] = BIT(18), |
| 497 | [SPI_TCR_CPHA] = BIT(2), |
| 498 | [SPI_TCR_CPOL] = BIT(3), |
| 499 | [SPI_TCR_CS_ACTIVE_LOW] = BIT(4), |
| 500 | [SPI_TCR_XCH] = BIT(10), |
| 501 | [SPI_TCR_CS_SEL] = 12, |
| 502 | [SPI_TCR_CS_MASK] = 0x3000, |
| 503 | [SPI_TCR_CS_MANUAL] = BIT(16), |
| 504 | [SPI_TCR_CS_LEVEL] = BIT(17), |
| 505 | [SPI_FCR_TF_RST] = BIT(8), |
| 506 | [SPI_FCR_RF_RST] = BIT(9), |
| 507 | [SPI_FSR_RF_CNT_MASK] = GENMASK(6, 0), |
| 508 | }; |
| 509 | |
Jagan Teki | f69b425 | 2019-02-27 20:02:11 +0530 | [diff] [blame] | 510 | static const unsigned long sun6i_spi_regs[] = { |
| 511 | [SPI_GCR] = SUN6I_GBL_CTL_REG, |
| 512 | [SPI_TCR] = SUN6I_TFR_CTL_REG, |
| 513 | [SPI_FCR] = SUN6I_FIFO_CTL_REG, |
| 514 | [SPI_FSR] = SUN6I_FIFO_STA_REG, |
| 515 | [SPI_CCR] = SUN6I_CLK_CTL_REG, |
| 516 | [SPI_BC] = SUN6I_BURST_CNT_REG, |
| 517 | [SPI_TC] = SUN6I_XMIT_CNT_REG, |
| 518 | [SPI_BCTL] = SUN6I_BURST_CTL_REG, |
| 519 | [SPI_TXD] = SUN6I_TXDATA_REG, |
| 520 | [SPI_RXD] = SUN6I_RXDATA_REG, |
| 521 | }; |
| 522 | |
| 523 | static const u32 sun6i_spi_bits[] = { |
| 524 | [SPI_GCR_TP] = BIT(7), |
| 525 | [SPI_GCR_SRST] = BIT(31), |
| 526 | [SPI_TCR_CPHA] = BIT(0), |
| 527 | [SPI_TCR_CPOL] = BIT(1), |
| 528 | [SPI_TCR_CS_ACTIVE_LOW] = BIT(2), |
| 529 | [SPI_TCR_CS_SEL] = 4, |
| 530 | [SPI_TCR_CS_MASK] = 0x30, |
| 531 | [SPI_TCR_CS_MANUAL] = BIT(6), |
| 532 | [SPI_TCR_CS_LEVEL] = BIT(7), |
Maksim Kiselev | 4d9267e | 2023-11-11 16:33:08 +0300 | [diff] [blame] | 533 | [SPI_TCR_SDC] = BIT(11), |
| 534 | [SPI_TCR_SDM] = BIT(13), |
Jagan Teki | f69b425 | 2019-02-27 20:02:11 +0530 | [diff] [blame] | 535 | [SPI_TCR_XCH] = BIT(31), |
| 536 | [SPI_FCR_RF_RST] = BIT(15), |
| 537 | [SPI_FCR_TF_RST] = BIT(31), |
| 538 | [SPI_FSR_RF_CNT_MASK] = GENMASK(7, 0), |
| 539 | }; |
| 540 | |
Jagan Teki | c25058c | 2019-02-27 20:02:08 +0530 | [diff] [blame] | 541 | static const struct sun4i_spi_variant sun4i_a10_spi_variant = { |
| 542 | .regs = sun4i_spi_regs, |
| 543 | .bits = sun4i_spi_bits, |
Jagan Teki | c12eb6a | 2019-02-27 20:02:09 +0530 | [diff] [blame] | 544 | .fifo_depth = 64, |
Maksim Kiselev | 4d9267e | 2023-11-11 16:33:08 +0300 | [diff] [blame] | 545 | .has_clk_ctl = true, |
Jagan Teki | f69b425 | 2019-02-27 20:02:11 +0530 | [diff] [blame] | 546 | }; |
| 547 | |
| 548 | static const struct sun4i_spi_variant sun6i_a31_spi_variant = { |
| 549 | .regs = sun6i_spi_regs, |
| 550 | .bits = sun6i_spi_bits, |
| 551 | .fifo_depth = 128, |
| 552 | .has_soft_reset = true, |
| 553 | .has_burst_ctl = true, |
Maksim Kiselev | 4d9267e | 2023-11-11 16:33:08 +0300 | [diff] [blame] | 554 | .has_clk_ctl = true, |
Jagan Teki | f69b425 | 2019-02-27 20:02:11 +0530 | [diff] [blame] | 555 | }; |
| 556 | |
| 557 | static const struct sun4i_spi_variant sun8i_h3_spi_variant = { |
| 558 | .regs = sun6i_spi_regs, |
| 559 | .bits = sun6i_spi_bits, |
| 560 | .fifo_depth = 64, |
| 561 | .has_soft_reset = true, |
| 562 | .has_burst_ctl = true, |
Maksim Kiselev | 4d9267e | 2023-11-11 16:33:08 +0300 | [diff] [blame] | 563 | .has_clk_ctl = true, |
Jagan Teki | c25058c | 2019-02-27 20:02:08 +0530 | [diff] [blame] | 564 | }; |
| 565 | |
Maksim Kiselev | 4d9267e | 2023-11-11 16:33:08 +0300 | [diff] [blame] | 566 | static const struct sun4i_spi_variant sun50i_r329_spi_variant = { |
| 567 | .regs = sun6i_spi_regs, |
| 568 | .bits = sun6i_spi_bits, |
| 569 | .fifo_depth = 64, |
| 570 | .has_soft_reset = true, |
| 571 | .has_burst_ctl = true, |
| 572 | }; |
| 573 | |
Stefan Mavrodiev | 5d71604 | 2018-02-06 15:14:33 +0200 | [diff] [blame] | 574 | static const struct udevice_id sun4i_spi_ids[] = { |
Jagan Teki | c25058c | 2019-02-27 20:02:08 +0530 | [diff] [blame] | 575 | { |
| 576 | .compatible = "allwinner,sun4i-a10-spi", |
| 577 | .data = (ulong)&sun4i_a10_spi_variant, |
| 578 | }, |
Jagan Teki | f69b425 | 2019-02-27 20:02:11 +0530 | [diff] [blame] | 579 | { |
| 580 | .compatible = "allwinner,sun6i-a31-spi", |
| 581 | .data = (ulong)&sun6i_a31_spi_variant, |
| 582 | }, |
| 583 | { |
| 584 | .compatible = "allwinner,sun8i-h3-spi", |
| 585 | .data = (ulong)&sun8i_h3_spi_variant, |
| 586 | }, |
Maksim Kiselev | 4d9267e | 2023-11-11 16:33:08 +0300 | [diff] [blame] | 587 | { |
| 588 | .compatible = "allwinner,sun50i-r329-spi", |
| 589 | .data = (ulong)&sun50i_r329_spi_variant, |
| 590 | }, |
Jagan Teki | 3f53a58 | 2019-02-27 20:02:12 +0530 | [diff] [blame] | 591 | { /* sentinel */ } |
Stefan Mavrodiev | 5d71604 | 2018-02-06 15:14:33 +0200 | [diff] [blame] | 592 | }; |
| 593 | |
| 594 | U_BOOT_DRIVER(sun4i_spi) = { |
| 595 | .name = "sun4i_spi", |
| 596 | .id = UCLASS_SPI, |
| 597 | .of_match = sun4i_spi_ids, |
| 598 | .ops = &sun4i_spi_ops, |
Simon Glass | aad29ae | 2020-12-03 16:55:21 -0700 | [diff] [blame] | 599 | .of_to_plat = sun4i_spi_of_to_plat, |
Simon Glass | b75b15b | 2020-12-03 16:55:23 -0700 | [diff] [blame] | 600 | .plat_auto = sizeof(struct sun4i_spi_plat), |
Simon Glass | 8a2b47f | 2020-12-03 16:55:17 -0700 | [diff] [blame] | 601 | .priv_auto = sizeof(struct sun4i_spi_priv), |
Stefan Mavrodiev | 5d71604 | 2018-02-06 15:14:33 +0200 | [diff] [blame] | 602 | .probe = sun4i_spi_probe, |
| 603 | }; |