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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Kumar Gala4c882892009-02-05 20:40:57 -06002/*
Poonam Aggrwal2ba3ee02011-01-13 21:39:27 +05303 * Copyright 2009-2011 Freescale Semiconductor, Inc.
Kumar Gala4c882892009-02-05 20:40:57 -06004 */
5
6#ifndef _ASM_CONFIG_H_
7#define _ASM_CONFIG_H_
8
Kumar Galafe137112011-01-19 03:05:26 -06009#ifdef CONFIG_MPC85xx
10#include <asm/config_mpc85xx.h>
11#endif
12
York Sune2cba152012-08-17 09:00:54 +000013#ifndef HWCONFIG_BUFFER_SIZE
14 #define HWCONFIG_BUFFER_SIZE 256
15#endif
16
Tom Rinibc9d46b2022-12-04 10:04:50 -050017#ifndef CFG_MAX_MEM_MAPPED
Heiko Schocher20280122017-06-27 16:49:14 +020018#if defined(CONFIG_E500) || \
York Sune12ce982011-08-26 11:32:44 -070019 defined(CONFIG_MPC86xx) || \
20 defined(CONFIG_E300)
Tom Rinibc9d46b2022-12-04 10:04:50 -050021#define CFG_MAX_MEM_MAPPED ((phys_size_t)2 << 30)
Kumar Gala4cd44a82009-02-05 20:40:58 -060022#else
Tom Rinibc9d46b2022-12-04 10:04:50 -050023#define CFG_MAX_MEM_MAPPED (256 << 20)
Kumar Gala4cd44a82009-02-05 20:40:58 -060024#endif
25#endif
26
Peter Tyser7feaacb2009-10-23 15:55:47 -050027/*
28 * Provide a default boot page translation virtual address that lines up with
29 * Freescale's default e500 reset page.
30 */
31#if (defined(CONFIG_E500) && defined(CONFIG_MP))
Tom Rini26483c12022-03-11 09:12:03 -050032#define BPTR_VIRT_ADDR 0xfffff000
Peter Tyser7feaacb2009-10-23 15:55:47 -050033#endif
34
Andy Fleming422effd2011-04-08 02:10:54 -050035/* The TSEC driver uses the PHYLIB infrastructure */
Zhao Qiangda6b88d2018-02-07 10:01:56 +080036#if defined(CONFIG_TSEC_ENET) && defined(CONFIG_PHYLIB)
Andy Fleming422effd2011-04-08 02:10:54 -050037#include <config_phylib_all_drivers.h>
38#endif /* TSEC_ENET */
Andy Fleming422effd2011-04-08 02:10:54 -050039
Kumar Gala2683c532011-04-13 08:37:44 -050040/* The FMAN driver uses the PHYLIB infrastructure */
Kumar Gala2683c532011-04-13 08:37:44 -050041
Marek Mojík064fb792024-06-06 18:33:25 +020042#if CONFIG_IS_ENABLED(DM_SERIAL) && !defined(CONFIG_CLK_MPC83XX)
Thomas Chou78b98812015-11-19 21:48:07 +080043/*
44 * TODO: Convert this to a clock driver exists that can give us the UART
45 * clock here.
46 */
Tom Rinidf6a2152022-11-16 13:10:28 -050047#define CFG_SYS_NS16550_CLK get_serial_clock()
Thomas Chou78b98812015-11-19 21:48:07 +080048#endif
49
Peter Tyserae7a7d42009-06-30 17:15:40 -050050#endif /* _ASM_CONFIG_H_ */