Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Kumar Gala | 4c88289 | 2009-02-05 20:40:57 -0600 | [diff] [blame] | 2 | /* |
Poonam Aggrwal | 2ba3ee0 | 2011-01-13 21:39:27 +0530 | [diff] [blame] | 3 | * Copyright 2009-2011 Freescale Semiconductor, Inc. |
Kumar Gala | 4c88289 | 2009-02-05 20:40:57 -0600 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #ifndef _ASM_CONFIG_H_ |
| 7 | #define _ASM_CONFIG_H_ |
| 8 | |
Kumar Gala | fe13711 | 2011-01-19 03:05:26 -0600 | [diff] [blame] | 9 | #ifdef CONFIG_MPC85xx |
| 10 | #include <asm/config_mpc85xx.h> |
| 11 | #endif |
| 12 | |
York Sun | e2cba15 | 2012-08-17 09:00:54 +0000 | [diff] [blame] | 13 | #ifndef HWCONFIG_BUFFER_SIZE |
| 14 | #define HWCONFIG_BUFFER_SIZE 256 |
| 15 | #endif |
| 16 | |
Tom Rini | bc9d46b | 2022-12-04 10:04:50 -0500 | [diff] [blame] | 17 | #ifndef CFG_MAX_MEM_MAPPED |
Heiko Schocher | 2028012 | 2017-06-27 16:49:14 +0200 | [diff] [blame] | 18 | #if defined(CONFIG_E500) || \ |
York Sun | e12ce98 | 2011-08-26 11:32:44 -0700 | [diff] [blame] | 19 | defined(CONFIG_MPC86xx) || \ |
| 20 | defined(CONFIG_E300) |
Tom Rini | bc9d46b | 2022-12-04 10:04:50 -0500 | [diff] [blame] | 21 | #define CFG_MAX_MEM_MAPPED ((phys_size_t)2 << 30) |
Kumar Gala | 4cd44a8 | 2009-02-05 20:40:58 -0600 | [diff] [blame] | 22 | #else |
Tom Rini | bc9d46b | 2022-12-04 10:04:50 -0500 | [diff] [blame] | 23 | #define CFG_MAX_MEM_MAPPED (256 << 20) |
Kumar Gala | 4cd44a8 | 2009-02-05 20:40:58 -0600 | [diff] [blame] | 24 | #endif |
| 25 | #endif |
| 26 | |
Peter Tyser | 7feaacb | 2009-10-23 15:55:47 -0500 | [diff] [blame] | 27 | /* |
| 28 | * Provide a default boot page translation virtual address that lines up with |
| 29 | * Freescale's default e500 reset page. |
| 30 | */ |
| 31 | #if (defined(CONFIG_E500) && defined(CONFIG_MP)) |
Tom Rini | 26483c1 | 2022-03-11 09:12:03 -0500 | [diff] [blame] | 32 | #define BPTR_VIRT_ADDR 0xfffff000 |
Peter Tyser | 7feaacb | 2009-10-23 15:55:47 -0500 | [diff] [blame] | 33 | #endif |
| 34 | |
Andy Fleming | 422effd | 2011-04-08 02:10:54 -0500 | [diff] [blame] | 35 | /* The TSEC driver uses the PHYLIB infrastructure */ |
Zhao Qiang | da6b88d | 2018-02-07 10:01:56 +0800 | [diff] [blame] | 36 | #if defined(CONFIG_TSEC_ENET) && defined(CONFIG_PHYLIB) |
Andy Fleming | 422effd | 2011-04-08 02:10:54 -0500 | [diff] [blame] | 37 | #include <config_phylib_all_drivers.h> |
| 38 | #endif /* TSEC_ENET */ |
Andy Fleming | 422effd | 2011-04-08 02:10:54 -0500 | [diff] [blame] | 39 | |
Kumar Gala | 2683c53 | 2011-04-13 08:37:44 -0500 | [diff] [blame] | 40 | /* The FMAN driver uses the PHYLIB infrastructure */ |
Kumar Gala | 2683c53 | 2011-04-13 08:37:44 -0500 | [diff] [blame] | 41 | |
Marek Mojík | 064fb79 | 2024-06-06 18:33:25 +0200 | [diff] [blame] | 42 | #if CONFIG_IS_ENABLED(DM_SERIAL) && !defined(CONFIG_CLK_MPC83XX) |
Thomas Chou | 78b9881 | 2015-11-19 21:48:07 +0800 | [diff] [blame] | 43 | /* |
| 44 | * TODO: Convert this to a clock driver exists that can give us the UART |
| 45 | * clock here. |
| 46 | */ |
Tom Rini | df6a215 | 2022-11-16 13:10:28 -0500 | [diff] [blame] | 47 | #define CFG_SYS_NS16550_CLK get_serial_clock() |
Thomas Chou | 78b9881 | 2015-11-19 21:48:07 +0800 | [diff] [blame] | 48 | #endif |
| 49 | |
Peter Tyser | ae7a7d4 | 2009-06-30 17:15:40 -0500 | [diff] [blame] | 50 | #endif /* _ASM_CONFIG_H_ */ |