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developerb73d7952020-01-10 16:30:26 +08001// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2019 MediaTek Inc.
4 * Author: Sam Shih <sam.shih@mediatek.com>
5 */
6
developerb73d7952020-01-10 16:30:26 +08007#include <fdtdec.h>
Simon Glass97589732020-05-10 11:40:02 -06008#include <init.h>
developerb73d7952020-01-10 16:30:26 +08009#include <asm/armv8/mmu.h>
developer87bf1bc2023-07-19 17:15:41 +080010#include <asm/system.h>
11#include <asm/global_data.h>
developer87bf1bc2023-07-19 17:15:41 +080012#include <linux/sizes.h>
13
14DECLARE_GLOBAL_DATA_PTR;
developerb73d7952020-01-10 16:30:26 +080015
16int print_cpuinfo(void)
17{
18 printf("CPU: MediaTek MT7622\n");
19 return 0;
20}
21
22int dram_init(void)
23{
24 int ret;
25
developer87bf1bc2023-07-19 17:15:41 +080026 ret = fdtdec_setup_mem_size_base();
developerb73d7952020-01-10 16:30:26 +080027 if (ret)
28 return ret;
developerb73d7952020-01-10 16:30:26 +080029
Frank Wunderlichdef764e2024-06-15 11:34:56 +020030 gd->ram_size = get_ram_size((void *)gd->ram_base, SZ_1G);
developer87bf1bc2023-07-19 17:15:41 +080031
32 return 0;
developerb73d7952020-01-10 16:30:26 +080033}
34
Harald Seiler6f14d5f2020-12-15 16:47:52 +010035void reset_cpu(void)
developerb73d7952020-01-10 16:30:26 +080036{
37 psci_system_reset();
38}
39
40static struct mm_region mt7622_mem_map[] = {
41 {
42 /* DDR */
43 .virt = 0x40000000UL,
44 .phys = 0x40000000UL,
45 .size = 0x40000000UL,
46 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
47 }, {
48 .virt = 0x00000000UL,
49 .phys = 0x00000000UL,
50 .size = 0x40000000UL,
51 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
52 PTE_BLOCK_NON_SHARE |
53 PTE_BLOCK_PXN | PTE_BLOCK_UXN
54 }, {
55 0,
56 }
57};
58struct mm_region *mem_map = mt7622_mem_map;