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git01.mediatek.com / filogic / uboot / 4104650c0c0ee1a067f08c65961c9ac6b4432adf / . / arch / arm / dts / k3-j721e-r5-common-proc-board.dts
blob: c7e344350c8508d008c1ed134d5675e5704773a3 [file] [log] [blame]
Lokesh Vutlaac736802019-06-13 10:29:55 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
Nishanth Menoneaa39c62023-11-01 15:56:03 -0500[diff] [blame]3 * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
Lokesh Vutlaac736802019-06-13 10:29:55 +0530[diff] [blame]4 */
5
6/dts-v1/;
7
Neha Malcom Francisbe557e92023-09-27 18:39:55 +0530[diff] [blame]8#include "k3-j721e-common-proc-board.dts"
Praneeth Bajjuri11077532020-12-03 17:43:47 -0600[diff] [blame]9#include "k3-j721e-ddr-evm-lp4-4266.dtsi"
Lokesh Vutla430a0b32019-10-07 19:26:37 +0530[diff] [blame]10#include "k3-j721e-ddr.dtsi"
Neha Malcom Francisbe557e92023-09-27 18:39:55 +0530[diff] [blame]11#include "k3-j721e-common-proc-board-u-boot.dtsi"
Lokesh Vutlaac736802019-06-13 10:29:55 +0530[diff] [blame]12
Neha Malcom Francis41046502024-05-20 15:29:14 +0530[diff] [blame^]13#include "k3-j721e-r5.dtsi"
Lokesh Vutlaac736802019-06-13 10:29:55 +0530[diff] [blame]14
Keerthyc6f86542019-10-24 15:00:59 +0530[diff] [blame]15&wkup_i2c0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]16 bootph-pre-ram;
Keerthyc6f86542019-10-24 15:00:59 +0530[diff] [blame]17 tps659413a: tps659413a@48 {
18 reg = <0x48>;
19 compatible = "ti,tps659413";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]20 bootph-pre-ram;
Keerthyc6f86542019-10-24 15:00:59 +0530[diff] [blame]21 pinctrl-names = "default";
22 pinctrl-0 = <&wkup_i2c0_pins_default>;
23 clock-frequency = <400000>;
24
25 regulators: regulators {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]26 bootph-pre-ram;
Keerthyc6f86542019-10-24 15:00:59 +0530[diff] [blame]27 buck12_reg: buck12 {
Keerthyac20ebd2022-02-10 09:25:58 +0530[diff] [blame]28 /*VDD_CPU*/
Keerthyc6f86542019-10-24 15:00:59 +0530[diff] [blame]29 regulator-name = "buck12";
Keerthyac20ebd2022-02-10 09:25:58 +0530[diff] [blame]30 regulator-min-microvolt = <600000>;
31 regulator-max-microvolt = <900000>;
Keerthyc6f86542019-10-24 15:00:59 +0530[diff] [blame]32 regulator-always-on;
33 regulator-boot-on;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]34 bootph-pre-ram;
Keerthyc6f86542019-10-24 15:00:59 +0530[diff] [blame]35 };
36 };
Neha Malcom Francisbe557e92023-09-27 18:39:55 +0530[diff] [blame]37
38 esm: esm {
39 compatible = "ti,tps659413-esm";
40 bootph-pre-ram;
41 };
Keerthyc6f86542019-10-24 15:00:59 +0530[diff] [blame]42 };
43};
44
Neha Malcom Franciscf5bc692023-09-27 18:39:56 +0530[diff] [blame]45&mcu_uart0_pins_default {
46 bootph-pre-ram;
Vignesh Raghavendra8a290cc2020-01-27 23:22:15 +0530[diff] [blame]47};
48
Neha Malcom Franciscf5bc692023-09-27 18:39:56 +0530[diff] [blame]49&wkup_vtm0 {
50 vdd-supply-2 = <&buck12_reg>;
51 bootph-pre-ram;
Vaishnav Achathfb708a42022-05-09 11:50:11 +0530[diff] [blame]52};
53
Vignesh Raghavendrada674372020-02-04 11:09:52 +0530[diff] [blame]54&ospi0 {
Neha Malcom Franciscf5bc692023-09-27 18:39:56 +0530[diff] [blame]55 /* Address change for data region (32-bit) */
Vignesh Raghavendrada674372020-02-04 11:09:52 +0530[diff] [blame]56 reg = <0x0 0x47040000 0x0 0x100>,
57 <0x0 0x50000000 0x0 0x8000000>;
Vignesh Raghavendrada674372020-02-04 11:09:52 +0530[diff] [blame]58};
59
Keerthy7b0b42d2020-03-04 10:10:01 +0530[diff] [blame]60&ospi1 {
Neha Malcom Franciscf5bc692023-09-27 18:39:56 +0530[diff] [blame]61 /* Address change for data region (32-bit) */
Keerthy7b0b42d2020-03-04 10:10:01 +0530[diff] [blame]62 reg = <0x0 0x47050000 0x0 0x100>,
63 <0x0 0x58000000 0x0 0x8000000>;
Sinthu Raja7fa564c2022-02-09 15:06:54 +0530[diff] [blame]64};