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git01.mediatek.com / filogic / uboot / cf5bc69dfc6043f34e996c382a0289673c769c68 / . / arch / arm / dts / k3-j721e-r5-common-proc-board.dts
blob: fcd9c716a5058ff4fddacb527193048907d53dfa [file] [log] [blame]
Lokesh Vutlaac736802019-06-13 10:29:55 +0530[diff] [blame]1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
4 */
5
6/dts-v1/;
7
Neha Malcom Francisbe557e92023-09-27 18:39:55 +0530[diff] [blame]8#include "k3-j721e-common-proc-board.dts"
Praneeth Bajjuri11077532020-12-03 17:43:47 -0600[diff] [blame]9#include "k3-j721e-ddr-evm-lp4-4266.dtsi"
Lokesh Vutla430a0b32019-10-07 19:26:37 +0530[diff] [blame]10#include "k3-j721e-ddr.dtsi"
Neha Malcom Francisbe557e92023-09-27 18:39:55 +0530[diff] [blame]11#include "k3-j721e-common-proc-board-u-boot.dtsi"
Lokesh Vutlaac736802019-06-13 10:29:55 +0530[diff] [blame]12
13/ {
Neha Malcom Franciscf5bc692023-09-27 18:39:56 +0530[diff] [blame^]14 chosen {
15 tick-timer = &mcu_timer0;
16 };
17
Lokesh Vutlaac736802019-06-13 10:29:55 +0530[diff] [blame]18 aliases {
19 remoteproc0 = &sysctrler;
20 remoteproc1 = &a72_0;
21 };
22
Lokesh Vutlaac736802019-06-13 10:29:55 +0530[diff] [blame]23 a72_0: a72@0 {
24 compatible = "ti,am654-rproc";
25 reg = <0x0 0x00a90000 0x0 0x10>;
26 power-domains = <&k3_pds 61 TI_SCI_PD_EXCLUSIVE>,
Manorit Chawdhryd9765d52023-04-14 09:47:54 +0530[diff] [blame]27 <&k3_pds 202 TI_SCI_PD_EXCLUSIVE>,
28 <&k3_pds 4 TI_SCI_PD_EXCLUSIVE>;
Lokesh Vutlaac736802019-06-13 10:29:55 +0530[diff] [blame]29 resets = <&k3_reset 202 0>;
Nishanth Menon975b78c2021-01-06 13:20:31 -0600[diff] [blame]30 clocks = <&k3_clks 61 1>;
Lokesh Vutlaac736802019-06-13 10:29:55 +0530[diff] [blame]31 assigned-clocks = <&k3_clks 202 2>, <&k3_clks 61 1>;
32 assigned-clock-rates = <2000000000>, <200000000>;
33 ti,sci = <&dmsc>;
34 ti,sci-proc-id = <32>;
35 ti,sci-host-id = <10>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]36 bootph-pre-ram;
Keerthybe86d322019-10-24 15:00:58 +0530[diff] [blame]37 };
Vignesh Raghavendra98181972021-06-07 19:47:50 +0530[diff] [blame]38
39 dm_tifs: dm-tifs {
40 compatible = "ti,j721e-dm-sci";
41 ti,host-id = <3>;
42 ti,secure-host;
43 mbox-names = "rx", "tx";
Neha Malcom Franciscf5bc692023-09-27 18:39:56 +0530[diff] [blame^]44 mboxes= <&secure_proxy_mcu 21>,
45 <&secure_proxy_mcu 23>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]46 bootph-pre-ram;
Vignesh Raghavendra98181972021-06-07 19:47:50 +0530[diff] [blame]47 };
Lokesh Vutlaac736802019-06-13 10:29:55 +0530[diff] [blame]48};
49
Neha Malcom Franciscf5bc692023-09-27 18:39:56 +0530[diff] [blame^]50&mcu_timer0 {
51 status = "okay";
52 bootph-pre-ram;
Tero Kristo3cafcd82020-02-14 11:18:17 +0200[diff] [blame]53};
54
Lokesh Vutlaac736802019-06-13 10:29:55 +0530[diff] [blame]55&dmsc {
Neha Malcom Franciscf5bc692023-09-27 18:39:56 +0530[diff] [blame^]56 mboxes= <&secure_proxy_mcu 8>, <&secure_proxy_mcu 6>, <&secure_proxy_mcu 5>;
Lokesh Vutlaac736802019-06-13 10:29:55 +0530[diff] [blame]57 mbox-names = "tx", "rx", "notify";
58 ti,host-id = <4>;
59 ti,secure-host;
60};
61
Neha Malcom Franciscf5bc692023-09-27 18:39:56 +0530[diff] [blame^]62&secure_proxy_mcu {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]63 bootph-pre-ram;
Lokesh Vutlaac736802019-06-13 10:29:55 +0530[diff] [blame]64 status = "okay";
65};
66
Neha Malcom Franciscf5bc692023-09-27 18:39:56 +0530[diff] [blame^]67&cbass_mcu_wakeup {
68 sysctrler: sysctrler {
69 bootph-pre-ram;
70 compatible = "ti,am654-system-controller";
71 mboxes= <&secure_proxy_mcu 4>, <&secure_proxy_mcu 5>;
72 mbox-names = "tx", "rx";
73 };
Lokesh Vutlaac736802019-06-13 10:29:55 +0530[diff] [blame]74};
75
Neha Malcom Franciscf5bc692023-09-27 18:39:56 +0530[diff] [blame^]76&mcu_ringacc {
77 ti,sci = <&dm_tifs>;
Lokesh Vutlaac736802019-06-13 10:29:55 +0530[diff] [blame]78};
79
Neha Malcom Franciscf5bc692023-09-27 18:39:56 +0530[diff] [blame^]80&mcu_udmap {
81 ti,sci = <&dm_tifs>;
Lokesh Vutlaac736802019-06-13 10:29:55 +0530[diff] [blame]82};
83
Keerthyc6f86542019-10-24 15:00:59 +0530[diff] [blame]84&wkup_i2c0 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]85 bootph-pre-ram;
Keerthyc6f86542019-10-24 15:00:59 +0530[diff] [blame]86 tps659413a: tps659413a@48 {
87 reg = <0x48>;
88 compatible = "ti,tps659413";
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]89 bootph-pre-ram;
Keerthyc6f86542019-10-24 15:00:59 +0530[diff] [blame]90 pinctrl-names = "default";
91 pinctrl-0 = <&wkup_i2c0_pins_default>;
92 clock-frequency = <400000>;
93
94 regulators: regulators {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]95 bootph-pre-ram;
Keerthyc6f86542019-10-24 15:00:59 +0530[diff] [blame]96 buck12_reg: buck12 {
Keerthyac20ebd2022-02-10 09:25:58 +0530[diff] [blame]97 /*VDD_CPU*/
Keerthyc6f86542019-10-24 15:00:59 +0530[diff] [blame]98 regulator-name = "buck12";
Keerthyac20ebd2022-02-10 09:25:58 +0530[diff] [blame]99 regulator-min-microvolt = <600000>;
100 regulator-max-microvolt = <900000>;
Keerthyc6f86542019-10-24 15:00:59 +0530[diff] [blame]101 regulator-always-on;
102 regulator-boot-on;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]103 bootph-pre-ram;
Keerthyc6f86542019-10-24 15:00:59 +0530[diff] [blame]104 };
105 };
Neha Malcom Francisbe557e92023-09-27 18:39:55 +0530[diff] [blame]106
107 esm: esm {
108 compatible = "ti,tps659413-esm";
109 bootph-pre-ram;
110 };
Keerthyc6f86542019-10-24 15:00:59 +0530[diff] [blame]111 };
112};
113
Neha Malcom Franciscf5bc692023-09-27 18:39:56 +0530[diff] [blame^]114&wkup_uart0_pins_default {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]115 bootph-pre-ram;
Keerthy7c9fa302019-10-24 15:01:00 +0530[diff] [blame]116};
117
Neha Malcom Franciscf5bc692023-09-27 18:39:56 +0530[diff] [blame^]118&mcu_uart0_pins_default {
119 bootph-pre-ram;
Vignesh Raghavendra8a290cc2020-01-27 23:22:15 +0530[diff] [blame]120};
121
Neha Malcom Franciscf5bc692023-09-27 18:39:56 +0530[diff] [blame^]122&wkup_vtm0 {
123 vdd-supply-2 = <&buck12_reg>;
124 bootph-pre-ram;
Vaishnav Achathfb708a42022-05-09 11:50:11 +0530[diff] [blame]125};
126
Vignesh Raghavendrada674372020-02-04 11:09:52 +0530[diff] [blame]127&ospi0 {
Neha Malcom Franciscf5bc692023-09-27 18:39:56 +0530[diff] [blame^]128 /* Address change for data region (32-bit) */
Vignesh Raghavendrada674372020-02-04 11:09:52 +0530[diff] [blame]129 reg = <0x0 0x47040000 0x0 0x100>,
130 <0x0 0x50000000 0x0 0x8000000>;
Vignesh Raghavendrada674372020-02-04 11:09:52 +0530[diff] [blame]131};
132
Keerthy7b0b42d2020-03-04 10:10:01 +0530[diff] [blame]133&ospi1 {
Neha Malcom Franciscf5bc692023-09-27 18:39:56 +0530[diff] [blame^]134 /* Address change for data region (32-bit) */
Keerthy7b0b42d2020-03-04 10:10:01 +0530[diff] [blame]135 reg = <0x0 0x47050000 0x0 0x100>,
136 <0x0 0x58000000 0x0 0x8000000>;
Sinthu Raja7fa564c2022-02-09 15:06:54 +0530[diff] [blame]137};