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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Poonam Aggrwala2ec1352011-02-09 19:17:53 +00002/*
3 * Copyright 2010-2011 Freescale Semiconductor, Inc.
Poonam Aggrwala2ec1352011-02-09 19:17:53 +00004 */
5
6#include <common.h>
7#include <asm/mmu.h>
8
9struct fsl_e_tlb_entry tlb_table[] = {
10 /* TLB 0 - for temp stack in cache */
11 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
12 MAS3_SX|MAS3_SW|MAS3_SR, 0,
13 0, 0, BOOKE_PAGESZ_4K, 0),
14 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
15 CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
16 MAS3_SX|MAS3_SW|MAS3_SR, 0,
17 0, 0, BOOKE_PAGESZ_4K, 0),
18 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
19 CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
20 MAS3_SX|MAS3_SW|MAS3_SR, 0,
21 0, 0, BOOKE_PAGESZ_4K, 0),
22 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
23 CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
24 MAS3_SX|MAS3_SW|MAS3_SR, 0,
25 0, 0, BOOKE_PAGESZ_4K, 0),
26
27 /* TLB 1 */
28 /* *I*** - Covers boot page */
Prabhakar Kushwahad6a7aba2013-05-07 11:19:55 +053029 SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
30 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
31 0, 0, BOOKE_PAGESZ_4K, 1),
Prabhakar Kushwahaafffcb02013-12-11 12:42:11 +053032#ifdef CONFIG_SPL_NAND_BOOT
Prabhakar Kushwaha66d6aa82013-04-16 13:28:12 +053033 SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000,
34 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
Prabhakar Kushwahad6a7aba2013-05-07 11:19:55 +053035 0, 10, BOOKE_PAGESZ_4K, 1),
36#endif
Poonam Aggrwala2ec1352011-02-09 19:17:53 +000037
38 /* *I*G* - CCSRBAR */
39 SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
40 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
41 0, 1, BOOKE_PAGESZ_1M, 1),
42
Prabhakar Kushwaha66d6aa82013-04-16 13:28:12 +053043#ifndef CONFIG_SPL_BUILD
Poonam Aggrwala2ec1352011-02-09 19:17:53 +000044 SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
45 MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
46 0, 2, BOOKE_PAGESZ_16M, 1),
47
48 SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x1000000,
49 CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000,
50 MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
51 0, 3, BOOKE_PAGESZ_16M, 1),
Poonam Aggrwala2ec1352011-02-09 19:17:53 +000052
Prabhakar Kushwaha5b029e92013-05-17 14:22:34 +053053#ifdef CONFIG_PCI
Poonam Aggrwala2ec1352011-02-09 19:17:53 +000054 /* *I*G* - PCI */
Tom Rini56af6592022-11-16 13:10:33 -050055 SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT, CFG_SYS_PCIE1_MEM_PHYS,
Poonam Aggrwala2ec1352011-02-09 19:17:53 +000056 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
57 0, 4, BOOKE_PAGESZ_1G, 1),
58
59 /* *I*G* - PCI I/O */
Tom Rini56af6592022-11-16 13:10:33 -050060 SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS,
Poonam Aggrwala2ec1352011-02-09 19:17:53 +000061 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
62 0, 5, BOOKE_PAGESZ_256K, 1),
63#endif
64#endif
65
Poonam Aggrwala2ec1352011-02-09 19:17:53 +000066 /* *I*G - Board CPLD */
67 SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
68 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
69 0, 6, BOOKE_PAGESZ_256K, 1),
70
Tom Rinib4213492022-11-12 17:36:51 -050071 SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS,
Poonam Aggrwala2ec1352011-02-09 19:17:53 +000072 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
73 0, 7, BOOKE_PAGESZ_1M, 1),
Poonam Aggrwala2ec1352011-02-09 19:17:53 +000074
Tom Rinif8f6b322022-05-21 14:44:28 -040075#if defined(CONFIG_SYS_RAMBOOT) || !CONFIG_IS_ENABLED(COMMON_INIT_DDR)
Poonam Aggrwala2ec1352011-02-09 19:17:53 +000076 SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
York Sun05204d02017-12-05 10:57:54 -080077 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
Ying Zhang1233cbc2014-01-24 15:50:09 +080078 0, 8, BOOKE_PAGESZ_1G, 1),
79#endif
80
81#ifdef CONFIG_SYS_INIT_L2_ADDR
82 /* *I*G - L2SRAM */
83 SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
84 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
85 0, 11, BOOKE_PAGESZ_256K, 1)
Poonam Aggrwala2ec1352011-02-09 19:17:53 +000086#endif
87};
88
89int num_tlb_entries = ARRAY_SIZE(tlb_table);