Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 2 | /* |
| 3 | * Copyright 2010-2011 Freescale Semiconductor, Inc. |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #include <common.h> |
| 7 | #include <asm/mmu.h> |
| 8 | |
| 9 | struct fsl_e_tlb_entry tlb_table[] = { |
| 10 | /* TLB 0 - for temp stack in cache */ |
| 11 | SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, |
| 12 | MAS3_SX|MAS3_SW|MAS3_SR, 0, |
| 13 | 0, 0, BOOKE_PAGESZ_4K, 0), |
| 14 | SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , |
| 15 | CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, |
| 16 | MAS3_SX|MAS3_SW|MAS3_SR, 0, |
| 17 | 0, 0, BOOKE_PAGESZ_4K, 0), |
| 18 | SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , |
| 19 | CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, |
| 20 | MAS3_SX|MAS3_SW|MAS3_SR, 0, |
| 21 | 0, 0, BOOKE_PAGESZ_4K, 0), |
| 22 | SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , |
| 23 | CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, |
| 24 | MAS3_SX|MAS3_SW|MAS3_SR, 0, |
| 25 | 0, 0, BOOKE_PAGESZ_4K, 0), |
| 26 | |
| 27 | /* TLB 1 */ |
| 28 | /* *I*** - Covers boot page */ |
Prabhakar Kushwaha | d6a7aba | 2013-05-07 11:19:55 +0530 | [diff] [blame] | 29 | SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, |
| 30 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
| 31 | 0, 0, BOOKE_PAGESZ_4K, 1), |
Prabhakar Kushwaha | afffcb0 | 2013-12-11 12:42:11 +0530 | [diff] [blame] | 32 | #ifdef CONFIG_SPL_NAND_BOOT |
Prabhakar Kushwaha | 66d6aa8 | 2013-04-16 13:28:12 +0530 | [diff] [blame] | 33 | SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000, |
| 34 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
Prabhakar Kushwaha | d6a7aba | 2013-05-07 11:19:55 +0530 | [diff] [blame] | 35 | 0, 10, BOOKE_PAGESZ_4K, 1), |
| 36 | #endif |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 37 | |
| 38 | /* *I*G* - CCSRBAR */ |
| 39 | SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, |
| 40 | MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
| 41 | 0, 1, BOOKE_PAGESZ_1M, 1), |
| 42 | |
Prabhakar Kushwaha | 66d6aa8 | 2013-04-16 13:28:12 +0530 | [diff] [blame] | 43 | #ifndef CONFIG_SPL_BUILD |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 44 | SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, |
| 45 | MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, |
| 46 | 0, 2, BOOKE_PAGESZ_16M, 1), |
| 47 | |
| 48 | SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x1000000, |
| 49 | CONFIG_SYS_FLASH_BASE_PHYS + 0x1000000, |
| 50 | MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, |
| 51 | 0, 3, BOOKE_PAGESZ_16M, 1), |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 52 | |
Prabhakar Kushwaha | 5b029e9 | 2013-05-17 14:22:34 +0530 | [diff] [blame] | 53 | #ifdef CONFIG_PCI |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 54 | /* *I*G* - PCI */ |
Tom Rini | 56af659 | 2022-11-16 13:10:33 -0500 | [diff] [blame] | 55 | SET_TLB_ENTRY(1, CFG_SYS_PCIE1_MEM_VIRT, CFG_SYS_PCIE1_MEM_PHYS, |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 56 | MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
| 57 | 0, 4, BOOKE_PAGESZ_1G, 1), |
| 58 | |
| 59 | /* *I*G* - PCI I/O */ |
Tom Rini | 56af659 | 2022-11-16 13:10:33 -0500 | [diff] [blame] | 60 | SET_TLB_ENTRY(1, CFG_SYS_PCIE1_IO_VIRT, CFG_SYS_PCIE1_IO_PHYS, |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 61 | MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
| 62 | 0, 5, BOOKE_PAGESZ_256K, 1), |
| 63 | #endif |
| 64 | #endif |
| 65 | |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 66 | /* *I*G - Board CPLD */ |
| 67 | SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, |
| 68 | MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
| 69 | 0, 6, BOOKE_PAGESZ_256K, 1), |
| 70 | |
Tom Rini | b421349 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 71 | SET_TLB_ENTRY(1, CFG_SYS_NAND_BASE, CFG_SYS_NAND_BASE_PHYS, |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 72 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, |
| 73 | 0, 7, BOOKE_PAGESZ_1M, 1), |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 74 | |
Tom Rini | f8f6b32 | 2022-05-21 14:44:28 -0400 | [diff] [blame] | 75 | #if defined(CONFIG_SYS_RAMBOOT) || !CONFIG_IS_ENABLED(COMMON_INIT_DDR) |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 76 | SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, |
York Sun | 05204d0 | 2017-12-05 10:57:54 -0800 | [diff] [blame] | 77 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M, |
Ying Zhang | 1233cbc | 2014-01-24 15:50:09 +0800 | [diff] [blame] | 78 | 0, 8, BOOKE_PAGESZ_1G, 1), |
| 79 | #endif |
| 80 | |
| 81 | #ifdef CONFIG_SYS_INIT_L2_ADDR |
| 82 | /* *I*G - L2SRAM */ |
| 83 | SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, |
| 84 | MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G, |
| 85 | 0, 11, BOOKE_PAGESZ_256K, 1) |
Poonam Aggrwal | a2ec135 | 2011-02-09 19:17:53 +0000 | [diff] [blame] | 86 | #endif |
| 87 | }; |
| 88 | |
| 89 | int num_tlb_entries = ARRAY_SIZE(tlb_table); |