Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
Scott Wood | b71689b | 2008-06-30 14:13:28 -0500 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. |
Scott Wood | b71689b | 2008-06-30 14:13:28 -0500 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #include <common.h> |
Simon Glass | 40d9b24 | 2020-05-10 11:40:07 -0600 | [diff] [blame^] | 7 | #include <asm-offsets.h> |
Simon Glass | 85d6531 | 2019-12-28 10:44:58 -0700 | [diff] [blame] | 8 | #include <clock_legacy.h> |
Scott Wood | b71689b | 2008-06-30 14:13:28 -0500 | [diff] [blame] | 9 | #include <mpc83xx.h> |
Simon Glass | a9dc068 | 2019-12-28 10:44:59 -0700 | [diff] [blame] | 10 | #include <time.h> |
Scott Wood | b71689b | 2008-06-30 14:13:28 -0500 | [diff] [blame] | 11 | |
Mario Six | b47839c | 2019-01-21 09:17:58 +0100 | [diff] [blame] | 12 | #include "lblaw/lblaw.h" |
Mario Six | 1faf95d | 2019-01-21 09:18:03 +0100 | [diff] [blame] | 13 | #include "elbc/elbc.h" |
Mario Six | b47839c | 2019-01-21 09:17:58 +0100 | [diff] [blame] | 14 | |
Scott Wood | b71689b | 2008-06-30 14:13:28 -0500 | [diff] [blame] | 15 | DECLARE_GLOBAL_DATA_PTR; |
| 16 | |
| 17 | /* |
| 18 | * Breathe some life into the CPU... |
| 19 | * |
| 20 | * Set up the memory map, |
| 21 | * initialize a bunch of registers, |
| 22 | * initialize the UPM's |
| 23 | */ |
| 24 | void cpu_init_f (volatile immap_t * im) |
| 25 | { |
Scott Wood | b71689b | 2008-06-30 14:13:28 -0500 | [diff] [blame] | 26 | /* Pointer is writable since we allocated a register for it */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 27 | gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET); |
Scott Wood | b71689b | 2008-06-30 14:13:28 -0500 | [diff] [blame] | 28 | |
mario.six@gdsys.cc | 85df7b4 | 2017-01-17 08:33:48 +0100 | [diff] [blame] | 29 | /* global data region was cleared in start.S */ |
Scott Wood | b71689b | 2008-06-30 14:13:28 -0500 | [diff] [blame] | 30 | |
| 31 | /* system performance tweaking */ |
| 32 | |
Mario Six | aa50254 | 2019-01-21 09:18:12 +0100 | [diff] [blame] | 33 | #ifndef CONFIG_ACR_PIPE_DEP_UNSET |
Scott Wood | b71689b | 2008-06-30 14:13:28 -0500 | [diff] [blame] | 34 | /* Arbiter pipeline depth */ |
| 35 | im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) | |
Mario Six | aa50254 | 2019-01-21 09:18:12 +0100 | [diff] [blame] | 36 | CONFIG_ACR_PIPE_DEP; |
Scott Wood | b71689b | 2008-06-30 14:13:28 -0500 | [diff] [blame] | 37 | #endif |
| 38 | |
Mario Six | aa50254 | 2019-01-21 09:18:12 +0100 | [diff] [blame] | 39 | #ifndef CONFIG_ACR_RPTCNT_UNSET |
Scott Wood | b71689b | 2008-06-30 14:13:28 -0500 | [diff] [blame] | 40 | /* Arbiter repeat count */ |
| 41 | im->arbiter.acr = (im->arbiter.acr & ~(ACR_RPTCNT)) | |
Mario Six | aa50254 | 2019-01-21 09:18:12 +0100 | [diff] [blame] | 42 | CONFIG_ACR_RPTCNT; |
Scott Wood | b71689b | 2008-06-30 14:13:28 -0500 | [diff] [blame] | 43 | #endif |
| 44 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 45 | #ifdef CONFIG_SYS_SPCR_OPT |
Scott Wood | b71689b | 2008-06-30 14:13:28 -0500 | [diff] [blame] | 46 | /* Optimize transactions between CSB and other devices */ |
| 47 | im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_OPT) | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 48 | (CONFIG_SYS_SPCR_OPT << SPCR_OPT_SHIFT); |
Scott Wood | b71689b | 2008-06-30 14:13:28 -0500 | [diff] [blame] | 49 | #endif |
| 50 | |
Robert P. J. Day | cbd618f | 2015-12-16 12:25:42 -0500 | [diff] [blame] | 51 | /* Enable Time Base & Decrementer (so we will have udelay()) */ |
Scott Wood | b71689b | 2008-06-30 14:13:28 -0500 | [diff] [blame] | 52 | im->sysconf.spcr |= SPCR_TBEN; |
| 53 | |
| 54 | /* DDR control driver register */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 55 | #ifdef CONFIG_SYS_DDRCDR |
| 56 | im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR; |
Scott Wood | b71689b | 2008-06-30 14:13:28 -0500 | [diff] [blame] | 57 | #endif |
| 58 | /* Output buffer impedance register */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 59 | #ifdef CONFIG_SYS_OBIR |
| 60 | im->sysconf.obir = CONFIG_SYS_OBIR; |
Scott Wood | b71689b | 2008-06-30 14:13:28 -0500 | [diff] [blame] | 61 | #endif |
| 62 | |
| 63 | /* |
| 64 | * Memory Controller: |
| 65 | */ |
| 66 | |
| 67 | /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary |
| 68 | * addresses - these have to be modified later when FLASH size |
| 69 | * has been determined |
| 70 | */ |
| 71 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 72 | #if defined(CONFIG_SYS_NAND_BR_PRELIM) \ |
| 73 | && defined(CONFIG_SYS_NAND_OR_PRELIM) \ |
| 74 | && defined(CONFIG_SYS_NAND_LBLAWBAR_PRELIM) \ |
| 75 | && defined(CONFIG_SYS_NAND_LBLAWAR_PRELIM) |
Becky Bruce | 0d4cee1 | 2010-06-17 11:37:20 -0500 | [diff] [blame] | 76 | set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM); |
| 77 | set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM); |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 78 | im->sysconf.lblaw[0].bar = CONFIG_SYS_NAND_LBLAWBAR_PRELIM; |
| 79 | im->sysconf.lblaw[0].ar = CONFIG_SYS_NAND_LBLAWAR_PRELIM; |
Scott Wood | b71689b | 2008-06-30 14:13:28 -0500 | [diff] [blame] | 80 | #else |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 81 | #error CONFIG_SYS_NAND_BR_PRELIM, CONFIG_SYS_NAND_OR_PRELIM, CONFIG_SYS_NAND_LBLAWBAR_PRELIM & CONFIG_SYS_NAND_LBLAWAR_PRELIM must be defined |
Scott Wood | b71689b | 2008-06-30 14:13:28 -0500 | [diff] [blame] | 82 | #endif |
| 83 | } |
| 84 | |
| 85 | /* |
| 86 | * Get timebase clock frequency (like cpu_clk in Hz) |
| 87 | */ |
| 88 | unsigned long get_tbclk(void) |
| 89 | { |
| 90 | return (gd->bus_clk + 3L) / 4L; |
| 91 | } |
| 92 | |
| 93 | void puts(const char *str) |
| 94 | { |
| 95 | while (*str) |
| 96 | putc(*str++); |
| 97 | } |
Mario Six | cd677ca | 2019-01-21 09:17:52 +0100 | [diff] [blame] | 98 | |
| 99 | ulong get_bus_freq(ulong dummy) |
| 100 | { |
| 101 | volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR; |
| 102 | u8 spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT; |
| 103 | |
Mario Six | d10f318 | 2019-01-21 09:17:53 +0100 | [diff] [blame] | 104 | return CONFIG_SYS_CLK_FREQ * spmf; |
Mario Six | cd677ca | 2019-01-21 09:17:52 +0100 | [diff] [blame] | 105 | } |