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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Scott Woodb71689b2008-06-30 14:13:28 -05002/*
3 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
Scott Woodb71689b2008-06-30 14:13:28 -05004 */
5
6#include <common.h>
Simon Glass85d65312019-12-28 10:44:58 -07007#include <clock_legacy.h>
Scott Woodb71689b2008-06-30 14:13:28 -05008#include <mpc83xx.h>
9
Mario Sixb47839c2019-01-21 09:17:58 +010010#include "lblaw/lblaw.h"
Mario Six1faf95d2019-01-21 09:18:03 +010011#include "elbc/elbc.h"
Mario Sixb47839c2019-01-21 09:17:58 +010012
Scott Woodb71689b2008-06-30 14:13:28 -050013DECLARE_GLOBAL_DATA_PTR;
14
15/*
16 * Breathe some life into the CPU...
17 *
18 * Set up the memory map,
19 * initialize a bunch of registers,
20 * initialize the UPM's
21 */
22void cpu_init_f (volatile immap_t * im)
23{
Scott Woodb71689b2008-06-30 14:13:28 -050024 /* Pointer is writable since we allocated a register for it */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020025 gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
Scott Woodb71689b2008-06-30 14:13:28 -050026
mario.six@gdsys.cc85df7b42017-01-17 08:33:48 +010027 /* global data region was cleared in start.S */
Scott Woodb71689b2008-06-30 14:13:28 -050028
29 /* system performance tweaking */
30
Mario Sixaa502542019-01-21 09:18:12 +010031#ifndef CONFIG_ACR_PIPE_DEP_UNSET
Scott Woodb71689b2008-06-30 14:13:28 -050032 /* Arbiter pipeline depth */
33 im->arbiter.acr = (im->arbiter.acr & ~ACR_PIPE_DEP) |
Mario Sixaa502542019-01-21 09:18:12 +010034 CONFIG_ACR_PIPE_DEP;
Scott Woodb71689b2008-06-30 14:13:28 -050035#endif
36
Mario Sixaa502542019-01-21 09:18:12 +010037#ifndef CONFIG_ACR_RPTCNT_UNSET
Scott Woodb71689b2008-06-30 14:13:28 -050038 /* Arbiter repeat count */
39 im->arbiter.acr = (im->arbiter.acr & ~(ACR_RPTCNT)) |
Mario Sixaa502542019-01-21 09:18:12 +010040 CONFIG_ACR_RPTCNT;
Scott Woodb71689b2008-06-30 14:13:28 -050041#endif
42
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020043#ifdef CONFIG_SYS_SPCR_OPT
Scott Woodb71689b2008-06-30 14:13:28 -050044 /* Optimize transactions between CSB and other devices */
45 im->sysconf.spcr = (im->sysconf.spcr & ~SPCR_OPT) |
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020046 (CONFIG_SYS_SPCR_OPT << SPCR_OPT_SHIFT);
Scott Woodb71689b2008-06-30 14:13:28 -050047#endif
48
Robert P. J. Daycbd618f2015-12-16 12:25:42 -050049 /* Enable Time Base & Decrementer (so we will have udelay()) */
Scott Woodb71689b2008-06-30 14:13:28 -050050 im->sysconf.spcr |= SPCR_TBEN;
51
52 /* DDR control driver register */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020053#ifdef CONFIG_SYS_DDRCDR
54 im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR;
Scott Woodb71689b2008-06-30 14:13:28 -050055#endif
56 /* Output buffer impedance register */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020057#ifdef CONFIG_SYS_OBIR
58 im->sysconf.obir = CONFIG_SYS_OBIR;
Scott Woodb71689b2008-06-30 14:13:28 -050059#endif
60
61 /*
62 * Memory Controller:
63 */
64
65 /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
66 * addresses - these have to be modified later when FLASH size
67 * has been determined
68 */
69
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020070#if defined(CONFIG_SYS_NAND_BR_PRELIM) \
71 && defined(CONFIG_SYS_NAND_OR_PRELIM) \
72 && defined(CONFIG_SYS_NAND_LBLAWBAR_PRELIM) \
73 && defined(CONFIG_SYS_NAND_LBLAWAR_PRELIM)
Becky Bruce0d4cee12010-06-17 11:37:20 -050074 set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
75 set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020076 im->sysconf.lblaw[0].bar = CONFIG_SYS_NAND_LBLAWBAR_PRELIM;
77 im->sysconf.lblaw[0].ar = CONFIG_SYS_NAND_LBLAWAR_PRELIM;
Scott Woodb71689b2008-06-30 14:13:28 -050078#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020079#error CONFIG_SYS_NAND_BR_PRELIM, CONFIG_SYS_NAND_OR_PRELIM, CONFIG_SYS_NAND_LBLAWBAR_PRELIM & CONFIG_SYS_NAND_LBLAWAR_PRELIM must be defined
Scott Woodb71689b2008-06-30 14:13:28 -050080#endif
81}
82
83/*
84 * Get timebase clock frequency (like cpu_clk in Hz)
85 */
86unsigned long get_tbclk(void)
87{
88 return (gd->bus_clk + 3L) / 4L;
89}
90
91void puts(const char *str)
92{
93 while (*str)
94 putc(*str++);
95}
Mario Sixcd677ca2019-01-21 09:17:52 +010096
97ulong get_bus_freq(ulong dummy)
98{
99 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
100 u8 spmf = (im->clk.spmr & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
101
Mario Sixd10f3182019-01-21 09:17:53 +0100102 return CONFIG_SYS_CLK_FREQ * spmf;
Mario Sixcd677ca2019-01-21 09:17:52 +0100103}