Patrick Delaunay | 5059914 | 2018-07-09 15:17:19 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) |
| 2 | /* |
| 3 | * Copyright (C) STMicroelectronics 2017 - All Rights Reserved |
| 4 | * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics. |
| 5 | */ |
| 6 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 7 | #include <dt-bindings/clock/stm32mp1-clks.h> |
| 8 | #include <dt-bindings/reset/stm32mp1-resets.h> |
| 9 | |
| 10 | / { |
| 11 | #address-cells = <1>; |
| 12 | #size-cells = <1>; |
| 13 | |
| 14 | cpus { |
| 15 | #address-cells = <1>; |
| 16 | #size-cells = <0>; |
| 17 | |
| 18 | cpu0: cpu@0 { |
| 19 | compatible = "arm,cortex-a7"; |
| 20 | device_type = "cpu"; |
| 21 | reg = <0>; |
| 22 | }; |
| 23 | |
| 24 | cpu1: cpu@1 { |
| 25 | compatible = "arm,cortex-a7"; |
| 26 | device_type = "cpu"; |
| 27 | reg = <1>; |
| 28 | }; |
| 29 | }; |
| 30 | |
| 31 | psci { |
Patrick Delaunay | 632341f | 2019-02-04 11:26:21 +0100 | [diff] [blame] | 32 | compatible = "arm,psci-1.0"; |
Patrick Delaunay | 5059914 | 2018-07-09 15:17:19 +0200 | [diff] [blame] | 33 | method = "smc"; |
| 34 | cpu_off = <0x84000002>; |
| 35 | cpu_on = <0x84000003>; |
| 36 | }; |
| 37 | |
Patrick Delaunay | 5059914 | 2018-07-09 15:17:19 +0200 | [diff] [blame] | 38 | intc: interrupt-controller@a0021000 { |
| 39 | compatible = "arm,cortex-a7-gic"; |
| 40 | #interrupt-cells = <3>; |
| 41 | interrupt-controller; |
| 42 | reg = <0xa0021000 0x1000>, |
| 43 | <0xa0022000 0x2000>; |
| 44 | }; |
| 45 | |
| 46 | timer { |
| 47 | compatible = "arm,armv7-timer"; |
| 48 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| 49 | <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| 50 | <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| 51 | <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; |
| 52 | interrupt-parent = <&intc>; |
| 53 | }; |
| 54 | |
| 55 | clocks { |
| 56 | clk_hse: clk-hse { |
| 57 | #clock-cells = <0>; |
| 58 | compatible = "fixed-clock"; |
| 59 | clock-frequency = <24000000>; |
| 60 | }; |
| 61 | |
| 62 | clk_hsi: clk-hsi { |
| 63 | #clock-cells = <0>; |
| 64 | compatible = "fixed-clock"; |
| 65 | clock-frequency = <64000000>; |
| 66 | }; |
| 67 | |
| 68 | clk_lse: clk-lse { |
| 69 | #clock-cells = <0>; |
| 70 | compatible = "fixed-clock"; |
| 71 | clock-frequency = <32768>; |
| 72 | }; |
| 73 | |
| 74 | clk_lsi: clk-lsi { |
| 75 | #clock-cells = <0>; |
| 76 | compatible = "fixed-clock"; |
| 77 | clock-frequency = <32000>; |
| 78 | }; |
| 79 | |
| 80 | clk_csi: clk-csi { |
| 81 | #clock-cells = <0>; |
| 82 | compatible = "fixed-clock"; |
| 83 | clock-frequency = <4000000>; |
| 84 | }; |
| 85 | }; |
| 86 | |
Patrick Delaunay | a370530 | 2019-07-11 11:15:28 +0200 | [diff] [blame] | 87 | thermal-zones { |
| 88 | cpu_thermal: cpu-thermal { |
| 89 | polling-delay-passive = <0>; |
| 90 | polling-delay = <0>; |
| 91 | thermal-sensors = <&dts>; |
| 92 | |
| 93 | trips { |
| 94 | cpu_alert1: cpu-alert1 { |
| 95 | temperature = <85000>; |
| 96 | hysteresis = <0>; |
| 97 | type = "passive"; |
| 98 | }; |
| 99 | |
| 100 | cpu-crit { |
| 101 | temperature = <120000>; |
| 102 | hysteresis = <0>; |
| 103 | type = "critical"; |
| 104 | }; |
| 105 | }; |
| 106 | |
| 107 | cooling-maps { |
| 108 | }; |
| 109 | }; |
| 110 | }; |
| 111 | |
| 112 | reboot { |
| 113 | compatible = "syscon-reboot"; |
| 114 | regmap = <&rcc>; |
| 115 | offset = <0x404>; |
| 116 | mask = <0x1>; |
| 117 | }; |
| 118 | |
Patrick Delaunay | 5059914 | 2018-07-09 15:17:19 +0200 | [diff] [blame] | 119 | soc { |
| 120 | compatible = "simple-bus"; |
| 121 | #address-cells = <1>; |
| 122 | #size-cells = <1>; |
| 123 | interrupt-parent = <&intc>; |
| 124 | ranges; |
| 125 | |
| 126 | timers2: timer@40000000 { |
| 127 | #address-cells = <1>; |
| 128 | #size-cells = <0>; |
| 129 | compatible = "st,stm32-timers"; |
| 130 | reg = <0x40000000 0x400>; |
| 131 | clocks = <&rcc TIM2_K>; |
| 132 | clock-names = "int"; |
Patrick Delaunay | a370530 | 2019-07-11 11:15:28 +0200 | [diff] [blame] | 133 | dmas = <&dmamux1 18 0x400 0x1>, |
| 134 | <&dmamux1 19 0x400 0x1>, |
| 135 | <&dmamux1 20 0x400 0x1>, |
| 136 | <&dmamux1 21 0x400 0x1>, |
| 137 | <&dmamux1 22 0x400 0x1>; |
| 138 | dma-names = "ch1", "ch2", "ch3", "ch4", "up"; |
Patrick Delaunay | 5059914 | 2018-07-09 15:17:19 +0200 | [diff] [blame] | 139 | status = "disabled"; |
| 140 | |
| 141 | pwm { |
| 142 | compatible = "st,stm32-pwm"; |
| 143 | status = "disabled"; |
| 144 | }; |
| 145 | |
| 146 | timer@1 { |
| 147 | compatible = "st,stm32h7-timer-trigger"; |
| 148 | reg = <1>; |
| 149 | status = "disabled"; |
| 150 | }; |
| 151 | }; |
| 152 | |
| 153 | timers3: timer@40001000 { |
| 154 | #address-cells = <1>; |
| 155 | #size-cells = <0>; |
| 156 | compatible = "st,stm32-timers"; |
| 157 | reg = <0x40001000 0x400>; |
| 158 | clocks = <&rcc TIM3_K>; |
| 159 | clock-names = "int"; |
Patrick Delaunay | a370530 | 2019-07-11 11:15:28 +0200 | [diff] [blame] | 160 | dmas = <&dmamux1 23 0x400 0x1>, |
| 161 | <&dmamux1 24 0x400 0x1>, |
| 162 | <&dmamux1 25 0x400 0x1>, |
| 163 | <&dmamux1 26 0x400 0x1>, |
| 164 | <&dmamux1 27 0x400 0x1>, |
| 165 | <&dmamux1 28 0x400 0x1>; |
| 166 | dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; |
Patrick Delaunay | 5059914 | 2018-07-09 15:17:19 +0200 | [diff] [blame] | 167 | status = "disabled"; |
| 168 | |
| 169 | pwm { |
| 170 | compatible = "st,stm32-pwm"; |
| 171 | status = "disabled"; |
| 172 | }; |
| 173 | |
| 174 | timer@2 { |
| 175 | compatible = "st,stm32h7-timer-trigger"; |
| 176 | reg = <2>; |
| 177 | status = "disabled"; |
| 178 | }; |
| 179 | }; |
| 180 | |
| 181 | timers4: timer@40002000 { |
| 182 | #address-cells = <1>; |
| 183 | #size-cells = <0>; |
| 184 | compatible = "st,stm32-timers"; |
| 185 | reg = <0x40002000 0x400>; |
| 186 | clocks = <&rcc TIM4_K>; |
| 187 | clock-names = "int"; |
Patrick Delaunay | a370530 | 2019-07-11 11:15:28 +0200 | [diff] [blame] | 188 | dmas = <&dmamux1 29 0x400 0x1>, |
| 189 | <&dmamux1 30 0x400 0x1>, |
| 190 | <&dmamux1 31 0x400 0x1>, |
| 191 | <&dmamux1 32 0x400 0x1>; |
| 192 | dma-names = "ch1", "ch2", "ch3", "ch4"; |
Patrick Delaunay | 5059914 | 2018-07-09 15:17:19 +0200 | [diff] [blame] | 193 | status = "disabled"; |
| 194 | |
| 195 | pwm { |
| 196 | compatible = "st,stm32-pwm"; |
| 197 | status = "disabled"; |
| 198 | }; |
| 199 | |
| 200 | timer@3 { |
| 201 | compatible = "st,stm32h7-timer-trigger"; |
| 202 | reg = <3>; |
| 203 | status = "disabled"; |
| 204 | }; |
| 205 | }; |
| 206 | |
| 207 | timers5: timer@40003000 { |
| 208 | #address-cells = <1>; |
| 209 | #size-cells = <0>; |
| 210 | compatible = "st,stm32-timers"; |
| 211 | reg = <0x40003000 0x400>; |
| 212 | clocks = <&rcc TIM5_K>; |
| 213 | clock-names = "int"; |
Patrick Delaunay | a370530 | 2019-07-11 11:15:28 +0200 | [diff] [blame] | 214 | dmas = <&dmamux1 55 0x400 0x1>, |
| 215 | <&dmamux1 56 0x400 0x1>, |
| 216 | <&dmamux1 57 0x400 0x1>, |
| 217 | <&dmamux1 58 0x400 0x1>, |
| 218 | <&dmamux1 59 0x400 0x1>, |
| 219 | <&dmamux1 60 0x400 0x1>; |
| 220 | dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; |
Patrick Delaunay | 5059914 | 2018-07-09 15:17:19 +0200 | [diff] [blame] | 221 | status = "disabled"; |
| 222 | |
| 223 | pwm { |
| 224 | compatible = "st,stm32-pwm"; |
| 225 | status = "disabled"; |
| 226 | }; |
| 227 | |
| 228 | timer@4 { |
| 229 | compatible = "st,stm32h7-timer-trigger"; |
| 230 | reg = <4>; |
| 231 | status = "disabled"; |
| 232 | }; |
| 233 | }; |
| 234 | |
| 235 | timers6: timer@40004000 { |
| 236 | #address-cells = <1>; |
| 237 | #size-cells = <0>; |
| 238 | compatible = "st,stm32-timers"; |
| 239 | reg = <0x40004000 0x400>; |
| 240 | clocks = <&rcc TIM6_K>; |
| 241 | clock-names = "int"; |
Patrick Delaunay | a370530 | 2019-07-11 11:15:28 +0200 | [diff] [blame] | 242 | dmas = <&dmamux1 69 0x400 0x1>; |
| 243 | dma-names = "up"; |
Patrick Delaunay | 5059914 | 2018-07-09 15:17:19 +0200 | [diff] [blame] | 244 | status = "disabled"; |
| 245 | |
| 246 | timer@5 { |
| 247 | compatible = "st,stm32h7-timer-trigger"; |
| 248 | reg = <5>; |
| 249 | status = "disabled"; |
| 250 | }; |
| 251 | }; |
| 252 | |
| 253 | timers7: timer@40005000 { |
| 254 | #address-cells = <1>; |
| 255 | #size-cells = <0>; |
| 256 | compatible = "st,stm32-timers"; |
| 257 | reg = <0x40005000 0x400>; |
| 258 | clocks = <&rcc TIM7_K>; |
| 259 | clock-names = "int"; |
Patrick Delaunay | a370530 | 2019-07-11 11:15:28 +0200 | [diff] [blame] | 260 | dmas = <&dmamux1 70 0x400 0x1>; |
| 261 | dma-names = "up"; |
Patrick Delaunay | 5059914 | 2018-07-09 15:17:19 +0200 | [diff] [blame] | 262 | status = "disabled"; |
| 263 | |
| 264 | timer@6 { |
| 265 | compatible = "st,stm32h7-timer-trigger"; |
| 266 | reg = <6>; |
| 267 | status = "disabled"; |
| 268 | }; |
| 269 | }; |
| 270 | |
| 271 | timers12: timer@40006000 { |
| 272 | #address-cells = <1>; |
| 273 | #size-cells = <0>; |
| 274 | compatible = "st,stm32-timers"; |
| 275 | reg = <0x40006000 0x400>; |
| 276 | clocks = <&rcc TIM12_K>; |
| 277 | clock-names = "int"; |
| 278 | status = "disabled"; |
| 279 | |
| 280 | pwm { |
| 281 | compatible = "st,stm32-pwm"; |
| 282 | status = "disabled"; |
| 283 | }; |
| 284 | |
| 285 | timer@11 { |
| 286 | compatible = "st,stm32h7-timer-trigger"; |
| 287 | reg = <11>; |
| 288 | status = "disabled"; |
| 289 | }; |
| 290 | }; |
| 291 | |
| 292 | timers13: timer@40007000 { |
| 293 | #address-cells = <1>; |
| 294 | #size-cells = <0>; |
| 295 | compatible = "st,stm32-timers"; |
| 296 | reg = <0x40007000 0x400>; |
| 297 | clocks = <&rcc TIM13_K>; |
| 298 | clock-names = "int"; |
| 299 | status = "disabled"; |
| 300 | |
| 301 | pwm { |
| 302 | compatible = "st,stm32-pwm"; |
| 303 | status = "disabled"; |
| 304 | }; |
| 305 | |
| 306 | timer@12 { |
| 307 | compatible = "st,stm32h7-timer-trigger"; |
| 308 | reg = <12>; |
| 309 | status = "disabled"; |
| 310 | }; |
| 311 | }; |
| 312 | |
| 313 | timers14: timer@40008000 { |
| 314 | #address-cells = <1>; |
| 315 | #size-cells = <0>; |
| 316 | compatible = "st,stm32-timers"; |
| 317 | reg = <0x40008000 0x400>; |
| 318 | clocks = <&rcc TIM14_K>; |
| 319 | clock-names = "int"; |
| 320 | status = "disabled"; |
| 321 | |
| 322 | pwm { |
| 323 | compatible = "st,stm32-pwm"; |
| 324 | status = "disabled"; |
| 325 | }; |
| 326 | |
| 327 | timer@13 { |
| 328 | compatible = "st,stm32h7-timer-trigger"; |
| 329 | reg = <13>; |
| 330 | status = "disabled"; |
| 331 | }; |
| 332 | }; |
| 333 | |
| 334 | lptimer1: timer@40009000 { |
| 335 | #address-cells = <1>; |
| 336 | #size-cells = <0>; |
| 337 | compatible = "st,stm32-lptimer"; |
| 338 | reg = <0x40009000 0x400>; |
| 339 | clocks = <&rcc LPTIM1_K>; |
| 340 | clock-names = "mux"; |
| 341 | status = "disabled"; |
| 342 | |
| 343 | pwm { |
| 344 | compatible = "st,stm32-pwm-lp"; |
| 345 | #pwm-cells = <3>; |
| 346 | status = "disabled"; |
| 347 | }; |
| 348 | |
| 349 | trigger@0 { |
| 350 | compatible = "st,stm32-lptimer-trigger"; |
| 351 | reg = <0>; |
| 352 | status = "disabled"; |
| 353 | }; |
| 354 | |
| 355 | counter { |
| 356 | compatible = "st,stm32-lptimer-counter"; |
| 357 | status = "disabled"; |
| 358 | }; |
| 359 | }; |
| 360 | |
Patrice Chotard | 00442d0 | 2019-02-12 16:50:38 +0100 | [diff] [blame] | 361 | spi2: spi@4000b000 { |
| 362 | #address-cells = <1>; |
| 363 | #size-cells = <0>; |
| 364 | compatible = "st,stm32h7-spi"; |
| 365 | reg = <0x4000b000 0x400>; |
| 366 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; |
| 367 | clocks = <&rcc SPI2_K>; |
| 368 | resets = <&rcc SPI2_R>; |
| 369 | dmas = <&dmamux1 39 0x400 0x05>, |
| 370 | <&dmamux1 40 0x400 0x05>; |
| 371 | dma-names = "rx", "tx"; |
| 372 | status = "disabled"; |
| 373 | }; |
| 374 | |
| 375 | spi3: spi@4000c000 { |
| 376 | #address-cells = <1>; |
| 377 | #size-cells = <0>; |
| 378 | compatible = "st,stm32h7-spi"; |
| 379 | reg = <0x4000c000 0x400>; |
| 380 | interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; |
| 381 | clocks = <&rcc SPI3_K>; |
| 382 | resets = <&rcc SPI3_R>; |
| 383 | dmas = <&dmamux1 61 0x400 0x05>, |
| 384 | <&dmamux1 62 0x400 0x05>; |
| 385 | dma-names = "rx", "tx"; |
| 386 | status = "disabled"; |
| 387 | }; |
| 388 | |
Patrick Delaunay | a370530 | 2019-07-11 11:15:28 +0200 | [diff] [blame] | 389 | spdifrx: audio-controller@4000d000 { |
| 390 | compatible = "st,stm32h7-spdifrx"; |
| 391 | #sound-dai-cells = <0>; |
| 392 | reg = <0x4000d000 0x400>; |
| 393 | clocks = <&rcc SPDIF_K>; |
| 394 | clock-names = "kclk"; |
| 395 | interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; |
| 396 | dmas = <&dmamux1 93 0x400 0x01>, |
| 397 | <&dmamux1 94 0x400 0x01>; |
| 398 | dma-names = "rx", "rx-ctrl"; |
| 399 | status = "disabled"; |
| 400 | }; |
| 401 | |
Patrick Delaunay | 5059914 | 2018-07-09 15:17:19 +0200 | [diff] [blame] | 402 | usart2: serial@4000e000 { |
| 403 | compatible = "st,stm32h7-uart"; |
| 404 | reg = <0x4000e000 0x400>; |
| 405 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; |
| 406 | clocks = <&rcc USART2_K>; |
| 407 | status = "disabled"; |
| 408 | }; |
| 409 | |
| 410 | usart3: serial@4000f000 { |
| 411 | compatible = "st,stm32h7-uart"; |
| 412 | reg = <0x4000f000 0x400>; |
| 413 | interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; |
| 414 | clocks = <&rcc USART3_K>; |
| 415 | status = "disabled"; |
| 416 | }; |
| 417 | |
| 418 | uart4: serial@40010000 { |
| 419 | compatible = "st,stm32h7-uart"; |
| 420 | reg = <0x40010000 0x400>; |
| 421 | interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; |
| 422 | clocks = <&rcc UART4_K>; |
| 423 | status = "disabled"; |
| 424 | }; |
| 425 | |
| 426 | uart5: serial@40011000 { |
| 427 | compatible = "st,stm32h7-uart"; |
| 428 | reg = <0x40011000 0x400>; |
| 429 | interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; |
| 430 | clocks = <&rcc UART5_K>; |
| 431 | status = "disabled"; |
| 432 | }; |
| 433 | |
| 434 | i2c1: i2c@40012000 { |
| 435 | compatible = "st,stm32f7-i2c"; |
| 436 | reg = <0x40012000 0x400>; |
| 437 | interrupt-names = "event", "error"; |
| 438 | interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, |
| 439 | <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; |
| 440 | clocks = <&rcc I2C1_K>; |
| 441 | resets = <&rcc I2C1_R>; |
| 442 | #address-cells = <1>; |
| 443 | #size-cells = <0>; |
| 444 | status = "disabled"; |
| 445 | }; |
| 446 | |
| 447 | i2c2: i2c@40013000 { |
| 448 | compatible = "st,stm32f7-i2c"; |
| 449 | reg = <0x40013000 0x400>; |
| 450 | interrupt-names = "event", "error"; |
| 451 | interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, |
| 452 | <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; |
| 453 | clocks = <&rcc I2C2_K>; |
| 454 | resets = <&rcc I2C2_R>; |
| 455 | #address-cells = <1>; |
| 456 | #size-cells = <0>; |
| 457 | status = "disabled"; |
| 458 | }; |
| 459 | |
| 460 | i2c3: i2c@40014000 { |
| 461 | compatible = "st,stm32f7-i2c"; |
| 462 | reg = <0x40014000 0x400>; |
| 463 | interrupt-names = "event", "error"; |
| 464 | interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, |
| 465 | <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; |
| 466 | clocks = <&rcc I2C3_K>; |
| 467 | resets = <&rcc I2C3_R>; |
| 468 | #address-cells = <1>; |
| 469 | #size-cells = <0>; |
| 470 | status = "disabled"; |
| 471 | }; |
| 472 | |
| 473 | i2c5: i2c@40015000 { |
| 474 | compatible = "st,stm32f7-i2c"; |
| 475 | reg = <0x40015000 0x400>; |
| 476 | interrupt-names = "event", "error"; |
| 477 | interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, |
| 478 | <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; |
| 479 | clocks = <&rcc I2C5_K>; |
| 480 | resets = <&rcc I2C5_R>; |
| 481 | #address-cells = <1>; |
| 482 | #size-cells = <0>; |
| 483 | status = "disabled"; |
| 484 | }; |
| 485 | |
| 486 | cec: cec@40016000 { |
| 487 | compatible = "st,stm32-cec"; |
| 488 | reg = <0x40016000 0x400>; |
| 489 | interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; |
| 490 | clocks = <&rcc CEC_K>, <&clk_lse>; |
| 491 | clock-names = "cec", "hdmi-cec"; |
| 492 | status = "disabled"; |
| 493 | }; |
| 494 | |
| 495 | dac: dac@40017000 { |
| 496 | compatible = "st,stm32h7-dac-core"; |
| 497 | reg = <0x40017000 0x400>; |
| 498 | clocks = <&rcc DAC12>; |
| 499 | clock-names = "pclk"; |
| 500 | #address-cells = <1>; |
| 501 | #size-cells = <0>; |
| 502 | status = "disabled"; |
| 503 | |
| 504 | dac1: dac@1 { |
| 505 | compatible = "st,stm32-dac"; |
| 506 | #io-channels-cells = <1>; |
| 507 | reg = <1>; |
| 508 | status = "disabled"; |
| 509 | }; |
| 510 | |
| 511 | dac2: dac@2 { |
| 512 | compatible = "st,stm32-dac"; |
| 513 | #io-channels-cells = <1>; |
| 514 | reg = <2>; |
| 515 | status = "disabled"; |
| 516 | }; |
| 517 | }; |
| 518 | |
| 519 | uart7: serial@40018000 { |
| 520 | compatible = "st,stm32h7-uart"; |
| 521 | reg = <0x40018000 0x400>; |
| 522 | interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; |
| 523 | clocks = <&rcc UART7_K>; |
| 524 | status = "disabled"; |
| 525 | }; |
| 526 | |
| 527 | uart8: serial@40019000 { |
| 528 | compatible = "st,stm32h7-uart"; |
| 529 | reg = <0x40019000 0x400>; |
| 530 | interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; |
| 531 | clocks = <&rcc UART8_K>; |
| 532 | status = "disabled"; |
| 533 | }; |
| 534 | |
| 535 | timers1: timer@44000000 { |
| 536 | #address-cells = <1>; |
| 537 | #size-cells = <0>; |
| 538 | compatible = "st,stm32-timers"; |
| 539 | reg = <0x44000000 0x400>; |
| 540 | clocks = <&rcc TIM1_K>; |
| 541 | clock-names = "int"; |
Patrick Delaunay | a370530 | 2019-07-11 11:15:28 +0200 | [diff] [blame] | 542 | dmas = <&dmamux1 11 0x400 0x1>, |
| 543 | <&dmamux1 12 0x400 0x1>, |
| 544 | <&dmamux1 13 0x400 0x1>, |
| 545 | <&dmamux1 14 0x400 0x1>, |
| 546 | <&dmamux1 15 0x400 0x1>, |
| 547 | <&dmamux1 16 0x400 0x1>, |
| 548 | <&dmamux1 17 0x400 0x1>; |
| 549 | dma-names = "ch1", "ch2", "ch3", "ch4", |
| 550 | "up", "trig", "com"; |
Patrick Delaunay | 5059914 | 2018-07-09 15:17:19 +0200 | [diff] [blame] | 551 | status = "disabled"; |
| 552 | |
| 553 | pwm { |
| 554 | compatible = "st,stm32-pwm"; |
| 555 | status = "disabled"; |
| 556 | }; |
| 557 | |
| 558 | timer@0 { |
| 559 | compatible = "st,stm32h7-timer-trigger"; |
| 560 | reg = <0>; |
| 561 | status = "disabled"; |
| 562 | }; |
| 563 | }; |
| 564 | |
| 565 | timers8: timer@44001000 { |
| 566 | #address-cells = <1>; |
| 567 | #size-cells = <0>; |
| 568 | compatible = "st,stm32-timers"; |
| 569 | reg = <0x44001000 0x400>; |
| 570 | clocks = <&rcc TIM8_K>; |
| 571 | clock-names = "int"; |
Patrick Delaunay | a370530 | 2019-07-11 11:15:28 +0200 | [diff] [blame] | 572 | dmas = <&dmamux1 47 0x400 0x1>, |
| 573 | <&dmamux1 48 0x400 0x1>, |
| 574 | <&dmamux1 49 0x400 0x1>, |
| 575 | <&dmamux1 50 0x400 0x1>, |
| 576 | <&dmamux1 51 0x400 0x1>, |
| 577 | <&dmamux1 52 0x400 0x1>, |
| 578 | <&dmamux1 53 0x400 0x1>; |
| 579 | dma-names = "ch1", "ch2", "ch3", "ch4", |
| 580 | "up", "trig", "com"; |
Patrick Delaunay | 5059914 | 2018-07-09 15:17:19 +0200 | [diff] [blame] | 581 | status = "disabled"; |
| 582 | |
| 583 | pwm { |
| 584 | compatible = "st,stm32-pwm"; |
| 585 | status = "disabled"; |
| 586 | }; |
| 587 | |
| 588 | timer@7 { |
| 589 | compatible = "st,stm32h7-timer-trigger"; |
| 590 | reg = <7>; |
| 591 | status = "disabled"; |
| 592 | }; |
| 593 | }; |
| 594 | |
| 595 | usart6: serial@44003000 { |
| 596 | compatible = "st,stm32h7-uart"; |
| 597 | reg = <0x44003000 0x400>; |
| 598 | interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; |
| 599 | clocks = <&rcc USART6_K>; |
| 600 | status = "disabled"; |
| 601 | }; |
| 602 | |
Patrice Chotard | 00442d0 | 2019-02-12 16:50:38 +0100 | [diff] [blame] | 603 | spi1: spi@44004000 { |
| 604 | #address-cells = <1>; |
| 605 | #size-cells = <0>; |
| 606 | compatible = "st,stm32h7-spi"; |
| 607 | reg = <0x44004000 0x400>; |
| 608 | interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; |
| 609 | clocks = <&rcc SPI1_K>; |
| 610 | resets = <&rcc SPI1_R>; |
| 611 | dmas = <&dmamux1 37 0x400 0x05>, |
| 612 | <&dmamux1 38 0x400 0x05>; |
| 613 | dma-names = "rx", "tx"; |
| 614 | status = "disabled"; |
| 615 | }; |
| 616 | |
| 617 | spi4: spi@44005000 { |
| 618 | #address-cells = <1>; |
| 619 | #size-cells = <0>; |
| 620 | compatible = "st,stm32h7-spi"; |
| 621 | reg = <0x44005000 0x400>; |
| 622 | interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; |
| 623 | clocks = <&rcc SPI4_K>; |
| 624 | resets = <&rcc SPI4_R>; |
| 625 | dmas = <&dmamux1 83 0x400 0x05>, |
| 626 | <&dmamux1 84 0x400 0x05>; |
| 627 | dma-names = "rx", "tx"; |
| 628 | status = "disabled"; |
| 629 | }; |
| 630 | |
Patrick Delaunay | 5059914 | 2018-07-09 15:17:19 +0200 | [diff] [blame] | 631 | timers15: timer@44006000 { |
| 632 | #address-cells = <1>; |
| 633 | #size-cells = <0>; |
| 634 | compatible = "st,stm32-timers"; |
| 635 | reg = <0x44006000 0x400>; |
| 636 | clocks = <&rcc TIM15_K>; |
| 637 | clock-names = "int"; |
Patrick Delaunay | a370530 | 2019-07-11 11:15:28 +0200 | [diff] [blame] | 638 | dmas = <&dmamux1 105 0x400 0x1>, |
| 639 | <&dmamux1 106 0x400 0x1>, |
| 640 | <&dmamux1 107 0x400 0x1>, |
| 641 | <&dmamux1 108 0x400 0x1>; |
| 642 | dma-names = "ch1", "up", "trig", "com"; |
Patrick Delaunay | 5059914 | 2018-07-09 15:17:19 +0200 | [diff] [blame] | 643 | status = "disabled"; |
| 644 | |
| 645 | pwm { |
| 646 | compatible = "st,stm32-pwm"; |
| 647 | status = "disabled"; |
| 648 | }; |
| 649 | |
| 650 | timer@14 { |
| 651 | compatible = "st,stm32h7-timer-trigger"; |
| 652 | reg = <14>; |
| 653 | status = "disabled"; |
| 654 | }; |
| 655 | }; |
| 656 | |
| 657 | timers16: timer@44007000 { |
| 658 | #address-cells = <1>; |
| 659 | #size-cells = <0>; |
| 660 | compatible = "st,stm32-timers"; |
| 661 | reg = <0x44007000 0x400>; |
| 662 | clocks = <&rcc TIM16_K>; |
| 663 | clock-names = "int"; |
Patrick Delaunay | a370530 | 2019-07-11 11:15:28 +0200 | [diff] [blame] | 664 | dmas = <&dmamux1 109 0x400 0x1>, |
| 665 | <&dmamux1 110 0x400 0x1>; |
| 666 | dma-names = "ch1", "up"; |
Patrick Delaunay | 5059914 | 2018-07-09 15:17:19 +0200 | [diff] [blame] | 667 | status = "disabled"; |
| 668 | |
| 669 | pwm { |
| 670 | compatible = "st,stm32-pwm"; |
| 671 | status = "disabled"; |
| 672 | }; |
| 673 | timer@15 { |
| 674 | compatible = "st,stm32h7-timer-trigger"; |
| 675 | reg = <15>; |
| 676 | status = "disabled"; |
| 677 | }; |
| 678 | }; |
| 679 | |
| 680 | timers17: timer@44008000 { |
| 681 | #address-cells = <1>; |
| 682 | #size-cells = <0>; |
| 683 | compatible = "st,stm32-timers"; |
| 684 | reg = <0x44008000 0x400>; |
| 685 | clocks = <&rcc TIM17_K>; |
| 686 | clock-names = "int"; |
Patrick Delaunay | a370530 | 2019-07-11 11:15:28 +0200 | [diff] [blame] | 687 | dmas = <&dmamux1 111 0x400 0x1>, |
| 688 | <&dmamux1 112 0x400 0x1>; |
| 689 | dma-names = "ch1", "up"; |
Patrick Delaunay | 5059914 | 2018-07-09 15:17:19 +0200 | [diff] [blame] | 690 | status = "disabled"; |
| 691 | |
| 692 | pwm { |
| 693 | compatible = "st,stm32-pwm"; |
| 694 | status = "disabled"; |
| 695 | }; |
| 696 | |
| 697 | timer@16 { |
| 698 | compatible = "st,stm32h7-timer-trigger"; |
| 699 | reg = <16>; |
| 700 | status = "disabled"; |
| 701 | }; |
Patrice Chotard | 00442d0 | 2019-02-12 16:50:38 +0100 | [diff] [blame] | 702 | }; |
| 703 | |
| 704 | spi5: spi@44009000 { |
| 705 | #address-cells = <1>; |
| 706 | #size-cells = <0>; |
| 707 | compatible = "st,stm32h7-spi"; |
| 708 | reg = <0x44009000 0x400>; |
| 709 | interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; |
| 710 | clocks = <&rcc SPI5_K>; |
| 711 | resets = <&rcc SPI5_R>; |
| 712 | dmas = <&dmamux1 85 0x400 0x05>, |
| 713 | <&dmamux1 86 0x400 0x05>; |
| 714 | dma-names = "rx", "tx"; |
| 715 | status = "disabled"; |
| 716 | }; |
| 717 | |
| 718 | dfsdm: dfsdm@4400d000 { |
| 719 | compatible = "st,stm32mp1-dfsdm"; |
| 720 | reg = <0x4400d000 0x800>; |
| 721 | clocks = <&rcc DFSDM_K>; |
| 722 | clock-names = "dfsdm"; |
| 723 | #address-cells = <1>; |
| 724 | #size-cells = <0>; |
| 725 | status = "disabled"; |
| 726 | |
| 727 | dfsdm0: filter@0 { |
| 728 | compatible = "st,stm32-dfsdm-adc"; |
| 729 | #io-channel-cells = <1>; |
| 730 | reg = <0>; |
| 731 | interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; |
| 732 | dmas = <&dmamux1 101 0x400 0x01>; |
| 733 | dma-names = "rx"; |
| 734 | status = "disabled"; |
| 735 | }; |
| 736 | |
| 737 | dfsdm1: filter@1 { |
| 738 | compatible = "st,stm32-dfsdm-adc"; |
| 739 | #io-channel-cells = <1>; |
| 740 | reg = <1>; |
| 741 | interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; |
| 742 | dmas = <&dmamux1 102 0x400 0x01>; |
| 743 | dma-names = "rx"; |
| 744 | status = "disabled"; |
| 745 | }; |
| 746 | |
| 747 | dfsdm2: filter@2 { |
| 748 | compatible = "st,stm32-dfsdm-adc"; |
| 749 | #io-channel-cells = <1>; |
| 750 | reg = <2>; |
| 751 | interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; |
| 752 | dmas = <&dmamux1 103 0x400 0x01>; |
| 753 | dma-names = "rx"; |
| 754 | status = "disabled"; |
| 755 | }; |
| 756 | |
| 757 | dfsdm3: filter@3 { |
| 758 | compatible = "st,stm32-dfsdm-adc"; |
| 759 | #io-channel-cells = <1>; |
| 760 | reg = <3>; |
| 761 | interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; |
| 762 | dmas = <&dmamux1 104 0x400 0x01>; |
| 763 | dma-names = "rx"; |
| 764 | status = "disabled"; |
| 765 | }; |
| 766 | |
| 767 | dfsdm4: filter@4 { |
| 768 | compatible = "st,stm32-dfsdm-adc"; |
| 769 | #io-channel-cells = <1>; |
| 770 | reg = <4>; |
| 771 | interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; |
| 772 | dmas = <&dmamux1 91 0x400 0x01>; |
| 773 | dma-names = "rx"; |
| 774 | status = "disabled"; |
| 775 | }; |
| 776 | |
| 777 | dfsdm5: filter@5 { |
| 778 | compatible = "st,stm32-dfsdm-adc"; |
| 779 | #io-channel-cells = <1>; |
| 780 | reg = <5>; |
| 781 | interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; |
| 782 | dmas = <&dmamux1 92 0x400 0x01>; |
| 783 | dma-names = "rx"; |
| 784 | status = "disabled"; |
| 785 | }; |
Patrick Delaunay | 5059914 | 2018-07-09 15:17:19 +0200 | [diff] [blame] | 786 | }; |
| 787 | |
Patrice Chotard | 00442d0 | 2019-02-12 16:50:38 +0100 | [diff] [blame] | 788 | m_can1: can@4400e000 { |
| 789 | compatible = "bosch,m_can"; |
Patrick Delaunay | a370530 | 2019-07-11 11:15:28 +0200 | [diff] [blame] | 790 | reg = <0x4400e000 0x400>, <0x44011000 0x1400>; |
Patrice Chotard | 00442d0 | 2019-02-12 16:50:38 +0100 | [diff] [blame] | 791 | reg-names = "m_can", "message_ram"; |
| 792 | interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, |
| 793 | <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; |
| 794 | interrupt-names = "int0", "int1"; |
| 795 | clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; |
| 796 | clock-names = "hclk", "cclk"; |
Patrick Delaunay | a370530 | 2019-07-11 11:15:28 +0200 | [diff] [blame] | 797 | bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>; |
Patrice Chotard | 00442d0 | 2019-02-12 16:50:38 +0100 | [diff] [blame] | 798 | status = "disabled"; |
| 799 | }; |
| 800 | |
| 801 | m_can2: can@4400f000 { |
| 802 | compatible = "bosch,m_can"; |
| 803 | reg = <0x4400f000 0x400>, <0x44011000 0x2800>; |
| 804 | reg-names = "m_can", "message_ram"; |
| 805 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, |
| 806 | <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; |
| 807 | interrupt-names = "int0", "int1"; |
| 808 | clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; |
| 809 | clock-names = "hclk", "cclk"; |
| 810 | bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>; |
| 811 | status = "disabled"; |
| 812 | }; |
| 813 | |
Patrick Delaunay | 5059914 | 2018-07-09 15:17:19 +0200 | [diff] [blame] | 814 | dma1: dma@48000000 { |
| 815 | compatible = "st,stm32-dma"; |
| 816 | reg = <0x48000000 0x400>; |
| 817 | interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, |
| 818 | <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, |
| 819 | <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, |
| 820 | <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, |
| 821 | <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, |
| 822 | <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, |
| 823 | <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, |
| 824 | <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; |
| 825 | clocks = <&rcc DMA1>; |
| 826 | #dma-cells = <4>; |
| 827 | st,mem2mem; |
| 828 | dma-requests = <8>; |
| 829 | }; |
| 830 | |
| 831 | dma2: dma@48001000 { |
| 832 | compatible = "st,stm32-dma"; |
| 833 | reg = <0x48001000 0x400>; |
| 834 | interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, |
| 835 | <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, |
| 836 | <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, |
| 837 | <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, |
| 838 | <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>, |
| 839 | <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, |
| 840 | <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, |
| 841 | <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; |
| 842 | clocks = <&rcc DMA2>; |
| 843 | #dma-cells = <4>; |
| 844 | st,mem2mem; |
| 845 | dma-requests = <8>; |
| 846 | }; |
| 847 | |
| 848 | dmamux1: dma-router@48002000 { |
| 849 | compatible = "st,stm32h7-dmamux"; |
| 850 | reg = <0x48002000 0x1c>; |
| 851 | #dma-cells = <3>; |
| 852 | dma-requests = <128>; |
| 853 | dma-masters = <&dma1 &dma2>; |
| 854 | dma-channels = <16>; |
| 855 | clocks = <&rcc DMAMUX>; |
| 856 | }; |
| 857 | |
Patrice Chotard | b5c87a4 | 2018-08-06 09:54:04 +0200 | [diff] [blame] | 858 | adc: adc@48003000 { |
| 859 | compatible = "st,stm32mp1-adc-core"; |
| 860 | reg = <0x48003000 0x400>; |
| 861 | interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, |
| 862 | <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; |
| 863 | clocks = <&rcc ADC12>, <&rcc ADC12_K>; |
| 864 | clock-names = "bus", "adc"; |
| 865 | interrupt-controller; |
| 866 | #interrupt-cells = <1>; |
| 867 | #address-cells = <1>; |
| 868 | #size-cells = <0>; |
| 869 | status = "disabled"; |
| 870 | |
| 871 | adc1: adc@0 { |
| 872 | compatible = "st,stm32mp1-adc"; |
| 873 | #io-channel-cells = <1>; |
| 874 | reg = <0x0>; |
| 875 | interrupt-parent = <&adc>; |
| 876 | interrupts = <0>; |
Patrice Chotard | 00442d0 | 2019-02-12 16:50:38 +0100 | [diff] [blame] | 877 | dmas = <&dmamux1 9 0x400 0x01>; |
| 878 | dma-names = "rx"; |
Patrice Chotard | b5c87a4 | 2018-08-06 09:54:04 +0200 | [diff] [blame] | 879 | status = "disabled"; |
| 880 | }; |
| 881 | |
| 882 | adc2: adc@100 { |
| 883 | compatible = "st,stm32mp1-adc"; |
| 884 | #io-channel-cells = <1>; |
| 885 | reg = <0x100>; |
| 886 | interrupt-parent = <&adc>; |
| 887 | interrupts = <1>; |
Patrice Chotard | 00442d0 | 2019-02-12 16:50:38 +0100 | [diff] [blame] | 888 | dmas = <&dmamux1 10 0x400 0x01>; |
| 889 | dma-names = "rx"; |
Patrice Chotard | b5c87a4 | 2018-08-06 09:54:04 +0200 | [diff] [blame] | 890 | status = "disabled"; |
| 891 | }; |
| 892 | }; |
| 893 | |
Patrick Delaunay | 5059914 | 2018-07-09 15:17:19 +0200 | [diff] [blame] | 894 | sdmmc3: sdmmc@48004000 { |
Patrick Delaunay | a370530 | 2019-07-11 11:15:28 +0200 | [diff] [blame] | 895 | compatible = "arm,pl18x", "arm,primecell"; |
| 896 | arm,primecell-periphid = <0x10153180>; |
| 897 | reg = <0x48004000 0x400>; |
| 898 | reg-names = "sdmmc"; |
Patrick Delaunay | 5059914 | 2018-07-09 15:17:19 +0200 | [diff] [blame] | 899 | interrupts = <GIC_SPI 137 IRQ_TYPE_NONE>; |
| 900 | clocks = <&rcc SDMMC3_K>; |
Patrick Delaunay | a370530 | 2019-07-11 11:15:28 +0200 | [diff] [blame] | 901 | clock-names = "apb_pclk"; |
Patrick Delaunay | 5059914 | 2018-07-09 15:17:19 +0200 | [diff] [blame] | 902 | resets = <&rcc SDMMC3_R>; |
Patrick Delaunay | 5059914 | 2018-07-09 15:17:19 +0200 | [diff] [blame] | 903 | cap-sd-highspeed; |
| 904 | cap-mmc-highspeed; |
| 905 | max-frequency = <120000000>; |
| 906 | status = "disabled"; |
| 907 | }; |
| 908 | |
Patrice Chotard | 18cb6f5 | 2018-08-10 17:12:11 +0200 | [diff] [blame] | 909 | usbotg_hs: usb-otg@49000000 { |
Patrick Delaunay | a370530 | 2019-07-11 11:15:28 +0200 | [diff] [blame] | 910 | compatible = "snps,dwc2"; |
Patrice Chotard | 18cb6f5 | 2018-08-10 17:12:11 +0200 | [diff] [blame] | 911 | reg = <0x49000000 0x10000>; |
| 912 | clocks = <&rcc USBO_K>; |
| 913 | clock-names = "otg"; |
| 914 | resets = <&rcc USBO_R>; |
| 915 | reset-names = "dwc2"; |
| 916 | interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; |
| 917 | g-rx-fifo-size = <256>; |
| 918 | g-np-tx-fifo-size = <32>; |
| 919 | g-tx-fifo-size = <128 128 64 64 64 64 32 32>; |
| 920 | dr_mode = "otg"; |
Patrick Delaunay | 6ba88cd | 2019-03-29 15:42:11 +0100 | [diff] [blame] | 921 | usb33d-supply = <&usb33>; |
Patrice Chotard | 18cb6f5 | 2018-08-10 17:12:11 +0200 | [diff] [blame] | 922 | status = "disabled"; |
| 923 | }; |
| 924 | |
Benjamin Gaignard | 7761112 | 2018-11-27 13:49:52 +0100 | [diff] [blame] | 925 | hwspinlock: hwspinlock@4c000000 { |
| 926 | compatible = "st,stm32-hwspinlock"; |
| 927 | #hwlock-cells = <1>; |
| 928 | reg = <0x4c000000 0x400>; |
| 929 | clocks = <&rcc HSEM>; |
| 930 | clock-names = "hwspinlock"; |
Benjamin Gaignard | 7761112 | 2018-11-27 13:49:52 +0100 | [diff] [blame] | 931 | }; |
| 932 | |
Fabien Dessenne | c2a97d3 | 2019-05-14 11:20:37 +0200 | [diff] [blame] | 933 | ipcc: mailbox@4c001000 { |
| 934 | compatible = "st,stm32mp1-ipcc"; |
| 935 | #mbox-cells = <1>; |
| 936 | reg = <0x4c001000 0x400>; |
| 937 | st,proc-id = <0>; |
| 938 | interrupts-extended = |
| 939 | <&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, |
Patrick Delaunay | a370530 | 2019-07-11 11:15:28 +0200 | [diff] [blame] | 940 | <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, |
| 941 | <&exti 61 1>; |
| 942 | interrupt-names = "rx", "tx", "wakeup"; |
Fabien Dessenne | c2a97d3 | 2019-05-14 11:20:37 +0200 | [diff] [blame] | 943 | clocks = <&rcc IPCC>; |
Patrick Delaunay | a370530 | 2019-07-11 11:15:28 +0200 | [diff] [blame] | 944 | wakeup-source; |
Fabien Dessenne | c2a97d3 | 2019-05-14 11:20:37 +0200 | [diff] [blame] | 945 | status = "disabled"; |
| 946 | }; |
| 947 | |
Patrick Delaunay | 5059914 | 2018-07-09 15:17:19 +0200 | [diff] [blame] | 948 | rcc: rcc@50000000 { |
| 949 | compatible = "st,stm32mp1-rcc", "syscon"; |
| 950 | reg = <0x50000000 0x1000>; |
| 951 | #clock-cells = <1>; |
| 952 | #reset-cells = <1>; |
| 953 | }; |
| 954 | |
Patrick Delaunay | 5059914 | 2018-07-09 15:17:19 +0200 | [diff] [blame] | 955 | pwr: pwr@50001000 { |
| 956 | compatible = "st,stm32mp1-pwr", "st,stm32-pwr", "syscon", "simple-mfd"; |
| 957 | reg = <0x50001000 0x400>; |
| 958 | system-power-controller; |
| 959 | interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; |
| 960 | st,sysrcc = <&rcc>; |
| 961 | clocks = <&rcc PLL2_R>; |
| 962 | clock-names = "phyclk"; |
| 963 | |
Patrick Delaunay | a370530 | 2019-07-11 11:15:28 +0200 | [diff] [blame] | 964 | pwr-regulators { |
Patrick Delaunay | 5059914 | 2018-07-09 15:17:19 +0200 | [diff] [blame] | 965 | compatible = "st,stm32mp1,pwr-reg"; |
| 966 | st,tzcr = <&rcc 0x0 0x1>; |
| 967 | |
| 968 | reg11: reg11 { |
| 969 | regulator-name = "reg11"; |
| 970 | regulator-min-microvolt = <1100000>; |
| 971 | regulator-max-microvolt = <1100000>; |
| 972 | }; |
| 973 | |
| 974 | reg18: reg18 { |
| 975 | regulator-name = "reg18"; |
| 976 | regulator-min-microvolt = <1800000>; |
| 977 | regulator-max-microvolt = <1800000>; |
| 978 | }; |
| 979 | |
| 980 | usb33: usb33 { |
| 981 | regulator-name = "usb33"; |
| 982 | regulator-min-microvolt = <3300000>; |
| 983 | regulator-max-microvolt = <3300000>; |
| 984 | }; |
| 985 | }; |
| 986 | }; |
| 987 | |
| 988 | exti: interrupt-controller@5000d000 { |
| 989 | compatible = "st,stm32mp1-exti", "syscon"; |
| 990 | interrupt-controller; |
| 991 | #interrupt-cells = <2>; |
| 992 | reg = <0x5000d000 0x400>; |
| 993 | }; |
| 994 | |
Patrice Chotard | 00442d0 | 2019-02-12 16:50:38 +0100 | [diff] [blame] | 995 | syscfg: syscon@50020000 { |
Patrick Delaunay | 63ae49e | 2019-02-27 17:01:23 +0100 | [diff] [blame] | 996 | compatible = "st,stm32mp157-syscfg", "syscon"; |
Patrick Delaunay | 5059914 | 2018-07-09 15:17:19 +0200 | [diff] [blame] | 997 | reg = <0x50020000 0x400>; |
Patrick Delaunay | a370530 | 2019-07-11 11:15:28 +0200 | [diff] [blame] | 998 | clocks = <&rcc SYSCFG>; |
Patrick Delaunay | 5059914 | 2018-07-09 15:17:19 +0200 | [diff] [blame] | 999 | }; |
| 1000 | |
| 1001 | lptimer2: timer@50021000 { |
| 1002 | #address-cells = <1>; |
| 1003 | #size-cells = <0>; |
| 1004 | compatible = "st,stm32-lptimer"; |
| 1005 | reg = <0x50021000 0x400>; |
| 1006 | clocks = <&rcc LPTIM2_K>; |
| 1007 | clock-names = "mux"; |
| 1008 | status = "disabled"; |
| 1009 | |
| 1010 | pwm { |
| 1011 | compatible = "st,stm32-pwm-lp"; |
| 1012 | #pwm-cells = <3>; |
| 1013 | status = "disabled"; |
| 1014 | }; |
| 1015 | |
| 1016 | trigger@1 { |
| 1017 | compatible = "st,stm32-lptimer-trigger"; |
| 1018 | reg = <1>; |
| 1019 | status = "disabled"; |
| 1020 | }; |
| 1021 | |
| 1022 | counter { |
| 1023 | compatible = "st,stm32-lptimer-counter"; |
| 1024 | status = "disabled"; |
| 1025 | }; |
| 1026 | }; |
| 1027 | |
| 1028 | lptimer3: timer@50022000 { |
| 1029 | #address-cells = <1>; |
| 1030 | #size-cells = <0>; |
| 1031 | compatible = "st,stm32-lptimer"; |
| 1032 | reg = <0x50022000 0x400>; |
| 1033 | clocks = <&rcc LPTIM3_K>; |
| 1034 | clock-names = "mux"; |
| 1035 | status = "disabled"; |
| 1036 | |
| 1037 | pwm { |
| 1038 | compatible = "st,stm32-pwm-lp"; |
| 1039 | #pwm-cells = <3>; |
| 1040 | status = "disabled"; |
| 1041 | }; |
| 1042 | |
| 1043 | trigger@2 { |
| 1044 | compatible = "st,stm32-lptimer-trigger"; |
| 1045 | reg = <2>; |
| 1046 | status = "disabled"; |
| 1047 | }; |
| 1048 | }; |
| 1049 | |
| 1050 | lptimer4: timer@50023000 { |
| 1051 | compatible = "st,stm32-lptimer"; |
| 1052 | reg = <0x50023000 0x400>; |
| 1053 | clocks = <&rcc LPTIM4_K>; |
| 1054 | clock-names = "mux"; |
| 1055 | status = "disabled"; |
| 1056 | |
| 1057 | pwm { |
| 1058 | compatible = "st,stm32-pwm-lp"; |
| 1059 | #pwm-cells = <3>; |
| 1060 | status = "disabled"; |
| 1061 | }; |
| 1062 | }; |
| 1063 | |
| 1064 | lptimer5: timer@50024000 { |
| 1065 | compatible = "st,stm32-lptimer"; |
| 1066 | reg = <0x50024000 0x400>; |
| 1067 | clocks = <&rcc LPTIM5_K>; |
| 1068 | clock-names = "mux"; |
| 1069 | status = "disabled"; |
| 1070 | |
| 1071 | pwm { |
| 1072 | compatible = "st,stm32-pwm-lp"; |
| 1073 | #pwm-cells = <3>; |
| 1074 | status = "disabled"; |
| 1075 | }; |
| 1076 | }; |
| 1077 | |
| 1078 | vrefbuf: vrefbuf@50025000 { |
| 1079 | compatible = "st,stm32-vrefbuf"; |
| 1080 | reg = <0x50025000 0x8>; |
| 1081 | regulator-min-microvolt = <1500000>; |
| 1082 | regulator-max-microvolt = <2500000>; |
| 1083 | clocks = <&rcc VREF>; |
| 1084 | status = "disabled"; |
| 1085 | }; |
| 1086 | |
Patrick Delaunay | a370530 | 2019-07-11 11:15:28 +0200 | [diff] [blame] | 1087 | dts: thermal@50028000 { |
| 1088 | compatible = "st,stm32-thermal"; |
| 1089 | reg = <0x50028000 0x100>; |
| 1090 | interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; |
| 1091 | clocks = <&rcc TMPSENS>; |
| 1092 | clock-names = "pclk"; |
| 1093 | #thermal-sensor-cells = <0>; |
| 1094 | status = "disabled"; |
| 1095 | }; |
| 1096 | |
Patrick Delaunay | 5059914 | 2018-07-09 15:17:19 +0200 | [diff] [blame] | 1097 | cryp1: cryp@54001000 { |
| 1098 | compatible = "st,stm32mp1-cryp"; |
| 1099 | reg = <0x54001000 0x400>; |
| 1100 | interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; |
| 1101 | clocks = <&rcc CRYP1>; |
| 1102 | resets = <&rcc CRYP1_R>; |
| 1103 | status = "disabled"; |
| 1104 | }; |
| 1105 | |
Patrice Chotard | 00442d0 | 2019-02-12 16:50:38 +0100 | [diff] [blame] | 1106 | hash1: hash@54002000 { |
| 1107 | compatible = "st,stm32f756-hash"; |
| 1108 | reg = <0x54002000 0x400>; |
| 1109 | interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; |
| 1110 | clocks = <&rcc HASH1>; |
| 1111 | resets = <&rcc HASH1_R>; |
| 1112 | dmas = <&mdma1 31 0x10 0x1000A02 0x0 0x0>; |
| 1113 | dma-names = "in"; |
| 1114 | dma-maxburst = <2>; |
| 1115 | status = "disabled"; |
| 1116 | }; |
| 1117 | |
Patrick Delaunay | 5059914 | 2018-07-09 15:17:19 +0200 | [diff] [blame] | 1118 | rng1: rng@54003000 { |
| 1119 | compatible = "st,stm32-rng"; |
| 1120 | reg = <0x54003000 0x400>; |
| 1121 | clocks = <&rcc RNG1_K>; |
| 1122 | resets = <&rcc RNG1_R>; |
| 1123 | status = "disabled"; |
| 1124 | }; |
| 1125 | |
| 1126 | mdma1: dma@58000000 { |
| 1127 | compatible = "st,stm32h7-mdma"; |
| 1128 | reg = <0x58000000 0x1000>; |
| 1129 | interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; |
| 1130 | clocks = <&rcc MDMA>; |
| 1131 | #dma-cells = <5>; |
| 1132 | dma-channels = <32>; |
| 1133 | dma-requests = <48>; |
| 1134 | }; |
| 1135 | |
Patrick Delaunay | e0188ac | 2019-04-08 15:30:52 +0200 | [diff] [blame] | 1136 | fmc: nand-controller@58002000 { |
| 1137 | compatible = "st,stm32mp15-fmc2"; |
| 1138 | reg = <0x58002000 0x1000>, |
| 1139 | <0x80000000 0x1000>, |
| 1140 | <0x88010000 0x1000>, |
| 1141 | <0x88020000 0x1000>, |
| 1142 | <0x81000000 0x1000>, |
| 1143 | <0x89010000 0x1000>, |
| 1144 | <0x89020000 0x1000>; |
| 1145 | interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; |
| 1146 | clocks = <&rcc FMC_K>; |
| 1147 | resets = <&rcc FMC_R>; |
| 1148 | status = "disabled"; |
| 1149 | }; |
| 1150 | |
Patrice Chotard | 00442d0 | 2019-02-12 16:50:38 +0100 | [diff] [blame] | 1151 | qspi: spi@58003000 { |
Patrick Delaunay | 5059914 | 2018-07-09 15:17:19 +0200 | [diff] [blame] | 1152 | compatible = "st,stm32f469-qspi"; |
| 1153 | reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; |
| 1154 | reg-names = "qspi", "qspi_mm"; |
| 1155 | interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; |
| 1156 | clocks = <&rcc QSPI_K>; |
| 1157 | resets = <&rcc QSPI_R>; |
| 1158 | status = "disabled"; |
| 1159 | }; |
| 1160 | |
| 1161 | sdmmc1: sdmmc@58005000 { |
Patrick Delaunay | a370530 | 2019-07-11 11:15:28 +0200 | [diff] [blame] | 1162 | compatible = "arm,pl18x", "arm,primecell"; |
| 1163 | arm,primecell-periphid = <0x10153180>; |
| 1164 | reg = <0x58005000 0x1000>; |
| 1165 | interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; |
| 1166 | interrupt-names = "cmd_irq"; |
Patrick Delaunay | 5059914 | 2018-07-09 15:17:19 +0200 | [diff] [blame] | 1167 | clocks = <&rcc SDMMC1_K>; |
Patrick Delaunay | a370530 | 2019-07-11 11:15:28 +0200 | [diff] [blame] | 1168 | clock-names = "apb_pclk"; |
Patrick Delaunay | 5059914 | 2018-07-09 15:17:19 +0200 | [diff] [blame] | 1169 | resets = <&rcc SDMMC1_R>; |
Patrick Delaunay | 5059914 | 2018-07-09 15:17:19 +0200 | [diff] [blame] | 1170 | cap-sd-highspeed; |
| 1171 | cap-mmc-highspeed; |
| 1172 | max-frequency = <120000000>; |
Patrick Delaunay | 5059914 | 2018-07-09 15:17:19 +0200 | [diff] [blame] | 1173 | }; |
| 1174 | |
| 1175 | sdmmc2: sdmmc@58007000 { |
Patrick Delaunay | a370530 | 2019-07-11 11:15:28 +0200 | [diff] [blame] | 1176 | compatible = "arm,pl18x", "arm,primecell"; |
| 1177 | arm,primecell-periphid = <0x10153180>; |
| 1178 | reg = <0x58007000 0x1000>; |
Patrick Delaunay | 5059914 | 2018-07-09 15:17:19 +0200 | [diff] [blame] | 1179 | interrupts = <GIC_SPI 124 IRQ_TYPE_NONE>; |
| 1180 | clocks = <&rcc SDMMC2_K>; |
Patrick Delaunay | a370530 | 2019-07-11 11:15:28 +0200 | [diff] [blame] | 1181 | clock-names = "apb_pclk"; |
Patrick Delaunay | 5059914 | 2018-07-09 15:17:19 +0200 | [diff] [blame] | 1182 | resets = <&rcc SDMMC2_R>; |
Patrick Delaunay | 5059914 | 2018-07-09 15:17:19 +0200 | [diff] [blame] | 1183 | cap-sd-highspeed; |
| 1184 | cap-mmc-highspeed; |
| 1185 | max-frequency = <120000000>; |
| 1186 | status = "disabled"; |
| 1187 | }; |
| 1188 | |
| 1189 | crc1: crc@58009000 { |
| 1190 | compatible = "st,stm32f7-crc"; |
| 1191 | reg = <0x58009000 0x400>; |
| 1192 | clocks = <&rcc CRC1>; |
| 1193 | status = "disabled"; |
| 1194 | }; |
| 1195 | |
Patrice Chotard | 00442d0 | 2019-02-12 16:50:38 +0100 | [diff] [blame] | 1196 | stmmac_axi_config_0: stmmac-axi-config { |
| 1197 | snps,wr_osr_lmt = <0x7>; |
| 1198 | snps,rd_osr_lmt = <0x7>; |
| 1199 | snps,blen = <0 0 0 0 16 8 4>; |
| 1200 | }; |
| 1201 | |
| 1202 | ethernet0: ethernet@5800a000 { |
| 1203 | compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a"; |
| 1204 | reg = <0x5800a000 0x2000>; |
| 1205 | reg-names = "stmmaceth"; |
Patrick Delaunay | a370530 | 2019-07-11 11:15:28 +0200 | [diff] [blame] | 1206 | interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; |
| 1207 | interrupt-names = "macirq"; |
Patrice Chotard | 00442d0 | 2019-02-12 16:50:38 +0100 | [diff] [blame] | 1208 | clock-names = "stmmaceth", |
| 1209 | "mac-clk-tx", |
| 1210 | "mac-clk-rx", |
Patrick Delaunay | a370530 | 2019-07-11 11:15:28 +0200 | [diff] [blame] | 1211 | "ethstp", |
| 1212 | "syscfg-clk"; |
Patrice Chotard | 00442d0 | 2019-02-12 16:50:38 +0100 | [diff] [blame] | 1213 | clocks = <&rcc ETHMAC>, |
| 1214 | <&rcc ETHTX>, |
| 1215 | <&rcc ETHRX>, |
Patrick Delaunay | a370530 | 2019-07-11 11:15:28 +0200 | [diff] [blame] | 1216 | <&rcc ETHSTP>, |
| 1217 | <&rcc SYSCFG>; |
Patrice Chotard | 00442d0 | 2019-02-12 16:50:38 +0100 | [diff] [blame] | 1218 | st,syscon = <&syscfg 0x4>; |
| 1219 | snps,mixed-burst; |
| 1220 | snps,pbl = <2>; |
| 1221 | snps,axi-config = <&stmmac_axi_config_0>; |
| 1222 | snps,tso; |
| 1223 | status = "disabled"; |
| 1224 | }; |
| 1225 | |
Patrick Delaunay | 5059914 | 2018-07-09 15:17:19 +0200 | [diff] [blame] | 1226 | usbh_ohci: usbh-ohci@5800c000 { |
| 1227 | compatible = "generic-ohci"; |
| 1228 | reg = <0x5800c000 0x1000>; |
| 1229 | clocks = <&rcc USBH>; |
| 1230 | resets = <&rcc USBH_R>; |
| 1231 | interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; |
| 1232 | status = "disabled"; |
| 1233 | }; |
| 1234 | |
| 1235 | usbh_ehci: usbh-ehci@5800d000 { |
| 1236 | compatible = "generic-ehci"; |
| 1237 | reg = <0x5800d000 0x1000>; |
| 1238 | clocks = <&rcc USBH>; |
| 1239 | resets = <&rcc USBH_R>; |
| 1240 | interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; |
| 1241 | companion = <&usbh_ohci>; |
| 1242 | status = "disabled"; |
| 1243 | }; |
| 1244 | |
| 1245 | dsi: dsi@5a000000 { |
| 1246 | compatible = "st,stm32-dsi"; |
| 1247 | reg = <0x5a000000 0x800>; |
| 1248 | clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>; |
| 1249 | clock-names = "pclk", "ref", "px_clk"; |
| 1250 | resets = <&rcc DSI_R>; |
| 1251 | reset-names = "apb"; |
| 1252 | status = "disabled"; |
| 1253 | }; |
| 1254 | |
| 1255 | ltdc: display-controller@5a001000 { |
| 1256 | compatible = "st,stm32-ltdc"; |
| 1257 | reg = <0x5a001000 0x400>; |
| 1258 | interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, |
| 1259 | <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; |
| 1260 | clocks = <&rcc LTDC_PX>; |
| 1261 | clock-names = "lcd"; |
| 1262 | resets = <&rcc LTDC_R>; |
| 1263 | status = "disabled"; |
| 1264 | }; |
| 1265 | |
Patrice Chotard | 00442d0 | 2019-02-12 16:50:38 +0100 | [diff] [blame] | 1266 | iwdg2: watchdog@5a002000 { |
| 1267 | compatible = "st,stm32mp1-iwdg"; |
| 1268 | reg = <0x5a002000 0x400>; |
| 1269 | clocks = <&rcc IWDG2>, <&rcc CK_LSI>; |
| 1270 | clock-names = "pclk", "lsi"; |
| 1271 | status = "disabled"; |
| 1272 | }; |
| 1273 | |
Patrick Delaunay | 5059914 | 2018-07-09 15:17:19 +0200 | [diff] [blame] | 1274 | usbphyc: usbphyc@5a006000 { |
| 1275 | #address-cells = <1>; |
| 1276 | #size-cells = <0>; |
| 1277 | compatible = "st,stm32mp1-usbphyc"; |
| 1278 | reg = <0x5a006000 0x1000>; |
| 1279 | clocks = <&rcc USBPHY_K>; |
| 1280 | resets = <&rcc USBPHY_R>; |
Patrick Delaunay | 6ba88cd | 2019-03-29 15:42:11 +0100 | [diff] [blame] | 1281 | vdda1v1-supply = <®11>; |
| 1282 | vdda1v8-supply = <®18>; |
Patrick Delaunay | 5059914 | 2018-07-09 15:17:19 +0200 | [diff] [blame] | 1283 | status = "disabled"; |
| 1284 | |
| 1285 | usbphyc_port0: usb-phy@0 { |
| 1286 | #phy-cells = <0>; |
| 1287 | reg = <0>; |
| 1288 | }; |
| 1289 | |
| 1290 | usbphyc_port1: usb-phy@1 { |
| 1291 | #phy-cells = <1>; |
| 1292 | reg = <1>; |
| 1293 | }; |
| 1294 | }; |
| 1295 | |
| 1296 | usart1: serial@5c000000 { |
| 1297 | compatible = "st,stm32h7-uart"; |
| 1298 | reg = <0x5c000000 0x400>; |
| 1299 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; |
| 1300 | clocks = <&rcc USART1_K>; |
| 1301 | status = "disabled"; |
| 1302 | }; |
| 1303 | |
Patrice Chotard | 00442d0 | 2019-02-12 16:50:38 +0100 | [diff] [blame] | 1304 | spi6: spi@5c001000 { |
| 1305 | #address-cells = <1>; |
| 1306 | #size-cells = <0>; |
| 1307 | compatible = "st,stm32h7-spi"; |
| 1308 | reg = <0x5c001000 0x400>; |
| 1309 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
| 1310 | clocks = <&rcc SPI6_K>; |
| 1311 | resets = <&rcc SPI6_R>; |
| 1312 | dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>, |
| 1313 | <&mdma1 35 0x0 0x40002 0x0 0x0>; |
| 1314 | dma-names = "rx", "tx"; |
| 1315 | status = "disabled"; |
| 1316 | }; |
| 1317 | |
Patrick Delaunay | 5059914 | 2018-07-09 15:17:19 +0200 | [diff] [blame] | 1318 | i2c4: i2c@5c002000 { |
| 1319 | compatible = "st,stm32f7-i2c"; |
| 1320 | reg = <0x5c002000 0x400>; |
| 1321 | interrupt-names = "event", "error"; |
| 1322 | interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, |
| 1323 | <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; |
| 1324 | clocks = <&rcc I2C4_K>; |
| 1325 | resets = <&rcc I2C4_R>; |
| 1326 | #address-cells = <1>; |
| 1327 | #size-cells = <0>; |
| 1328 | status = "disabled"; |
| 1329 | }; |
| 1330 | |
Patrice Chotard | 00442d0 | 2019-02-12 16:50:38 +0100 | [diff] [blame] | 1331 | rtc: rtc@5c004000 { |
| 1332 | compatible = "st,stm32mp1-rtc"; |
| 1333 | reg = <0x5c004000 0x400>; |
| 1334 | clocks = <&rcc RTCAPB>, <&rcc RTC>; |
| 1335 | clock-names = "pclk", "rtc_ck"; |
| 1336 | interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; |
| 1337 | status = "disabled"; |
| 1338 | }; |
| 1339 | |
Patrick Delaunay | bdd7136 | 2019-02-27 17:01:27 +0100 | [diff] [blame] | 1340 | bsec: nvmem@5c005000 { |
| 1341 | compatible = "st,stm32mp15-bsec"; |
| 1342 | reg = <0x5c005000 0x400>; |
| 1343 | #address-cells = <1>; |
| 1344 | #size-cells = <1>; |
Patrick Delaunay | a370530 | 2019-07-11 11:15:28 +0200 | [diff] [blame] | 1345 | ts_cal1: calib@5c { |
| 1346 | reg = <0x5c 0x2>; |
| 1347 | }; |
| 1348 | ts_cal2: calib@5e { |
| 1349 | reg = <0x5e 0x2>; |
| 1350 | }; |
Patrick Delaunay | bdd7136 | 2019-02-27 17:01:27 +0100 | [diff] [blame] | 1351 | }; |
| 1352 | |
Patrick Delaunay | 5059914 | 2018-07-09 15:17:19 +0200 | [diff] [blame] | 1353 | i2c6: i2c@5c009000 { |
| 1354 | compatible = "st,stm32f7-i2c"; |
| 1355 | reg = <0x5c009000 0x400>; |
| 1356 | interrupt-names = "event", "error"; |
| 1357 | interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, |
| 1358 | <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; |
| 1359 | clocks = <&rcc I2C6_K>; |
| 1360 | resets = <&rcc I2C6_R>; |
| 1361 | #address-cells = <1>; |
| 1362 | #size-cells = <0>; |
| 1363 | status = "disabled"; |
| 1364 | }; |
| 1365 | }; |
| 1366 | }; |