Marek Vasut | 0f97ed0 | 2020-04-29 20:09:08 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * Copyright 2018 NXP |
| 4 | */ |
| 5 | |
Marek Vasut | 0f97ed0 | 2020-04-29 20:09:08 +0200 | [diff] [blame] | 6 | #include <env.h> |
| 7 | #include <init.h> |
| 8 | #include <malloc.h> |
| 9 | #include <errno.h> |
Simon Glass | 3ba929a | 2020-10-30 21:38:53 -0600 | [diff] [blame] | 10 | #include <asm/global_data.h> |
Marek Vasut | 0f97ed0 | 2020-04-29 20:09:08 +0200 | [diff] [blame] | 11 | #include <asm/io.h> |
| 12 | #include <miiphy.h> |
| 13 | #include <netdev.h> |
| 14 | #include <asm/mach-imx/iomux-v3.h> |
| 15 | #include <asm-generic/gpio.h> |
| 16 | #include <fsl_esdhc_imx.h> |
| 17 | #include <mmc.h> |
| 18 | #include <asm/arch/imx8mq_pins.h> |
| 19 | #include <asm/arch/sys_proto.h> |
| 20 | #include <asm/mach-imx/gpio.h> |
| 21 | #include <asm/mach-imx/mxc_i2c.h> |
| 22 | #include <asm/arch/clock.h> |
Simon Glass | dbd7954 | 2020-05-10 11:40:11 -0600 | [diff] [blame] | 23 | #include <linux/delay.h> |
Marek Vasut | 0f97ed0 | 2020-04-29 20:09:08 +0200 | [diff] [blame] | 24 | #include <spl.h> |
| 25 | #include <power/pmic.h> |
| 26 | |
| 27 | DECLARE_GLOBAL_DATA_PTR; |
| 28 | |
| 29 | #define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) |
| 30 | |
| 31 | #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) |
| 32 | |
| 33 | static iomux_v3_cfg_t const wdog_pads[] = { |
| 34 | IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), |
| 35 | }; |
| 36 | |
| 37 | static iomux_v3_cfg_t const uart_pads[] = { |
| 38 | IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), |
| 39 | IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), |
| 40 | }; |
| 41 | |
| 42 | int board_early_init_f(void) |
| 43 | { |
| 44 | struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; |
| 45 | |
| 46 | imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); |
| 47 | set_wdog_reset(wdog); |
| 48 | |
| 49 | imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); |
| 50 | |
| 51 | return 0; |
| 52 | } |
| 53 | |
Peng Fan | fa35c3d | 2020-07-09 15:26:06 +0800 | [diff] [blame] | 54 | int board_phys_sdram_size(phys_size_t *size) |
Marek Vasut | 0f97ed0 | 2020-04-29 20:09:08 +0200 | [diff] [blame] | 55 | { |
Peng Fan | e9015f3 | 2023-06-15 18:09:18 +0800 | [diff] [blame] | 56 | int ddr_size = readl(MCU_BOOTROM_BASE_ADDR); |
Marek Vasut | 0f97ed0 | 2020-04-29 20:09:08 +0200 | [diff] [blame] | 57 | |
Peng Fan | fa35c3d | 2020-07-09 15:26:06 +0800 | [diff] [blame] | 58 | if (ddr_size == 0x4) { |
| 59 | *size = 0x100000000; |
| 60 | } else if (ddr_size == 0x3) { |
| 61 | *size = 0xc0000000; |
| 62 | } else if (ddr_size == 0x2) { |
| 63 | *size = 0x80000000; |
| 64 | } else if (ddr_size == 0x1) { |
| 65 | *size = 0x40000000; |
| 66 | } else { |
Marek Vasut | 0f97ed0 | 2020-04-29 20:09:08 +0200 | [diff] [blame] | 67 | printf("Unknown DDR type!!!\n"); |
Peng Fan | fa35c3d | 2020-07-09 15:26:06 +0800 | [diff] [blame] | 68 | return -1; |
| 69 | } |
Marek Vasut | 0f97ed0 | 2020-04-29 20:09:08 +0200 | [diff] [blame] | 70 | |
| 71 | return 0; |
| 72 | } |
| 73 | |
| 74 | #ifdef CONFIG_FEC_MXC |
| 75 | #define FEC_RST_PAD IMX_GPIO_NR(1, 9) |
| 76 | #define FEC_PWR_PAD IMX_GPIO_NR(1, 0) |
| 77 | static iomux_v3_cfg_t const fec1_pads[] = { |
| 78 | /* Reset */ |
| 79 | IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| 80 | /* Power */ |
| 81 | IMX8MQ_PAD_GPIO1_IO00__GPIO1_IO0 | MUX_PAD_CTRL(NO_PAD_CTRL), |
| 82 | }; |
| 83 | |
| 84 | static void setup_iomux_fec(void) |
| 85 | { |
| 86 | imx_iomux_v3_setup_multiple_pads(fec1_pads, ARRAY_SIZE(fec1_pads)); |
| 87 | |
| 88 | gpio_request(IMX_GPIO_NR(1, 0), "fec1_pwr"); |
| 89 | gpio_direction_output(IMX_GPIO_NR(1, 0), 1); |
| 90 | udelay(500); |
| 91 | |
| 92 | gpio_request(IMX_GPIO_NR(1, 9), "fec1_rst"); |
| 93 | gpio_direction_output(IMX_GPIO_NR(1, 9), 0); |
| 94 | udelay(500); |
| 95 | gpio_direction_output(IMX_GPIO_NR(1, 9), 1); |
| 96 | } |
| 97 | |
| 98 | static int setup_fec(void) |
| 99 | { |
| 100 | struct iomuxc_gpr_base_regs *gpr = |
| 101 | (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; |
| 102 | |
| 103 | setup_iomux_fec(); |
| 104 | |
| 105 | /* Use 125M anatop REF_CLK1 for ENET1, not from external */ |
| 106 | clrsetbits_le32(&gpr->gpr[1], BIT(13) | BIT(17), 0); |
| 107 | return set_clk_enet(ENET_125MHZ); |
| 108 | } |
| 109 | |
| 110 | int board_phy_config(struct phy_device *phydev) |
| 111 | { |
| 112 | /* enable rgmii rxc skew and phy mode select to RGMII copper */ |
| 113 | phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); |
| 114 | phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); |
| 115 | |
| 116 | phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); |
| 117 | phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); |
| 118 | |
| 119 | if (phydev->drv->config) |
| 120 | phydev->drv->config(phydev); |
| 121 | return 0; |
| 122 | } |
| 123 | #endif |
| 124 | |
| 125 | int board_init(void) |
| 126 | { |
| 127 | #ifdef CONFIG_FEC_MXC |
| 128 | setup_fec(); |
| 129 | #endif |
| 130 | |
| 131 | return 0; |
| 132 | } |
| 133 | |
| 134 | int board_mmc_get_env_dev(int devno) |
| 135 | { |
| 136 | return devno; |
| 137 | } |
| 138 | |
| 139 | int board_late_init(void) |
| 140 | { |
| 141 | #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG |
| 142 | env_set("board_rev", "iMX8MQ"); |
| 143 | #endif |
| 144 | return 0; |
| 145 | } |