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Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +02002/*
3 * (C) Copyright 2008
4 * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com.
5 *
6 * Copyright 2008 Freescale Semiconductor, Inc.
7 *
8 * (C) Copyright 2000
9 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020010 */
11
Tom Rinie833d002024-04-30 20:42:48 -060012#include <config.h>
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020013#include <asm/fsl_law.h>
14#include <asm/mmu.h>
15
16/*
17 * LAW(Local Access Window) configuration:
18 *
Sergei Poselenov96dd16b2008-06-06 15:42:41 +020019 * 0x0000_0000 0x2fff_ffff DDR 512M
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020020 * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
Sergei Poselenov96dd16b2008-06-06 15:42:41 +020021 * 0xc000_0000 0xc00f_ffff FPGA 1M
Anatolij Gustschine6f5c912008-08-15 15:42:13 +020022 * 0xc800_0000 0xcbff_ffff LIME 64M
Sergei Poselenov96dd16b2008-06-06 15:42:41 +020023 * 0xe000_0000 0xe00f_ffff CCSR 1M (mapped by CCSRBAR)
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020024 * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
Sergei Poselenov96dd16b2008-06-06 15:42:41 +020025 * 0xfc00_0000 0xffff_ffff FLASH 64M
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020026 *
27 * Notes:
28 * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
29 * If flash is 8M at default position (last 8M), no LAW needed.
30 */
31
32struct law_entry law_table[] = {
Tom Rini6a5dccc2022-11-16 13:10:41 -050033 SET_LAW(CFG_SYS_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR),
34 SET_LAW(CFG_SYS_LBC_FLASH_BASE, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
35#if defined(CFG_SYS_FPGA_BASE)
36 SET_LAW(CFG_SYS_FPGA_BASE, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
Sergei Poselenov96dd16b2008-06-06 15:42:41 +020037#endif
Tom Rini6a5dccc2022-11-16 13:10:41 -050038 SET_LAW(CFG_SYS_LIME_BASE, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
Sergei Poselenovf2bf96c2008-04-30 11:42:50 +020039};
40
41int num_law_entries = ARRAY_SIZE(law_table);