Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Rick Chen | 76c0a24 | 2017-12-26 13:55:51 +0800 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (c) 2017 Microsemi Corporation. |
| 4 | * Padmarao Begari, Microsemi Corporation <padmarao.begari@microsemi.com> |
Rick Chen | 76c0a24 | 2017-12-26 13:55:51 +0800 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef RISCV_CSR_ENCODING_H |
| 8 | #define RISCV_CSR_ENCODING_H |
| 9 | |
Anup Patel | 89b3934 | 2018-12-03 10:57:40 +0530 | [diff] [blame] | 10 | #ifdef CONFIG_RISCV_SMODE |
| 11 | #define MODE_PREFIX(__suffix) s##__suffix |
| 12 | #else |
| 13 | #define MODE_PREFIX(__suffix) m##__suffix |
| 14 | #endif |
| 15 | |
Rick Chen | 76c0a24 | 2017-12-26 13:55:51 +0800 | [diff] [blame] | 16 | #define MSTATUS_UIE 0x00000001 |
| 17 | #define MSTATUS_SIE 0x00000002 |
| 18 | #define MSTATUS_HIE 0x00000004 |
| 19 | #define MSTATUS_MIE 0x00000008 |
| 20 | #define MSTATUS_UPIE 0x00000010 |
| 21 | #define MSTATUS_SPIE 0x00000020 |
| 22 | #define MSTATUS_HPIE 0x00000040 |
| 23 | #define MSTATUS_MPIE 0x00000080 |
| 24 | #define MSTATUS_SPP 0x00000100 |
| 25 | #define MSTATUS_HPP 0x00000600 |
| 26 | #define MSTATUS_MPP 0x00001800 |
| 27 | #define MSTATUS_FS 0x00006000 |
| 28 | #define MSTATUS_XS 0x00018000 |
| 29 | #define MSTATUS_MPRV 0x00020000 |
| 30 | #define MSTATUS_PUM 0x00040000 |
| 31 | #define MSTATUS_VM 0x1F000000 |
| 32 | #define MSTATUS32_SD 0x80000000 |
| 33 | #define MSTATUS64_SD 0x8000000000000000 |
| 34 | |
| 35 | #define MCAUSE32_CAUSE 0x7FFFFFFF |
| 36 | #define MCAUSE64_CAUSE 0x7FFFFFFFFFFFFFFF |
| 37 | #define MCAUSE32_INT 0x80000000 |
| 38 | #define MCAUSE64_INT 0x8000000000000000 |
| 39 | |
| 40 | #define SSTATUS_UIE 0x00000001 |
| 41 | #define SSTATUS_SIE 0x00000002 |
| 42 | #define SSTATUS_UPIE 0x00000010 |
| 43 | #define SSTATUS_SPIE 0x00000020 |
| 44 | #define SSTATUS_SPP 0x00000100 |
| 45 | #define SSTATUS_FS 0x00006000 |
| 46 | #define SSTATUS_XS 0x00018000 |
| 47 | #define SSTATUS_PUM 0x00040000 |
| 48 | #define SSTATUS32_SD 0x80000000 |
| 49 | #define SSTATUS64_SD 0x8000000000000000 |
| 50 | |
| 51 | #define MIP_SSIP BIT(IRQ_S_SOFT) |
| 52 | #define MIP_HSIP BIT(IRQ_H_SOFT) |
| 53 | #define MIP_MSIP BIT(IRQ_M_SOFT) |
| 54 | #define MIP_STIP BIT(IRQ_S_TIMER) |
| 55 | #define MIP_HTIP BIT(IRQ_H_TIMER) |
| 56 | #define MIP_MTIP BIT(IRQ_M_TIMER) |
| 57 | #define MIP_SEIP BIT(IRQ_S_EXT) |
| 58 | #define MIP_HEIP BIT(IRQ_H_EXT) |
| 59 | #define MIP_MEIP BIT(IRQ_M_EXT) |
| 60 | |
| 61 | #define SIP_SSIP MIP_SSIP |
| 62 | #define SIP_STIP MIP_STIP |
| 63 | |
| 64 | #define PRV_U 0 |
| 65 | #define PRV_S 1 |
| 66 | #define PRV_H 2 |
| 67 | #define PRV_M 3 |
| 68 | |
| 69 | #define VM_MBARE 0 |
| 70 | #define VM_MBB 1 |
| 71 | #define VM_MBBID 2 |
| 72 | #define VM_SV32 8 |
| 73 | #define VM_SV39 9 |
| 74 | #define VM_SV48 10 |
| 75 | |
| 76 | #define IRQ_S_SOFT 1 |
| 77 | #define IRQ_H_SOFT 2 |
| 78 | #define IRQ_M_SOFT 3 |
| 79 | #define IRQ_S_TIMER 5 |
| 80 | #define IRQ_H_TIMER 6 |
| 81 | #define IRQ_M_TIMER 7 |
| 82 | #define IRQ_S_EXT 9 |
| 83 | #define IRQ_H_EXT 10 |
| 84 | #define IRQ_M_EXT 11 |
| 85 | #define IRQ_COP 12 |
| 86 | #define IRQ_HOST 13 |
| 87 | |
Bin Meng | 731e2d4 | 2018-12-12 06:12:37 -0800 | [diff] [blame] | 88 | #define CAUSE_MISALIGNED_FETCH 0 |
| 89 | #define CAUSE_FETCH_ACCESS 1 |
| 90 | #define CAUSE_ILLEGAL_INSTRUCTION 2 |
| 91 | #define CAUSE_BREAKPOINT 3 |
| 92 | #define CAUSE_MISALIGNED_LOAD 4 |
| 93 | #define CAUSE_LOAD_ACCESS 5 |
| 94 | #define CAUSE_MISALIGNED_STORE 6 |
| 95 | #define CAUSE_STORE_ACCESS 7 |
| 96 | #define CAUSE_USER_ECALL 8 |
| 97 | #define CAUSE_SUPERVISOR_ECALL 9 |
| 98 | #define CAUSE_MACHINE_ECALL 11 |
| 99 | #define CAUSE_FETCH_PAGE_FAULT 12 |
| 100 | #define CAUSE_LOAD_PAGE_FAULT 13 |
| 101 | #define CAUSE_STORE_PAGE_FAULT 15 |
| 102 | |
Rick Chen | 76c0a24 | 2017-12-26 13:55:51 +0800 | [diff] [blame] | 103 | #define DEFAULT_RSTVEC 0x00001000 |
| 104 | #define DEFAULT_NMIVEC 0x00001004 |
| 105 | #define DEFAULT_MTVEC 0x00001010 |
| 106 | #define CONFIG_STRING_ADDR 0x0000100C |
| 107 | #define EXT_IO_BASE 0x40000000 |
| 108 | #define DRAM_BASE 0x80000000 |
| 109 | |
| 110 | // page table entry (PTE) fields |
| 111 | #define PTE_V 0x001 // Valid |
| 112 | #define PTE_TYPE 0x01E // Type |
| 113 | #define PTE_R 0x020 // Referenced |
| 114 | #define PTE_D 0x040 // Dirty |
| 115 | #define PTE_SOFT 0x380 // Reserved for Software |
| 116 | |
| 117 | #define PTE_TYPE_TABLE 0x00 |
| 118 | #define PTE_TYPE_TABLE_GLOBAL 0x02 |
| 119 | #define PTE_TYPE_URX_SR 0x04 |
| 120 | #define PTE_TYPE_URWX_SRW 0x06 |
| 121 | #define PTE_TYPE_UR_SR 0x08 |
| 122 | #define PTE_TYPE_URW_SRW 0x0A |
| 123 | #define PTE_TYPE_URX_SRX 0x0C |
| 124 | #define PTE_TYPE_URWX_SRWX0x0E |
| 125 | #define PTE_TYPE_SR 0x10 |
| 126 | #define PTE_TYPE_SRW 0x12 |
| 127 | #define PTE_TYPE_SRX 0x14 |
| 128 | #define PTE_TYPE_SRWX 0x16 |
| 129 | #define PTE_TYPE_SR_GLOBAL 0x18 |
| 130 | #define PTE_TYPE_SRW_GLOBAL 0x1A |
| 131 | #define PTE_TYPE_SRX_GLOBAL 0x1C |
| 132 | #define PTE_TYPE_SRWX_GLOBAL 0x1E |
| 133 | |
| 134 | #define PTE_PPN_SHIFT 10 |
| 135 | |
| 136 | #define PTE_TABLE(PTE) ((0x0000000AU >> ((PTE) & 0x1F)) & 1) |
| 137 | #define PTE_UR(PTE) ((0x0000AAA0U >> ((PTE) & 0x1F)) & 1) |
| 138 | #define PTE_UW(PTE) ((0x00008880U >> ((PTE) & 0x1F)) & 1) |
| 139 | #define PTE_UX(PTE) ((0x0000A0A0U >> ((PTE) & 0x1F)) & 1) |
| 140 | #define PTE_SR(PTE) ((0xAAAAAAA0U >> ((PTE) & 0x1F)) & 1) |
| 141 | #define PTE_SW(PTE) ((0x88888880U >> ((PTE) & 0x1F)) & 1) |
| 142 | #define PTE_SX(PTE) ((0xA0A0A000U >> ((PTE) & 0x1F)) & 1) |
| 143 | |
Rick Chen | 5febadd | 2018-02-12 11:07:58 +0800 | [diff] [blame] | 144 | #define PTE_CHECK_PERM(_PTE, _SUPERVISOR, STORE, FETCH) \ |
| 145 | typeof(_PTE) (PTE) = (_PTE); \ |
| 146 | typeof(_SUPERVISOR) (SUPERVISOR) = (_SUPERVISOR); \ |
Rick Chen | 76c0a24 | 2017-12-26 13:55:51 +0800 | [diff] [blame] | 147 | ((STORE) ? ((SUPERVISOR) ? PTE_SW(PTE) : PTE_UW(PTE)) : \ |
| 148 | (FETCH) ? ((SUPERVISOR) ? PTE_SX(PTE) : PTE_UX(PTE)) : \ |
| 149 | ((SUPERVISOR) ? PTE_SR(PTE) : PTE_UR(PTE))) |
| 150 | |
| 151 | #ifdef __riscv |
Bin Meng | 748dae2 | 2018-09-26 06:55:15 -0700 | [diff] [blame] | 152 | |
Rick Chen | 76c0a24 | 2017-12-26 13:55:51 +0800 | [diff] [blame] | 153 | #ifdef CONFIG_64BIT |
| 154 | # define MSTATUS_SD MSTATUS64_SD |
| 155 | # define SSTATUS_SD SSTATUS64_SD |
| 156 | # define MCAUSE_INT MCAUSE64_INT |
| 157 | # define MCAUSE_CAUSE MCAUSE64_CAUSE |
| 158 | # define RISCV_PGLEVEL_BITS 9 |
| 159 | #else |
| 160 | # define MSTATUS_SD MSTATUS32_SD |
| 161 | # define SSTATUS_SD SSTATUS32_SD |
| 162 | # define RISCV_PGLEVEL_BITS 10 |
| 163 | # define MCAUSE_INT MCAUSE32_INT |
| 164 | # define MCAUSE_CAUSE MCAUSE32_CAUSE |
| 165 | #endif |
Bin Meng | 748dae2 | 2018-09-26 06:55:15 -0700 | [diff] [blame] | 166 | |
Rick Chen | 76c0a24 | 2017-12-26 13:55:51 +0800 | [diff] [blame] | 167 | #define RISCV_PGSHIFT 12 |
| 168 | #define RISCV_PGSIZE BIT(RISCV_PGSHIFT) |
| 169 | |
Bin Meng | ea5086b | 2018-12-12 06:12:36 -0800 | [diff] [blame] | 170 | /* CSR numbers */ |
| 171 | #define CSR_FFLAGS 0x1 |
| 172 | #define CSR_FRM 0x2 |
| 173 | #define CSR_FCSR 0x3 |
| 174 | |
| 175 | #define CSR_SSTATUS 0x100 |
| 176 | #define CSR_SEDELEG 0x102 |
| 177 | #define CSR_SIDELEG 0x103 |
| 178 | #define CSR_SIE 0x104 |
| 179 | #define CSR_STVEC 0x105 |
| 180 | #define CSR_SCOUNTEREN 0x106 |
| 181 | #define CSR_SSCRATCH 0x140 |
| 182 | #define CSR_SEPC 0x141 |
| 183 | #define CSR_SCAUSE 0x142 |
| 184 | #define CSR_STVAL 0x143 |
| 185 | #define CSR_SIP 0x144 |
| 186 | #define CSR_SATP 0x180 |
| 187 | |
| 188 | #define CSR_MSTATUS 0x300 |
| 189 | #define CSR_MISA 0x301 |
| 190 | #define CSR_MEDELEG 0x302 |
| 191 | #define CSR_MIDELEG 0x303 |
| 192 | #define CSR_MIE 0x304 |
| 193 | #define CSR_MTVEC 0x305 |
| 194 | #define CSR_MCOUNTEREN 0x306 |
| 195 | #define CSR_MHPMEVENT3 0x323 |
| 196 | #define CSR_MHPMEVENT4 0x324 |
| 197 | #define CSR_MHPMEVENT5 0x325 |
| 198 | #define CSR_MHPMEVENT6 0x326 |
| 199 | #define CSR_MHPMEVENT7 0x327 |
| 200 | #define CSR_MHPMEVENT8 0x328 |
| 201 | #define CSR_MHPMEVENT9 0x329 |
| 202 | #define CSR_MHPMEVENT10 0x32a |
| 203 | #define CSR_MHPMEVENT11 0x32b |
| 204 | #define CSR_MHPMEVENT12 0x32c |
| 205 | #define CSR_MHPMEVENT13 0x32d |
| 206 | #define CSR_MHPMEVENT14 0x32e |
| 207 | #define CSR_MHPMEVENT15 0x32f |
| 208 | #define CSR_MHPMEVENT16 0x330 |
| 209 | #define CSR_MHPMEVENT17 0x331 |
| 210 | #define CSR_MHPMEVENT18 0x332 |
| 211 | #define CSR_MHPMEVENT19 0x333 |
| 212 | #define CSR_MHPMEVENT20 0x334 |
| 213 | #define CSR_MHPMEVENT21 0x335 |
| 214 | #define CSR_MHPMEVENT22 0x336 |
| 215 | #define CSR_MHPMEVENT23 0x337 |
| 216 | #define CSR_MHPMEVENT24 0x338 |
| 217 | #define CSR_MHPMEVENT25 0x339 |
| 218 | #define CSR_MHPMEVENT26 0x33a |
| 219 | #define CSR_MHPMEVENT27 0x33b |
| 220 | #define CSR_MHPMEVENT28 0x33c |
| 221 | #define CSR_MHPMEVENT29 0x33d |
| 222 | #define CSR_MHPMEVENT30 0x33e |
| 223 | #define CSR_MHPMEVENT31 0x33f |
| 224 | #define CSR_MSCRATCH 0x340 |
| 225 | #define CSR_MEPC 0x341 |
| 226 | #define CSR_MCAUSE 0x342 |
| 227 | #define CSR_MTVAL 0x343 |
| 228 | #define CSR_MIP 0x344 |
| 229 | #define CSR_PMPCFG0 0x3a0 |
| 230 | #define CSR_PMPCFG1 0x3a1 |
| 231 | #define CSR_PMPCFG2 0x3a2 |
| 232 | #define CSR_PMPCFG3 0x3a3 |
| 233 | #define CSR_PMPADDR0 0x3b0 |
| 234 | #define CSR_PMPADDR1 0x3b1 |
| 235 | #define CSR_PMPADDR2 0x3b2 |
| 236 | #define CSR_PMPADDR3 0x3b3 |
| 237 | #define CSR_PMPADDR4 0x3b4 |
| 238 | #define CSR_PMPADDR5 0x3b5 |
| 239 | #define CSR_PMPADDR6 0x3b6 |
| 240 | #define CSR_PMPADDR7 0x3b7 |
| 241 | #define CSR_PMPADDR8 0x3b8 |
| 242 | #define CSR_PMPADDR9 0x3b9 |
| 243 | #define CSR_PMPADDR10 0x3ba |
| 244 | #define CSR_PMPADDR11 0x3bb |
| 245 | #define CSR_PMPADDR12 0x3bc |
| 246 | #define CSR_PMPADDR13 0x3bd |
| 247 | #define CSR_PMPADDR14 0x3be |
| 248 | #define CSR_PMPADDR15 0x3bf |
| 249 | |
| 250 | #define CSR_TSELECT 0x7a0 |
| 251 | #define CSR_TDATA1 0x7a1 |
| 252 | #define CSR_TDATA2 0x7a2 |
| 253 | #define CSR_TDATA3 0x7a3 |
| 254 | #define CSR_DCSR 0x7b0 |
| 255 | #define CSR_DPC 0x7b1 |
| 256 | #define CSR_DSCRATCH 0x7b2 |
| 257 | |
| 258 | #define CSR_MCYCLE 0xb00 |
| 259 | #define CSR_MINSTRET 0xb02 |
| 260 | #define CSR_MHPMCOUNTER3 0xb03 |
| 261 | #define CSR_MHPMCOUNTER4 0xb04 |
| 262 | #define CSR_MHPMCOUNTER5 0xb05 |
| 263 | #define CSR_MHPMCOUNTER6 0xb06 |
| 264 | #define CSR_MHPMCOUNTER7 0xb07 |
| 265 | #define CSR_MHPMCOUNTER8 0xb08 |
| 266 | #define CSR_MHPMCOUNTER9 0xb09 |
| 267 | #define CSR_MHPMCOUNTER10 0xb0a |
| 268 | #define CSR_MHPMCOUNTER11 0xb0b |
| 269 | #define CSR_MHPMCOUNTER12 0xb0c |
| 270 | #define CSR_MHPMCOUNTER13 0xb0d |
| 271 | #define CSR_MHPMCOUNTER14 0xb0e |
| 272 | #define CSR_MHPMCOUNTER15 0xb0f |
| 273 | #define CSR_MHPMCOUNTER16 0xb10 |
| 274 | #define CSR_MHPMCOUNTER17 0xb11 |
| 275 | #define CSR_MHPMCOUNTER18 0xb12 |
| 276 | #define CSR_MHPMCOUNTER19 0xb13 |
| 277 | #define CSR_MHPMCOUNTER20 0xb14 |
| 278 | #define CSR_MHPMCOUNTER21 0xb15 |
| 279 | #define CSR_MHPMCOUNTER22 0xb16 |
| 280 | #define CSR_MHPMCOUNTER23 0xb17 |
| 281 | #define CSR_MHPMCOUNTER24 0xb18 |
| 282 | #define CSR_MHPMCOUNTER25 0xb19 |
| 283 | #define CSR_MHPMCOUNTER26 0xb1a |
| 284 | #define CSR_MHPMCOUNTER27 0xb1b |
| 285 | #define CSR_MHPMCOUNTER28 0xb1c |
| 286 | #define CSR_MHPMCOUNTER29 0xb1d |
| 287 | #define CSR_MHPMCOUNTER30 0xb1e |
| 288 | #define CSR_MHPMCOUNTER31 0xb1f |
| 289 | #define CSR_MCYCLEH 0xb80 |
| 290 | #define CSR_MINSTRETH 0xb82 |
| 291 | #define CSR_MHPMCOUNTER3H 0xb83 |
| 292 | #define CSR_MHPMCOUNTER4H 0xb84 |
| 293 | #define CSR_MHPMCOUNTER5H 0xb85 |
| 294 | #define CSR_MHPMCOUNTER6H 0xb86 |
| 295 | #define CSR_MHPMCOUNTER7H 0xb87 |
| 296 | #define CSR_MHPMCOUNTER8H 0xb88 |
| 297 | #define CSR_MHPMCOUNTER9H 0xb89 |
| 298 | #define CSR_MHPMCOUNTER10H 0xb8a |
| 299 | #define CSR_MHPMCOUNTER11H 0xb8b |
| 300 | #define CSR_MHPMCOUNTER12H 0xb8c |
| 301 | #define CSR_MHPMCOUNTER13H 0xb8d |
| 302 | #define CSR_MHPMCOUNTER14H 0xb8e |
| 303 | #define CSR_MHPMCOUNTER15H 0xb8f |
| 304 | #define CSR_MHPMCOUNTER16H 0xb90 |
| 305 | #define CSR_MHPMCOUNTER17H 0xb91 |
| 306 | #define CSR_MHPMCOUNTER18H 0xb92 |
| 307 | #define CSR_MHPMCOUNTER19H 0xb93 |
| 308 | #define CSR_MHPMCOUNTER20H 0xb94 |
| 309 | #define CSR_MHPMCOUNTER21H 0xb95 |
| 310 | #define CSR_MHPMCOUNTER22H 0xb96 |
| 311 | #define CSR_MHPMCOUNTER23H 0xb97 |
| 312 | #define CSR_MHPMCOUNTER24H 0xb98 |
| 313 | #define CSR_MHPMCOUNTER25H 0xb99 |
| 314 | #define CSR_MHPMCOUNTER26H 0xb9a |
| 315 | #define CSR_MHPMCOUNTER27H 0xb9b |
| 316 | #define CSR_MHPMCOUNTER28H 0xb9c |
| 317 | #define CSR_MHPMCOUNTER29H 0xb9d |
| 318 | #define CSR_MHPMCOUNTER30H 0xb9e |
| 319 | #define CSR_MHPMCOUNTER31H 0xb9f |
| 320 | |
| 321 | #define CSR_CYCLE 0xc00 |
| 322 | #define CSR_TIME 0xc01 |
| 323 | #define CSR_INSTRET 0xc02 |
| 324 | #define CSR_HPMCOUNTER3 0xc03 |
| 325 | #define CSR_HPMCOUNTER4 0xc04 |
| 326 | #define CSR_HPMCOUNTER5 0xc05 |
| 327 | #define CSR_HPMCOUNTER6 0xc06 |
| 328 | #define CSR_HPMCOUNTER7 0xc07 |
| 329 | #define CSR_HPMCOUNTER8 0xc08 |
| 330 | #define CSR_HPMCOUNTER9 0xc09 |
| 331 | #define CSR_HPMCOUNTER10 0xc0a |
| 332 | #define CSR_HPMCOUNTER11 0xc0b |
| 333 | #define CSR_HPMCOUNTER12 0xc0c |
| 334 | #define CSR_HPMCOUNTER13 0xc0d |
| 335 | #define CSR_HPMCOUNTER14 0xc0e |
| 336 | #define CSR_HPMCOUNTER15 0xc0f |
| 337 | #define CSR_HPMCOUNTER16 0xc10 |
| 338 | #define CSR_HPMCOUNTER17 0xc11 |
| 339 | #define CSR_HPMCOUNTER18 0xc12 |
| 340 | #define CSR_HPMCOUNTER19 0xc13 |
| 341 | #define CSR_HPMCOUNTER20 0xc14 |
| 342 | #define CSR_HPMCOUNTER21 0xc15 |
| 343 | #define CSR_HPMCOUNTER22 0xc16 |
| 344 | #define CSR_HPMCOUNTER23 0xc17 |
| 345 | #define CSR_HPMCOUNTER24 0xc18 |
| 346 | #define CSR_HPMCOUNTER25 0xc19 |
| 347 | #define CSR_HPMCOUNTER26 0xc1a |
| 348 | #define CSR_HPMCOUNTER27 0xc1b |
| 349 | #define CSR_HPMCOUNTER28 0xc1c |
| 350 | #define CSR_HPMCOUNTER29 0xc1d |
| 351 | #define CSR_HPMCOUNTER30 0xc1e |
| 352 | #define CSR_HPMCOUNTER31 0xc1f |
| 353 | #define CSR_CYCLEH 0xc80 |
| 354 | #define CSR_TIMEH 0xc81 |
| 355 | #define CSR_INSTRETH 0xc82 |
| 356 | #define CSR_HPMCOUNTER3H 0xc83 |
| 357 | #define CSR_HPMCOUNTER4H 0xc84 |
| 358 | #define CSR_HPMCOUNTER5H 0xc85 |
| 359 | #define CSR_HPMCOUNTER6H 0xc86 |
| 360 | #define CSR_HPMCOUNTER7H 0xc87 |
| 361 | #define CSR_HPMCOUNTER8H 0xc88 |
| 362 | #define CSR_HPMCOUNTER9H 0xc89 |
| 363 | #define CSR_HPMCOUNTER10H 0xc8a |
| 364 | #define CSR_HPMCOUNTER11H 0xc8b |
| 365 | #define CSR_HPMCOUNTER12H 0xc8c |
| 366 | #define CSR_HPMCOUNTER13H 0xc8d |
| 367 | #define CSR_HPMCOUNTER14H 0xc8e |
| 368 | #define CSR_HPMCOUNTER15H 0xc8f |
| 369 | #define CSR_HPMCOUNTER16H 0xc90 |
| 370 | #define CSR_HPMCOUNTER17H 0xc91 |
| 371 | #define CSR_HPMCOUNTER18H 0xc92 |
| 372 | #define CSR_HPMCOUNTER19H 0xc93 |
| 373 | #define CSR_HPMCOUNTER20H 0xc94 |
| 374 | #define CSR_HPMCOUNTER21H 0xc95 |
| 375 | #define CSR_HPMCOUNTER22H 0xc96 |
| 376 | #define CSR_HPMCOUNTER23H 0xc97 |
| 377 | #define CSR_HPMCOUNTER24H 0xc98 |
| 378 | #define CSR_HPMCOUNTER25H 0xc99 |
| 379 | #define CSR_HPMCOUNTER26H 0xc9a |
| 380 | #define CSR_HPMCOUNTER27H 0xc9b |
| 381 | #define CSR_HPMCOUNTER28H 0xc9c |
| 382 | #define CSR_HPMCOUNTER29H 0xc9d |
| 383 | #define CSR_HPMCOUNTER30H 0xc9e |
| 384 | #define CSR_HPMCOUNTER31H 0xc9f |
| 385 | |
| 386 | #define CSR_MVENDORID 0xf11 |
| 387 | #define CSR_MARCHID 0xf12 |
| 388 | #define CSR_MIMPID 0xf13 |
| 389 | #define CSR_MHARTID 0xf14 |
| 390 | |
Bin Meng | 748dae2 | 2018-09-26 06:55:15 -0700 | [diff] [blame] | 391 | #endif /* __riscv */ |
Rick Chen | 76c0a24 | 2017-12-26 13:55:51 +0800 | [diff] [blame] | 392 | |
Bin Meng | 748dae2 | 2018-09-26 06:55:15 -0700 | [diff] [blame] | 393 | #endif /* RISCV_CSR_ENCODING_H */ |