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Jagannadha Sutradharudu Tekifc0d22b2014-01-09 01:48:29 +05301/*
2 * Xilinx ZC770 XM012 board DTS
3 *
Michal Simek1b27e662015-07-22 11:36:32 +02004 * Copyright (C) 2013 - 2015 Xilinx, Inc.
Jagannadha Sutradharudu Tekifc0d22b2014-01-09 01:48:29 +05305 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8/dts-v1/;
9#include "zynq-7000.dtsi"
10
11/ {
Jagannadha Sutradharudu Tekifc0d22b2014-01-09 01:48:29 +053012 compatible = "xlnx,zynq-zc770-xm012", "xlnx,zynq-7000";
Michal Simek1b27e662015-07-22 11:36:32 +020013 model = "Xilinx Zynq";
Masahiro Yamadad6367a22014-05-15 20:37:54 +090014
Masahiro Yamada87f645e2014-05-15 20:37:55 +090015 aliases {
Michal Simek1b27e662015-07-22 11:36:32 +020016 i2c0 = &i2c0;
17 i2c1 = &i2c1;
Masahiro Yamada87f645e2014-05-15 20:37:55 +090018 serial0 = &uart1;
Michal Simek1b27e662015-07-22 11:36:32 +020019 spi0 = &spi1;
Masahiro Yamada87f645e2014-05-15 20:37:55 +090020 };
21
Michal Simek1b27e662015-07-22 11:36:32 +020022 chosen {
Michal Simek8073b862016-04-07 11:15:00 +020023 bootargs = "";
Michal Simekc9af95a2016-01-12 13:56:44 +010024 stdout-path = "serial0:115200n8";
Michal Simek1b27e662015-07-22 11:36:32 +020025 };
26
Michal Simekb3585f42016-11-11 13:11:37 +010027 memory@0 {
Masahiro Yamadad6367a22014-05-15 20:37:54 +090028 device_type = "memory";
Michal Simek1b27e662015-07-22 11:36:32 +020029 reg = <0x0 0x40000000>;
Masahiro Yamadad6367a22014-05-15 20:37:54 +090030 };
Jagannadha Sutradharudu Tekifc0d22b2014-01-09 01:48:29 +053031};
Michal Simek1b27e662015-07-22 11:36:32 +020032
Michal Simek1b27e662015-07-22 11:36:32 +020033&can1 {
34 status = "okay";
35};
36
37&i2c0 {
38 status = "okay";
39 clock-frequency = <400000>;
40
41 m24c02_eeprom@52 {
42 compatible = "at,24c02";
43 reg = <0x52>;
44 };
45};
46
47&i2c1 {
48 status = "okay";
49 clock-frequency = <400000>;
50
51 m24c02_eeprom@52 {
52 compatible = "at,24c02";
53 reg = <0x52>;
54 };
55};
56
Michal Simek49f44b92016-01-14 13:09:16 +010057&spi1 {
58 status = "okay";
59 num-cs = <4>;
60 is-decoded-cs = <0>;
61};
62
Michal Simek1b27e662015-07-22 11:36:32 +020063&uart1 {
Simon Glass8c7323a2015-10-17 19:41:24 -060064 u-boot,dm-pre-reloc;
Michal Simek1b27e662015-07-22 11:36:32 +020065 status = "okay";
66};