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git01.mediatek.com / filogic / uboot / 8c7323a2036985dd9f63ef143d910506edc443bc / . / arch / arm / dts / zynq-zc770-xm012.dts
blob: 3e1769acb51f994c20a85f9353efc450563560aa [file] [log] [blame]
Jagannadha Sutradharudu Tekifc0d22b2014-01-09 01:48:29 +0530[diff] [blame]1/*
2 * Xilinx ZC770 XM012 board DTS
3 *
Michal Simek1b27e662015-07-22 11:36:32 +0200[diff] [blame]4 * Copyright (C) 2013 - 2015 Xilinx, Inc.
Jagannadha Sutradharudu Tekifc0d22b2014-01-09 01:48:29 +0530[diff] [blame]5 *
6 * SPDX-License-Identifier: GPL-2.0+
7 */
8/dts-v1/;
9#include "zynq-7000.dtsi"
10
11/ {
Jagannadha Sutradharudu Tekifc0d22b2014-01-09 01:48:29 +0530[diff] [blame]12 compatible = "xlnx,zynq-zc770-xm012", "xlnx,zynq-7000";
Michal Simek1b27e662015-07-22 11:36:32 +0200[diff] [blame]13 model = "Xilinx Zynq";
Masahiro Yamadad6367a22014-05-15 20:37:54 +0900[diff] [blame]14
Masahiro Yamada87f645e2014-05-15 20:37:55 +0900[diff] [blame]15 aliases {
Michal Simek1b27e662015-07-22 11:36:32 +0200[diff] [blame]16 i2c0 = &i2c0;
17 i2c1 = &i2c1;
Masahiro Yamada87f645e2014-05-15 20:37:55 +0900[diff] [blame]18 serial0 = &uart1;
Michal Simek1b27e662015-07-22 11:36:32 +0200[diff] [blame]19 spi0 = &spi1;
Masahiro Yamada87f645e2014-05-15 20:37:55 +0900[diff] [blame]20 };
21
Michal Simek1b27e662015-07-22 11:36:32 +0200[diff] [blame]22 chosen {
23 bootargs = "console=ttyPS0,115200 root=/dev/ram rw earlyprintk";
24 linux,stdout-path = &uart1;
25 stdout-path = &uart1;
26 };
27
Michal Simeka8d362f2015-08-12 11:25:05 +0200[diff] [blame]28 memory {
Masahiro Yamadad6367a22014-05-15 20:37:54 +0900[diff] [blame]29 device_type = "memory";
Michal Simek1b27e662015-07-22 11:36:32 +0200[diff] [blame]30 reg = <0x0 0x40000000>;
Masahiro Yamadad6367a22014-05-15 20:37:54 +0900[diff] [blame]31 };
Jagannadha Sutradharudu Tekifc0d22b2014-01-09 01:48:29 +0530[diff] [blame]32};
Michal Simek1b27e662015-07-22 11:36:32 +0200[diff] [blame]33
34&spi1 {
35 status = "okay";
36 num-cs = <4>;
37 is-decoded-cs = <0>;
38};
39
40&can1 {
41 status = "okay";
42};
43
44&i2c0 {
45 status = "okay";
46 clock-frequency = <400000>;
47
48 m24c02_eeprom@52 {
49 compatible = "at,24c02";
50 reg = <0x52>;
51 };
52};
53
54&i2c1 {
55 status = "okay";
56 clock-frequency = <400000>;
57
58 m24c02_eeprom@52 {
59 compatible = "at,24c02";
60 reg = <0x52>;
61 };
62};
63
64&uart1 {
Simon Glass8c7323a2015-10-17 19:41:24 -0600[diff] [blame^]65 u-boot,dm-pre-reloc;
Michal Simek1b27e662015-07-22 11:36:32 +0200[diff] [blame]66 status = "okay";
67};