Aleksandar Gerasimovski | 032bdbc | 2021-02-22 18:18:11 +0000 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * Copyright 2020 Hitachi Power Grids. All rights reserved. |
| 4 | */ |
| 5 | |
| 6 | #include <common.h> |
| 7 | #include <i2c.h> |
| 8 | #include <asm/io.h> |
| 9 | #include <asm/arch/immap_ls102xa.h> |
| 10 | #include <asm/arch/clock.h> |
| 11 | #include <asm/arch/fsl_serdes.h> |
| 12 | #include <asm/arch/ls102xa_devdis.h> |
| 13 | #include <asm/arch/ls102xa_soc.h> |
| 14 | #include <hwconfig.h> |
| 15 | #include <mmc.h> |
| 16 | #include <fsl_csu.h> |
| 17 | #include <fsl_esdhc.h> |
| 18 | #include <fsl_ifc.h> |
| 19 | #include <fsl_immap.h> |
| 20 | #include <netdev.h> |
| 21 | #include <fsl_mdio.h> |
| 22 | #include <tsec.h> |
| 23 | #include <fsl_sec.h> |
| 24 | #include <fsl_devdis.h> |
| 25 | #include <fsl_ddr.h> |
| 26 | #include <spl.h> |
| 27 | #include <fdt_support.h> |
| 28 | #include <fsl_qe.h> |
| 29 | #include <fsl_validate.h> |
| 30 | |
| 31 | #include "../common/common.h" |
| 32 | #include "../common/qrio.h" |
| 33 | |
| 34 | DECLARE_GLOBAL_DATA_PTR; |
| 35 | |
| 36 | static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN]; |
| 37 | |
| 38 | int checkboard(void) |
| 39 | { |
| 40 | show_qrio(); |
| 41 | |
| 42 | return 0; |
| 43 | } |
| 44 | |
| 45 | int dram_init(void) |
| 46 | { |
| 47 | return fsl_initdram(); |
| 48 | } |
| 49 | |
| 50 | int board_early_init_f(void) |
| 51 | { |
| 52 | struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; |
| 53 | struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; |
| 54 | struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL}; |
| 55 | |
| 56 | /* Disable unused MCK1 */ |
| 57 | setbits_be32(&gur->ddrclkdr, 2); |
| 58 | |
| 59 | /* IFC Global Configuration */ |
| 60 | setbits_be32(&ifc.gregs->ifc_gcr, 12 << IFC_GCR_TBCTL_TRN_TIME_SHIFT); |
| 61 | setbits_be32(&ifc.gregs->ifc_ccr, IFC_CCR_CLK_DIV(3) | |
| 62 | IFC_CCR_INV_CLK_EN); |
| 63 | |
| 64 | /* clear BD & FR bits for BE BD's and frame data */ |
| 65 | clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR); |
| 66 | out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125); |
| 67 | |
| 68 | init_early_memctl_regs(); |
| 69 | |
| 70 | /* QRIO Configuration */ |
| 71 | qrio_uprstreq(UPREQ_CORE_RST); |
| 72 | |
Aleksandar Gerasimovski | 3b24bbd | 2021-06-08 14:16:28 +0000 | [diff] [blame] | 73 | #if CONFIG_IS_ENABLED(TARGET_PG_WCOM_SELI8) |
| 74 | qrio_prstcfg(KM_LIU_RST, PRSTCFG_POWUP_UNIT_RST); |
| 75 | qrio_wdmask(KM_LIU_RST, true); |
Aleksandar Gerasimovski | 032bdbc | 2021-02-22 18:18:11 +0000 | [diff] [blame] | 76 | |
Aleksandar Gerasimovski | 3b24bbd | 2021-06-08 14:16:28 +0000 | [diff] [blame] | 77 | qrio_prstcfg(KM_PAXK_RST, PRSTCFG_POWUP_UNIT_RST); |
| 78 | qrio_wdmask(KM_PAXK_RST, true); |
| 79 | #endif |
| 80 | |
| 81 | #if CONFIG_IS_ENABLED(TARGET_PG_WCOM_EXPU1) |
| 82 | qrio_prstcfg(WCOM_TMG_RST, PRSTCFG_POWUP_UNIT_RST); |
| 83 | qrio_wdmask(WCOM_TMG_RST, true); |
| 84 | |
| 85 | qrio_prstcfg(WCOM_PHY_RST, PRSTCFG_POWUP_UNIT_RST); |
| 86 | qrio_prst(WCOM_PHY_RST, false, false); |
| 87 | |
| 88 | qrio_prstcfg(WCOM_QSFP_RST, PRSTCFG_POWUP_UNIT_RST); |
| 89 | qrio_wdmask(WCOM_QSFP_RST, true); |
Aleksandar Gerasimovski | 032bdbc | 2021-02-22 18:18:11 +0000 | [diff] [blame] | 90 | |
Aleksandar Gerasimovski | 3b24bbd | 2021-06-08 14:16:28 +0000 | [diff] [blame] | 91 | qrio_prstcfg(WCOM_CLIPS_RST, PRSTCFG_POWUP_UNIT_RST); |
| 92 | qrio_prst(WCOM_CLIPS_RST, false, false); |
| 93 | #endif |
Aleksandar Gerasimovski | 3651431 | 2021-11-16 12:51:47 +0000 | [diff] [blame] | 94 | |
| 95 | /* deasset debug phy reset only if piggy is present */ |
Aleksandar Gerasimovski | 3b24bbd | 2021-06-08 14:16:28 +0000 | [diff] [blame] | 96 | qrio_prstcfg(KM_DBG_ETH_RST, PRSTCFG_POWUP_UNIT_CORE_RST); |
Aleksandar Gerasimovski | 3651431 | 2021-11-16 12:51:47 +0000 | [diff] [blame] | 97 | qrio_prst(KM_DBG_ETH_RST, !qrio_get_pgy_pres_pin(), false); |
Aleksandar Gerasimovski | 032bdbc | 2021-02-22 18:18:11 +0000 | [diff] [blame] | 98 | |
| 99 | i2c_deblock_gpio_cfg(); |
| 100 | |
Aleksandar Gerasimovski | 8e26562 | 2021-06-08 14:24:32 +0000 | [diff] [blame] | 101 | /* enable the Unit LED (red) & Boot LED (on) */ |
| 102 | qrio_set_leds(); |
| 103 | |
| 104 | /* enable Application Buffer */ |
| 105 | qrio_enable_app_buffer(); |
| 106 | |
Aleksandar Gerasimovski | 032bdbc | 2021-02-22 18:18:11 +0000 | [diff] [blame] | 107 | arch_soc_init(); |
| 108 | |
| 109 | return 0; |
| 110 | } |
| 111 | |
Aleksandar Gerasimovski | 1cc133d | 2021-12-10 11:08:44 +0100 | [diff] [blame] | 112 | int misc_init_f(void) |
| 113 | { |
| 114 | if (IS_ENABLED(CONFIG_PG_WCOM_UBOOT_UPDATE_SUPPORTED)) |
| 115 | check_for_uboot_update(); |
| 116 | return 0; |
| 117 | } |
| 118 | |
Aleksandar Gerasimovski | 032bdbc | 2021-02-22 18:18:11 +0000 | [diff] [blame] | 119 | int board_init(void) |
| 120 | { |
| 121 | if (IS_ENABLED(CONFIG_SYS_FSL_ERRATUM_A010315)) |
| 122 | erratum_a010315(); |
| 123 | |
| 124 | fsl_serdes_init(); |
| 125 | |
| 126 | ls102xa_smmu_stream_id_init(); |
| 127 | |
| 128 | u_qe_init(); |
| 129 | |
| 130 | return 0; |
| 131 | } |
| 132 | |
| 133 | int board_late_init(void) |
| 134 | { |
| 135 | return 0; |
| 136 | } |
| 137 | |
| 138 | int misc_init_r(void) |
| 139 | { |
Aleksandar Gerasimovski | fcaaa4f | 2021-11-16 13:06:31 +0000 | [diff] [blame] | 140 | device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl)); |
Aleksandar Gerasimovski | 032bdbc | 2021-02-22 18:18:11 +0000 | [diff] [blame] | 141 | |
| 142 | ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN, |
| 143 | CONFIG_PIGGY_MAC_ADDRESS_OFFSET); |
| 144 | |
| 145 | return 0; |
| 146 | } |
| 147 | |
| 148 | int ft_board_setup(void *blob, struct bd_info *bd) |
| 149 | { |
| 150 | ft_cpu_setup(blob, bd); |
| 151 | |
| 152 | if (IS_ENABLED(CONFIG_PCI)) |
| 153 | ft_pci_setup(blob, bd); |
| 154 | |
| 155 | return 0; |
| 156 | } |
| 157 | |
Aleksandar Gerasimovski | bece73e | 2021-06-08 14:17:34 +0000 | [diff] [blame] | 158 | #if defined(CONFIG_POST) |
| 159 | int post_hotkeys_pressed(void) |
| 160 | { |
Aleksandar Gerasimovski | 83a4baa | 2021-11-16 12:49:46 +0000 | [diff] [blame] | 161 | /* DIC26_SELFTEST: QRIO, SLFTEST */ |
| 162 | return qrio_get_selftest_pin(); |
Aleksandar Gerasimovski | bece73e | 2021-06-08 14:17:34 +0000 | [diff] [blame] | 163 | } |
| 164 | |
Aleksandar Gerasimovski | f4993e8 | 2021-11-16 13:13:35 +0000 | [diff] [blame] | 165 | /* POST word is located in the unused SCRATCHRW4 register */ |
| 166 | #define CCSR_SCRATCHRW4_ADDR 0x1ee020c |
| 167 | |
Aleksandar Gerasimovski | bece73e | 2021-06-08 14:17:34 +0000 | [diff] [blame] | 168 | ulong post_word_load(void) |
| 169 | { |
Aleksandar Gerasimovski | f4993e8 | 2021-11-16 13:13:35 +0000 | [diff] [blame] | 170 | void *addr = (void *)CCSR_SCRATCHRW4_ADDR; |
Aleksandar Gerasimovski | bece73e | 2021-06-08 14:17:34 +0000 | [diff] [blame] | 171 | return in_le32(addr); |
| 172 | } |
| 173 | |
| 174 | void post_word_store(ulong value) |
| 175 | { |
Aleksandar Gerasimovski | f4993e8 | 2021-11-16 13:13:35 +0000 | [diff] [blame] | 176 | void *addr = (void *)CCSR_SCRATCHRW4_ADDR; |
Aleksandar Gerasimovski | bece73e | 2021-06-08 14:17:34 +0000 | [diff] [blame] | 177 | out_le32(addr, value); |
| 178 | } |
| 179 | |
| 180 | int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset) |
| 181 | { |
| 182 | /* Define only 1MiB range for mem_regions at the middle of the RAM */ |
| 183 | /* For 1GiB range mem_regions takes approx. 4min */ |
| 184 | *vstart = CONFIG_SYS_SDRAM_BASE + (gd->ram_size >> 1); |
| 185 | *size = 1 << 20; |
| 186 | return 0; |
| 187 | } |
| 188 | #endif |
| 189 | |
Aleksandar Gerasimovski | 032bdbc | 2021-02-22 18:18:11 +0000 | [diff] [blame] | 190 | u8 flash_read8(void *addr) |
| 191 | { |
| 192 | return __raw_readb(addr + 1); |
| 193 | } |
| 194 | |
| 195 | void flash_write16(u16 val, void *addr) |
| 196 | { |
| 197 | u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00)); |
| 198 | |
| 199 | __raw_writew(shftval, addr); |
| 200 | } |
| 201 | |
| 202 | u16 flash_read16(void *addr) |
| 203 | { |
| 204 | u16 val = __raw_readw(addr); |
| 205 | |
| 206 | return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00); |
| 207 | } |
| 208 | |
| 209 | int hush_init_var(void) |
| 210 | { |
| 211 | ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN); |
| 212 | return 0; |
| 213 | } |
| 214 | |
| 215 | int last_stage_init(void) |
| 216 | { |
| 217 | set_km_env(); |
| 218 | return 0; |
| 219 | } |