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wdenk324f6cf2002-10-07 21:13:39 +00001/*
2 * (C) Copyright 2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenk9dfa8d12002-12-08 09:53:23 +00006 *
7 * Be sure to mark tests to be run before relocation as such with the
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +02008 * CONFIG_SYS_POST_PREREL flag so that logging is done correctly if the
wdenk9dfa8d12002-12-08 09:53:23 +00009 * logbuffer support is enabled.
wdenk324f6cf2002-10-07 21:13:39 +000010 */
11
12#include <common.h>
13
wdenk324f6cf2002-10-07 21:13:39 +000014#include <post.h>
15
Yuri Tikhonovc3655b82008-05-08 15:42:47 +020016extern int ocm_post_test (int flags);
wdenk324f6cf2002-10-07 21:13:39 +000017extern int cache_post_test (int flags);
18extern int watchdog_post_test (int flags);
19extern int i2c_post_test (int flags);
20extern int rtc_post_test (int flags);
21extern int memory_post_test (int flags);
22extern int cpu_post_test (int flags);
Igor Lisitsin95bcd382007-03-28 19:06:19 +040023extern int fpu_post_test (int flags);
wdenk324f6cf2002-10-07 21:13:39 +000024extern int uart_post_test (int flags);
25extern int ether_post_test (int flags);
26extern int spi_post_test (int flags);
27extern int usb_post_test (int flags);
28extern int spr_post_test (int flags);
wdenkc08f1582003-04-27 22:52:51 +000029extern int sysmon_post_test (int flags);
wdenk61642172004-04-15 21:16:42 +000030extern int dsp_post_test (int flags);
wdenkc4e854f2004-06-07 23:46:25 +000031extern int codec_post_test (int flags);
Pavel Kolesnikov5d896112007-07-20 15:03:03 +020032extern int ecc_post_test (int flags);
Mike Frysinger813531f2011-05-10 13:35:40 +000033extern int flash_post_test(int flags);
wdenkc08f1582003-04-27 22:52:51 +000034
Yuri Tikhonovc147d482008-02-04 14:10:42 +010035extern int dspic_init_post_test (int flags);
36extern int dspic_post_test (int flags);
37extern int gdc_post_test (int flags);
38extern int fpga_post_test (int flags);
39extern int lwmon5_watchdog_post_test(int flags);
40extern int sysmon1_post_test(int flags);
Anatolij Gustschin810b2072010-04-24 19:27:11 +020041extern int coprocessor_post_test(int flags);
Mike Frysinger32ed1fe2011-05-10 16:22:25 -040042extern int led_post_test(int flags);
43extern int button_post_test(int flags);
Valentin Longchamp24db42a2011-09-12 04:18:40 +000044extern int memory_regions_post_test(int flags);
Yuri Tikhonovc147d482008-02-04 14:10:42 +010045
wdenkc08f1582003-04-27 22:52:51 +000046extern int sysmon_init_f (void);
47
48extern void sysmon_reloc (void);
49
wdenk324f6cf2002-10-07 21:13:39 +000050
51struct post_test post_list[] =
52{
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020053#if CONFIG_POST & CONFIG_SYS_POST_OCM
Yuri Tikhonovc3655b82008-05-08 15:42:47 +020054 {
55 "OCM test",
56 "ocm",
57 "This test checks on chip memory (OCM).",
Yuri Tikhonov9c667bf2008-05-08 15:46:02 +020058 POST_ROM | POST_ALWAYS | POST_PREREL | POST_CRITICAL | POST_STOP,
Yuri Tikhonovc3655b82008-05-08 15:42:47 +020059 &ocm_post_test,
60 NULL,
61 NULL,
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020062 CONFIG_SYS_POST_OCM
Yuri Tikhonovc3655b82008-05-08 15:42:47 +020063 },
64#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020065#if CONFIG_POST & CONFIG_SYS_POST_CACHE
wdenk324f6cf2002-10-07 21:13:39 +000066 {
wdenk57b2d802003-06-27 21:31:46 +000067 "Cache test",
68 "cache",
69 "This test verifies the CPU cache operation.",
70 POST_RAM | POST_ALWAYS,
71 &cache_post_test,
72 NULL,
73 NULL,
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020074 CONFIG_SYS_POST_CACHE
wdenk324f6cf2002-10-07 21:13:39 +000075 },
76#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020077#if CONFIG_POST & CONFIG_SYS_POST_WATCHDOG
Yuri Tikhonovc147d482008-02-04 14:10:42 +010078#if defined(CONFIG_POST_WATCHDOG)
79 CONFIG_POST_WATCHDOG,
80#else
wdenk324f6cf2002-10-07 21:13:39 +000081 {
wdenk57b2d802003-06-27 21:31:46 +000082 "Watchdog timer test",
83 "watchdog",
84 "This test checks the watchdog timer.",
wdenkdccbda02003-07-14 22:13:32 +000085 POST_RAM | POST_POWERON | POST_SLOWTEST | POST_MANUAL | POST_REBOOT,
wdenk57b2d802003-06-27 21:31:46 +000086 &watchdog_post_test,
87 NULL,
88 NULL,
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020089 CONFIG_SYS_POST_WATCHDOG
wdenk324f6cf2002-10-07 21:13:39 +000090 },
91#endif
Yuri Tikhonovc147d482008-02-04 14:10:42 +010092#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020093#if CONFIG_POST & CONFIG_SYS_POST_I2C
wdenk324f6cf2002-10-07 21:13:39 +000094 {
wdenk57b2d802003-06-27 21:31:46 +000095 "I2C test",
96 "i2c",
97 "This test verifies the I2C operation.",
98 POST_RAM | POST_ALWAYS,
99 &i2c_post_test,
100 NULL,
101 NULL,
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200102 CONFIG_SYS_POST_I2C
wdenk324f6cf2002-10-07 21:13:39 +0000103 },
104#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200105#if CONFIG_POST & CONFIG_SYS_POST_RTC
wdenk324f6cf2002-10-07 21:13:39 +0000106 {
wdenk57b2d802003-06-27 21:31:46 +0000107 "RTC test",
108 "rtc",
109 "This test verifies the RTC operation.",
wdenkdccbda02003-07-14 22:13:32 +0000110 POST_RAM | POST_SLOWTEST | POST_MANUAL,
wdenk57b2d802003-06-27 21:31:46 +0000111 &rtc_post_test,
112 NULL,
113 NULL,
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200114 CONFIG_SYS_POST_RTC
wdenk324f6cf2002-10-07 21:13:39 +0000115 },
116#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200117#if CONFIG_POST & CONFIG_SYS_POST_MEMORY
wdenk324f6cf2002-10-07 21:13:39 +0000118 {
wdenk57b2d802003-06-27 21:31:46 +0000119 "Memory test",
120 "memory",
121 "This test checks RAM.",
wdenkdccbda02003-07-14 22:13:32 +0000122 POST_ROM | POST_POWERON | POST_SLOWTEST | POST_PREREL,
wdenk57b2d802003-06-27 21:31:46 +0000123 &memory_post_test,
124 NULL,
125 NULL,
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200126 CONFIG_SYS_POST_MEMORY
wdenk324f6cf2002-10-07 21:13:39 +0000127 },
128#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200129#if CONFIG_POST & CONFIG_SYS_POST_CPU
wdenk324f6cf2002-10-07 21:13:39 +0000130 {
wdenk57b2d802003-06-27 21:31:46 +0000131 "CPU test",
132 "cpu",
133 "This test verifies the arithmetic logic unit of"
134 " CPU.",
135 POST_RAM | POST_ALWAYS,
136 &cpu_post_test,
137 NULL,
138 NULL,
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200139 CONFIG_SYS_POST_CPU
wdenk324f6cf2002-10-07 21:13:39 +0000140 },
141#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200142#if CONFIG_POST & CONFIG_SYS_POST_FPU
Igor Lisitsin95bcd382007-03-28 19:06:19 +0400143 {
144 "FPU test",
145 "fpu",
146 "This test verifies the arithmetic logic unit of"
147 " FPU.",
148 POST_RAM | POST_ALWAYS,
149 &fpu_post_test,
150 NULL,
151 NULL,
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200152 CONFIG_SYS_POST_FPU
Igor Lisitsin95bcd382007-03-28 19:06:19 +0400153 },
154#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200155#if CONFIG_POST & CONFIG_SYS_POST_UART
Stefan Roese770b00b2010-10-07 14:16:25 +0200156#if defined(CONFIG_POST_UART)
157 CONFIG_POST_UART,
158#else
wdenk324f6cf2002-10-07 21:13:39 +0000159 {
wdenk57b2d802003-06-27 21:31:46 +0000160 "UART test",
161 "uart",
162 "This test verifies the UART operation.",
wdenkdccbda02003-07-14 22:13:32 +0000163 POST_RAM | POST_SLOWTEST | POST_MANUAL,
wdenk57b2d802003-06-27 21:31:46 +0000164 &uart_post_test,
165 NULL,
166 NULL,
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200167 CONFIG_SYS_POST_UART
wdenk324f6cf2002-10-07 21:13:39 +0000168 },
Stefan Roese770b00b2010-10-07 14:16:25 +0200169#endif /* CONFIG_POST_UART */
wdenk324f6cf2002-10-07 21:13:39 +0000170#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200171#if CONFIG_POST & CONFIG_SYS_POST_ETHER
wdenk324f6cf2002-10-07 21:13:39 +0000172 {
wdenk57b2d802003-06-27 21:31:46 +0000173 "ETHERNET test",
174 "ethernet",
175 "This test verifies the ETHERNET operation.",
Robert P. J. Day15bdcaf2016-03-27 10:18:55 -0400176 POST_RAM | POST_ALWAYS,
wdenk57b2d802003-06-27 21:31:46 +0000177 &ether_post_test,
178 NULL,
179 NULL,
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200180 CONFIG_SYS_POST_ETHER
wdenk324f6cf2002-10-07 21:13:39 +0000181 },
182#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200183#if CONFIG_POST & CONFIG_SYS_POST_USB
wdenk324f6cf2002-10-07 21:13:39 +0000184 {
wdenk57b2d802003-06-27 21:31:46 +0000185 "USB test",
186 "usb",
187 "This test verifies the USB operation.",
Robert P. J. Day15bdcaf2016-03-27 10:18:55 -0400188 POST_RAM | POST_ALWAYS,
wdenk57b2d802003-06-27 21:31:46 +0000189 &usb_post_test,
190 NULL,
191 NULL,
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200192 CONFIG_SYS_POST_USB
wdenk324f6cf2002-10-07 21:13:39 +0000193 },
194#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200195#if CONFIG_POST & CONFIG_SYS_POST_SPR
wdenk324f6cf2002-10-07 21:13:39 +0000196 {
wdenk57b2d802003-06-27 21:31:46 +0000197 "SPR test",
198 "spr",
199 "This test checks SPR contents.",
Stefan Roese191a8dc2008-01-09 10:38:58 +0100200 POST_RAM | POST_ALWAYS,
wdenk57b2d802003-06-27 21:31:46 +0000201 &spr_post_test,
202 NULL,
203 NULL,
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200204 CONFIG_SYS_POST_SPR
wdenk324f6cf2002-10-07 21:13:39 +0000205 },
206#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200207#if CONFIG_POST & CONFIG_SYS_POST_SYSMON
wdenkc08f1582003-04-27 22:52:51 +0000208 {
wdenk57b2d802003-06-27 21:31:46 +0000209 "SYSMON test",
210 "sysmon",
211 "This test monitors system hardware.",
212 POST_RAM | POST_ALWAYS,
213 &sysmon_post_test,
214 &sysmon_init_f,
215 &sysmon_reloc,
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200216 CONFIG_SYS_POST_SYSMON
wdenkc08f1582003-04-27 22:52:51 +0000217 },
218#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200219#if CONFIG_POST & CONFIG_SYS_POST_DSP
wdenk61642172004-04-15 21:16:42 +0000220 {
221 "DSP test",
222 "dsp",
223 "This test checks any connected DSP(s).",
Robert P. J. Day15bdcaf2016-03-27 10:18:55 -0400224 POST_RAM | POST_ALWAYS,
wdenk61642172004-04-15 21:16:42 +0000225 &dsp_post_test,
226 NULL,
227 NULL,
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200228 CONFIG_SYS_POST_DSP
wdenk61642172004-04-15 21:16:42 +0000229 },
230#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200231#if CONFIG_POST & CONFIG_SYS_POST_CODEC
wdenkc4e854f2004-06-07 23:46:25 +0000232 {
233 "CODEC test",
234 "codec",
235 "This test checks any connected codec(s).",
236 POST_RAM | POST_MANUAL,
237 &codec_post_test,
238 NULL,
239 NULL,
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200240 CONFIG_SYS_POST_CODEC
wdenkc4e854f2004-06-07 23:46:25 +0000241 },
242#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200243#if CONFIG_POST & CONFIG_SYS_POST_ECC
Pavel Kolesnikov5d896112007-07-20 15:03:03 +0200244 {
245 "ECC test",
246 "ecc",
Larry Johnsonc2abd6e2008-01-12 23:35:33 -0500247 "This test checks the ECC facility of memory.",
248 POST_ROM | POST_ALWAYS | POST_PREREL,
Pavel Kolesnikov5d896112007-07-20 15:03:03 +0200249 &ecc_post_test,
250 NULL,
251 NULL,
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200252 CONFIG_SYS_POST_ECC
Pavel Kolesnikov5d896112007-07-20 15:03:03 +0200253 },
254#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200255#if CONFIG_POST & CONFIG_SYS_POST_BSPEC1
Yuri Tikhonovc147d482008-02-04 14:10:42 +0100256 CONFIG_POST_BSPEC1,
257#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200258#if CONFIG_POST & CONFIG_SYS_POST_BSPEC2
Yuri Tikhonovc147d482008-02-04 14:10:42 +0100259 CONFIG_POST_BSPEC2,
260#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200261#if CONFIG_POST & CONFIG_SYS_POST_BSPEC3
Yuri Tikhonovc147d482008-02-04 14:10:42 +0100262 CONFIG_POST_BSPEC3,
263#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200264#if CONFIG_POST & CONFIG_SYS_POST_BSPEC4
Yuri Tikhonovc147d482008-02-04 14:10:42 +0100265 CONFIG_POST_BSPEC4,
266#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200267#if CONFIG_POST & CONFIG_SYS_POST_BSPEC5
Yuri Tikhonovc147d482008-02-04 14:10:42 +0100268 CONFIG_POST_BSPEC5,
269#endif
Anatolij Gustschin810b2072010-04-24 19:27:11 +0200270#if CONFIG_POST & CONFIG_SYS_POST_COPROC
271 {
272 "Coprocessors communication test",
273 "coproc_com",
274 "This test checks communication with coprocessors.",
275 POST_RAM | POST_ALWAYS | POST_CRITICAL,
276 &coprocessor_post_test,
277 NULL,
278 NULL,
279 CONFIG_SYS_POST_COPROC
Mike Frysinger813531f2011-05-10 13:35:40 +0000280 },
281#endif
282#if CONFIG_POST & CONFIG_SYS_POST_FLASH
283 {
284 "Parallel NOR flash test",
285 "flash",
286 "This test verifies parallel flash operations.",
287 POST_RAM | POST_SLOWTEST | POST_MANUAL,
288 &flash_post_test,
289 NULL,
290 NULL,
291 CONFIG_SYS_POST_FLASH
292 },
Anatolij Gustschin810b2072010-04-24 19:27:11 +0200293#endif
Valentin Longchamp24db42a2011-09-12 04:18:40 +0000294#if CONFIG_POST & CONFIG_SYS_POST_MEM_REGIONS
295 {
296 "Memory regions test",
297 "mem_regions",
298 "This test checks regularly placed regions of the RAM.",
299 POST_ROM | POST_SLOWTEST | POST_PREREL,
300 &memory_regions_post_test,
301 NULL,
302 NULL,
303 CONFIG_SYS_POST_MEM_REGIONS
304 },
305#endif
wdenk324f6cf2002-10-07 21:13:39 +0000306};
307
Mike Frysinger83a687b2011-05-10 07:28:35 +0000308unsigned int post_list_size = ARRAY_SIZE(post_list);