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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Heiko Schocher60301192010-02-22 16:43:02 +05302/*
3 * (C) Copyright 2009
4 * Marvell Semiconductor <www.marvell.com>
5 * Prafulla Wadaskar <prafulla@marvell.com>
6 *
7 * (C) Copyright 2009
8 * Stefan Roese, DENX Software Engineering, sr@denx.de.
9 *
Holger Brunck2ef42952012-07-05 05:37:46 +000010 * (C) Copyright 2011-2012
11 * Holger Brunck, Keymile GmbH Hannover, holger.brunck@keymile.com
12 * Valentin Longchamp, Keymile AG, valentin.longchamp@keymile.com
Heiko Schocher60301192010-02-22 16:43:02 +053013 */
14
15/*
16 * for linking errors see
17 * http://lists.denx.de/pipermail/u-boot/2009-July/057350.html
18 */
19
Holger Brunck1f974e92011-06-16 18:11:15 +053020#ifndef _CONFIG_KM_KIRKWOOD_H
21#define _CONFIG_KM_KIRKWOOD_H
Heiko Schocher60301192010-02-22 16:43:02 +053022
Holger Brunckb693ce82012-07-05 05:05:06 +000023/* KM_KIRKWOOD */
Holger Brunck9f03a382012-05-25 01:57:13 +000024#if defined(CONFIG_KM_KIRKWOOD)
Mario Six790d8442018-03-28 14:38:20 +020025#define CONFIG_HOSTNAME "km_kirkwood"
Holger Brunckb693ce82012-07-05 05:05:06 +000026#define CONFIG_KM_DISABLE_PCIE
Holger Brunckb693ce82012-07-05 05:05:06 +000027
28/* KM_KIRKWOOD_PCI */
Holger Brunck9f03a382012-05-25 01:57:13 +000029#elif defined(CONFIG_KM_KIRKWOOD_PCI)
Mario Six790d8442018-03-28 14:38:20 +020030#define CONFIG_HOSTNAME "km_kirkwood_pci"
Holger Brunck4dd3bcf2014-08-15 10:51:48 +020031#define CONFIG_KM_UBI_PART_BOOT_OPTS ",2048"
32#define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
Holger Brunckb693ce82012-07-05 05:05:06 +000033
Karlheinz Jerg34544ea2013-09-18 09:32:48 +020034/* KM_KIRKWOOD_128M16 */
35#elif defined(CONFIG_KM_KIRKWOOD_128M16)
Mario Six790d8442018-03-28 14:38:20 +020036#define CONFIG_HOSTNAME "km_kirkwood_128m16"
Karlheinz Jerg34544ea2013-09-18 09:32:48 +020037#define CONFIG_KM_DISABLE_PCIE
Karlheinz Jerg34544ea2013-09-18 09:32:48 +020038
Holger Brunck09f34042020-01-13 15:34:02 +010039/* KM_NUSA */
40#elif defined(CONFIG_KM_NUSA)
Gerlando Falauto29ff59a2014-02-13 16:43:00 +010041
Mario Six790d8442018-03-28 14:38:20 +020042#define CONFIG_HOSTNAME "kmnusa"
Gerlando Falauto29ff59a2014-02-13 16:43:00 +010043
Holger Brunckd896d0d2012-07-05 05:05:03 +000044/* KMCOGE5UN */
Holger Brunckf065ce02012-07-05 05:05:02 +000045#elif defined(CONFIG_KM_COGE5UN)
Mario Six790d8442018-03-28 14:38:20 +020046#define CONFIG_HOSTNAME "kmcoge5un"
Holger Brunckf065ce02012-07-05 05:05:02 +000047#define CONFIG_KM_DISABLE_PCIE
Holger Brunckc9caa7f2012-07-05 05:05:04 +000048
Holger Brunck55b3c6c2020-01-13 15:34:01 +010049/* KM_SUSE2 */
50#elif defined(CONFIG_KM_SUSE2)
51#define CONFIG_HOSTNAME "kmsuse2"
Holger Brunck55b3c6c2020-01-13 15:34:01 +010052#define CONFIG_KM_UBI_PART_BOOT_OPTS ",2048"
53#define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
Holger Brunck2ef42952012-07-05 05:37:46 +000054#else
55#error ("Board unsupported")
Holger Brunck1f974e92011-06-16 18:11:15 +053056#endif
Heiko Schocher60301192010-02-22 16:43:02 +053057
Holger Brunck2ef42952012-07-05 05:37:46 +000058/* include common defines/options for all arm based Keymile boards */
59#include "km/km_arm.h"
60
Holger Brunck2ef42952012-07-05 05:37:46 +000061#if defined(CONFIG_KM_PIGGY4_88E6352)
62/*
63 * Some keymile boards like mgcoge5un & nusa1 have their PIGGY4 connected via
64 * an Marvell 88E6352 simple switch.
65 * In this case we have to change the default settings for the etherent mac.
66 * There is NO ethernet phy. The ARM and Switch are conencted directly over
67 * RGMII in MAC-MAC mode
68 * In this case 1GBit full duplex and autoneg off
69 */
70#define PORT_SERIAL_CONTROL_VALUE ( \
71 MVGBE_FORCE_LINK_PASS | \
72 MVGBE_DIS_AUTO_NEG_FOR_DUPLX | \
73 MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL | \
74 MVGBE_ADV_NO_FLOW_CTRL | \
75 MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
76 MVGBE_FORCE_BP_MODE_NO_JAM | \
77 (1 << 9) /* Reserved bit has to be 1 */ | \
78 MVGBE_DO_NOT_FORCE_LINK_FAIL | \
79 MVGBE_DIS_AUTO_NEG_SPEED_GMII | \
80 MVGBE_DTE_ADV_0 | \
81 MVGBE_MIIPHY_MAC_MODE | \
82 MVGBE_AUTO_NEG_NO_CHANGE | \
83 MVGBE_MAX_RX_PACKET_1552BYTE | \
84 MVGBE_CLR_EXT_LOOPBACK | \
85 MVGBE_SET_FULL_DUPLEX_MODE | \
86 MVGBE_EN_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX |\
87 MVGBE_SET_GMII_SPEED_TO_1000 |\
88 MVGBE_SET_MII_SPEED_TO_100)
89
90#endif
Heiko Schochere4533af2011-03-08 10:53:51 +010091
Holger Brunckd896d0d2012-07-05 05:05:03 +000092#ifdef CONFIG_KM_PIGGY4_88E6061
93/*
Holger Bruncke306c672019-11-25 17:24:15 +010094 * Some keymile boards like mgcoge5un have their PIGGY4 connected via
Holger Brunckd896d0d2012-07-05 05:05:03 +000095 * an Marvell 88E6061 simple switch.
96 * In this case we have to change the default settings for the
97 * ethernet phy connected to the kirkwood.
98 * In this case 100MB full duplex and autoneg off
99 */
100#define PORT_SERIAL_CONTROL_VALUE ( \
101 MVGBE_FORCE_LINK_PASS | \
102 MVGBE_DIS_AUTO_NEG_FOR_DUPLX | \
103 MVGBE_DIS_AUTO_NEG_FOR_FLOW_CTRL | \
104 MVGBE_ADV_NO_FLOW_CTRL | \
105 MVGBE_FORCE_FC_MODE_NO_PAUSE_DIS_TX | \
106 MVGBE_FORCE_BP_MODE_NO_JAM | \
107 (1 << 9) /* Reserved bit has to be 1 */ | \
108 MVGBE_DO_NOT_FORCE_LINK_FAIL | \
109 MVGBE_DIS_AUTO_NEG_SPEED_GMII | \
110 MVGBE_DTE_ADV_0 | \
111 MVGBE_MIIPHY_MAC_MODE | \
112 MVGBE_AUTO_NEG_NO_CHANGE | \
113 MVGBE_MAX_RX_PACKET_1552BYTE | \
114 MVGBE_CLR_EXT_LOOPBACK | \
115 MVGBE_SET_FULL_DUPLEX_MODE | \
116 MVGBE_DIS_FLOW_CTRL_TX_RX_IN_FULL_DUPLEX |\
117 MVGBE_SET_GMII_SPEED_TO_10_100 |\
118 MVGBE_SET_MII_SPEED_TO_100)
119#endif
120
Pascal Linder9da11de2019-07-09 09:28:23 +0200121#ifdef CONFIG_KM_DISABLE_PCIE
Holger Brunckd896d0d2012-07-05 05:05:03 +0000122#undef CONFIG_KIRKWOOD_PCIE_INIT
123#endif
Valentin Longchamp6633fed2012-07-05 05:05:05 +0000124
Holger Brunck1f974e92011-06-16 18:11:15 +0530125#endif /* _CONFIG_KM_KIRKWOOD */