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git01.mediatek.com / filogic / uboot / 3dc5ea7e76174239b6d62aae637d2a7ab83c065d / . / arch / sandbox / dts / test.dts
blob: 1bc3ca0770c5ac1c6784c1621e4200f92b359e95 [file] [log] [blame]
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]1/dts-v1/;
2
3/ {
4 model = "sandbox";
5 compatible = "sandbox";
6 #address-cells = <1>;
7 #size-cells = <0>;
8
Simon Glassfef72b72014-07-23 06:55:03 -0600[diff] [blame]9 aliases {
10 console = &uart0;
Simon Glass0ccb0972015-01-25 08:27:05 -0700[diff] [blame]11 i2c0 = "/i2c@0";
Simon Glass6b0fb742015-04-20 12:37:30 -0600[diff] [blame]12 spi0 = "/spi@0";
Przemyslaw Marczak3dbb55e2015-05-13 13:38:34 +0200[diff] [blame]13 pci0 = &pci;
14 testfdt6 = "/e-test";
Simon Glass0ccb0972015-01-25 08:27:05 -0700[diff] [blame]15 testbus3 = "/some-bus";
16 testfdt0 = "/some-bus/c-test@0";
17 testfdt1 = "/some-bus/c-test@1";
18 testfdt3 = "/b-test";
19 testfdt5 = "/some-bus/c-test@5";
20 testfdt8 = "/a-test";
Przemyslaw Marczak3dbb55e2015-05-13 13:38:34 +0200[diff] [blame]21 eth0 = "/eth@10002000";
22 eth5 = &eth_5;
Simon Glass31680482015-03-25 12:23:05 -0600[diff] [blame]23 usb0 = &usb_0;
24 usb1 = &usb_1;
25 usb2 = &usb_2;
Simon Glassfef72b72014-07-23 06:55:03 -0600[diff] [blame]26 };
27
28 uart0: serial {
29 compatible = "sandbox,serial";
30 u-boot,dm-pre-reloc;
31 };
32
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]33 a-test {
34 reg = <0>;
35 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600[diff] [blame]36 ping-expect = <0>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]37 ping-add = <0>;
Simon Glassfef72b72014-07-23 06:55:03 -0600[diff] [blame]38 u-boot,dm-pre-reloc;
Simon Glass16e10402015-01-05 20:05:29 -0700[diff] [blame]39 test-gpios = <&gpio_a 1>, <&gpio_a 4>, <&gpio_b 5 0 3 2 1>,
40 <0>, <&gpio_a 12>;
41 test2-gpios = <&gpio_a 1>, <&gpio_a 4>, <&gpio_b 6 1 3 2 1>,
42 <&gpio_b 7 2 3 2 1>, <&gpio_b 8 4 3 2 1>,
43 <&gpio_b 9 0xc 3 2 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]44 };
45
46 junk {
47 reg = <1>;
48 compatible = "not,compatible";
49 };
50
51 no-compatible {
52 reg = <2>;
53 };
54
55 b-test {
56 reg = <3>;
57 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600[diff] [blame]58 ping-expect = <3>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]59 ping-add = <3>;
60 };
61
62 some-bus {
63 #address-cells = <1>;
64 #size-cells = <0>;
Simon Glass40717422014-07-23 06:55:18 -0600[diff] [blame]65 compatible = "denx,u-boot-test-bus";
Simon Glassdb6f0202014-07-23 06:55:12 -0600[diff] [blame]66 reg = <3>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600[diff] [blame]67 ping-expect = <4>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]68 ping-add = <4>;
Simon Glass40717422014-07-23 06:55:18 -0600[diff] [blame]69 c-test@5 {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]70 compatible = "denx,u-boot-fdt-test";
71 reg = <5>;
Simon Glass40717422014-07-23 06:55:18 -0600[diff] [blame]72 ping-expect = <5>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]73 ping-add = <5>;
74 };
Simon Glass40717422014-07-23 06:55:18 -0600[diff] [blame]75 c-test@0 {
76 compatible = "denx,u-boot-fdt-test";
77 reg = <0>;
78 ping-expect = <6>;
79 ping-add = <6>;
80 };
81 c-test@1 {
82 compatible = "denx,u-boot-fdt-test";
83 reg = <1>;
84 ping-expect = <7>;
85 ping-add = <7>;
86 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]87 };
88
89 d-test {
Simon Glassdb6f0202014-07-23 06:55:12 -0600[diff] [blame]90 reg = <3>;
91 ping-expect = <6>;
92 ping-add = <6>;
93 compatible = "google,another-fdt-test";
94 };
95
96 e-test {
97 reg = <3>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600[diff] [blame]98 ping-expect = <6>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]99 ping-add = <6>;
100 compatible = "google,another-fdt-test";
101 };
102
Simon Glass0ccb0972015-01-25 08:27:05 -0700[diff] [blame]103 f-test {
104 compatible = "denx,u-boot-fdt-test";
105 };
106
107 g-test {
108 compatible = "denx,u-boot-fdt-test";
109 };
110
Simon Glass25348a42014-10-13 23:42:11 -0600[diff] [blame]111 gpio_a: base-gpios {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]112 compatible = "sandbox,gpio";
Simon Glass16e10402015-01-05 20:05:29 -0700[diff] [blame]113 gpio-controller;
114 #gpio-cells = <1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]115 gpio-bank-name = "a";
116 num-gpios = <20>;
117 };
118
Simon Glass16e10402015-01-05 20:05:29 -0700[diff] [blame]119 gpio_b: extra-gpios {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]120 compatible = "sandbox,gpio";
Simon Glass16e10402015-01-05 20:05:29 -0700[diff] [blame]121 gpio-controller;
122 #gpio-cells = <5>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]123 gpio-bank-name = "b";
124 num-gpios = <10>;
125 };
Simon Glass25348a42014-10-13 23:42:11 -0600[diff] [blame]126
Simon Glass7df766e2014-12-10 08:55:55 -0700[diff] [blame]127 i2c@0 {
128 #address-cells = <1>;
129 #size-cells = <0>;
130 reg = <0>;
131 compatible = "sandbox,i2c";
132 clock-frequency = <100000>;
133 eeprom@2c {
134 reg = <0x2c>;
135 compatible = "i2c-eeprom";
136 emul {
137 compatible = "sandbox,i2c-eeprom";
138 sandbox,filename = "i2c.bin";
139 sandbox,size = <256>;
140 };
141 };
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200[diff] [blame]142
143 sandbox_pmic: sandbox_pmic {
144 reg = <0x40>;
145 };
Simon Glass7df766e2014-12-10 08:55:55 -0700[diff] [blame]146 };
147
Simon Glass3a6eae62015-03-05 12:25:34 -0700[diff] [blame]148 pci: pci-controller {
149 compatible = "sandbox,pci";
150 device_type = "pci";
151 #address-cells = <3>;
152 #size-cells = <2>;
153 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000
154 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
155 pci@1f,0 {
156 compatible = "pci-generic";
157 reg = <0xf800 0 0 0 0>;
158 emul@1f,0 {
159 compatible = "sandbox,swap-case";
160 };
161 };
162 };
163
Simon Glass25348a42014-10-13 23:42:11 -0600[diff] [blame]164 spi@0 {
165 #address-cells = <1>;
166 #size-cells = <0>;
167 reg = <0>;
168 compatible = "sandbox,spi";
169 cs-gpios = <0>, <&gpio_a 0>;
170 spi.bin@0 {
171 reg = <0>;
172 compatible = "spansion,m25p16", "spi-flash";
173 spi-max-frequency = <40000000>;
174 sandbox,filename = "spi.bin";
175 };
176 };
177
Joe Hershberger4c197242015-03-22 17:09:15 -0500[diff] [blame]178 eth@10002000 {
179 compatible = "sandbox,eth";
180 reg = <0x10002000 0x1000>;
181 fake-host-hwaddr = <0x00 0x00 0x66 0x44 0x22 0x00>;
182 };
183
Joe Hershberger279d2f62015-03-22 17:09:16 -0500[diff] [blame]184 eth_5: eth@10003000 {
Joe Hershberger4c197242015-03-22 17:09:15 -0500[diff] [blame]185 compatible = "sandbox,eth";
186 reg = <0x10003000 0x1000>;
187 fake-host-hwaddr = <0x00 0x00 0x66 0x44 0x22 0x11>;
188 };
189
190 eth@10004000 {
191 compatible = "sandbox,eth";
192 reg = <0x10004000 0x1000>;
193 fake-host-hwaddr = <0x00 0x00 0x66 0x44 0x22 0x22>;
194 };
195
Simon Glass31680482015-03-25 12:23:05 -0600[diff] [blame]196 usb_0: usb@0 {
197 compatible = "sandbox,usb";
198 status = "disabled";
199 hub {
200 compatible = "sandbox,usb-hub";
201 #address-cells = <1>;
202 #size-cells = <0>;
203 flash-stick {
204 reg = <0>;
205 compatible = "sandbox,usb-flash";
206 };
207 };
208 };
209
210 usb_1: usb@1 {
211 compatible = "sandbox,usb";
212 hub {
213 compatible = "usb-hub";
214 usb,device-class = <9>;
215 hub-emul {
216 compatible = "sandbox,usb-hub";
217 #address-cells = <1>;
218 #size-cells = <0>;
219 flash-stick {
220 reg = <0>;
221 compatible = "sandbox,usb-flash";
222 sandbox,filepath = "testflash.bin";
223 };
224
225 };
226 };
227 };
228
229 usb_2: usb@2 {
230 compatible = "sandbox,usb";
231 status = "disabled";
232 };
233
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]234};
Przemyslaw Marczak77bee052015-05-13 13:38:35 +0200[diff] [blame]235
236#include "sandbox_pmic.dtsi"