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git01.mediatek.com / filogic / uboot / 279d2f67e6282aee5bb977fafe63cee33fffee81 / . / test / dm / test.dts
blob: 0ab0916858aaeab5a8c9af7ce1dee6c3ba8d2b2d [file] [log] [blame]
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]1/dts-v1/;
2
3/ {
4 model = "sandbox";
5 compatible = "sandbox";
6 #address-cells = <1>;
7 #size-cells = <0>;
8
Simon Glassfef72b72014-07-23 06:55:03 -0600[diff] [blame]9 aliases {
10 console = &uart0;
Simon Glass0ccb0972015-01-25 08:27:05 -0700[diff] [blame]11 i2c0 = "/i2c@0";
12 spi0 = "/spi@0";
Simon Glass3a6eae62015-03-05 12:25:34 -0700[diff] [blame]13 pci0 = &pci;
Simon Glassdb6f0202014-07-23 06:55:12 -0600[diff] [blame]14 testfdt6 = "/e-test";
Simon Glass0ccb0972015-01-25 08:27:05 -0700[diff] [blame]15 testbus3 = "/some-bus";
16 testfdt0 = "/some-bus/c-test@0";
17 testfdt1 = "/some-bus/c-test@1";
18 testfdt3 = "/b-test";
19 testfdt5 = "/some-bus/c-test@5";
20 testfdt8 = "/a-test";
Joe Hershberger279d2f62015-03-22 17:09:16 -0500[diff] [blame^]21 eth0 = "/eth@10002000";
22 eth5 = &eth_5;
Simon Glassfef72b72014-07-23 06:55:03 -0600[diff] [blame]23 };
24
25 uart0: serial {
26 compatible = "sandbox,serial";
27 u-boot,dm-pre-reloc;
28 };
29
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]30 a-test {
31 reg = <0>;
32 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600[diff] [blame]33 ping-expect = <0>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]34 ping-add = <0>;
Simon Glassfef72b72014-07-23 06:55:03 -0600[diff] [blame]35 u-boot,dm-pre-reloc;
Simon Glass16e10402015-01-05 20:05:29 -0700[diff] [blame]36 test-gpios = <&gpio_a 1>, <&gpio_a 4>, <&gpio_b 5 0 3 2 1>,
37 <0>, <&gpio_a 12>;
38 test2-gpios = <&gpio_a 1>, <&gpio_a 4>, <&gpio_b 6 1 3 2 1>,
39 <&gpio_b 7 2 3 2 1>, <&gpio_b 8 4 3 2 1>,
40 <&gpio_b 9 0xc 3 2 1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]41 };
42
43 junk {
44 reg = <1>;
45 compatible = "not,compatible";
46 };
47
48 no-compatible {
49 reg = <2>;
50 };
51
52 b-test {
53 reg = <3>;
54 compatible = "denx,u-boot-fdt-test";
Simon Glassa7bb08a2014-07-23 06:54:57 -0600[diff] [blame]55 ping-expect = <3>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]56 ping-add = <3>;
57 };
58
59 some-bus {
60 #address-cells = <1>;
61 #size-cells = <0>;
Simon Glass40717422014-07-23 06:55:18 -0600[diff] [blame]62 compatible = "denx,u-boot-test-bus";
Simon Glassdb6f0202014-07-23 06:55:12 -0600[diff] [blame]63 reg = <3>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600[diff] [blame]64 ping-expect = <4>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]65 ping-add = <4>;
Simon Glass40717422014-07-23 06:55:18 -0600[diff] [blame]66 c-test@5 {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]67 compatible = "denx,u-boot-fdt-test";
68 reg = <5>;
Simon Glass40717422014-07-23 06:55:18 -0600[diff] [blame]69 ping-expect = <5>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]70 ping-add = <5>;
71 };
Simon Glass40717422014-07-23 06:55:18 -0600[diff] [blame]72 c-test@0 {
73 compatible = "denx,u-boot-fdt-test";
74 reg = <0>;
75 ping-expect = <6>;
76 ping-add = <6>;
77 };
78 c-test@1 {
79 compatible = "denx,u-boot-fdt-test";
80 reg = <1>;
81 ping-expect = <7>;
82 ping-add = <7>;
83 };
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]84 };
85
86 d-test {
Simon Glassdb6f0202014-07-23 06:55:12 -0600[diff] [blame]87 reg = <3>;
88 ping-expect = <6>;
89 ping-add = <6>;
90 compatible = "google,another-fdt-test";
91 };
92
93 e-test {
94 reg = <3>;
Simon Glassa7bb08a2014-07-23 06:54:57 -0600[diff] [blame]95 ping-expect = <6>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]96 ping-add = <6>;
97 compatible = "google,another-fdt-test";
98 };
99
Simon Glass0ccb0972015-01-25 08:27:05 -0700[diff] [blame]100 f-test {
101 compatible = "denx,u-boot-fdt-test";
102 };
103
104 g-test {
105 compatible = "denx,u-boot-fdt-test";
106 };
107
Simon Glass25348a42014-10-13 23:42:11 -0600[diff] [blame]108 gpio_a: base-gpios {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]109 compatible = "sandbox,gpio";
Simon Glass16e10402015-01-05 20:05:29 -0700[diff] [blame]110 gpio-controller;
111 #gpio-cells = <1>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]112 gpio-bank-name = "a";
113 num-gpios = <20>;
114 };
115
Simon Glass16e10402015-01-05 20:05:29 -0700[diff] [blame]116 gpio_b: extra-gpios {
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]117 compatible = "sandbox,gpio";
Simon Glass16e10402015-01-05 20:05:29 -0700[diff] [blame]118 gpio-controller;
119 #gpio-cells = <5>;
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]120 gpio-bank-name = "b";
121 num-gpios = <10>;
122 };
Simon Glass25348a42014-10-13 23:42:11 -0600[diff] [blame]123
Simon Glass7df766e2014-12-10 08:55:55 -0700[diff] [blame]124 i2c@0 {
125 #address-cells = <1>;
126 #size-cells = <0>;
127 reg = <0>;
128 compatible = "sandbox,i2c";
129 clock-frequency = <100000>;
130 eeprom@2c {
131 reg = <0x2c>;
132 compatible = "i2c-eeprom";
133 emul {
134 compatible = "sandbox,i2c-eeprom";
135 sandbox,filename = "i2c.bin";
136 sandbox,size = <256>;
137 };
138 };
139 };
140
Simon Glass3a6eae62015-03-05 12:25:34 -0700[diff] [blame]141 pci: pci-controller {
142 compatible = "sandbox,pci";
143 device_type = "pci";
144 #address-cells = <3>;
145 #size-cells = <2>;
146 ranges = <0x02000000 0 0x10000000 0x10000000 0 0x2000
147 0x01000000 0 0x20000000 0x20000000 0 0x2000>;
148 pci@1f,0 {
149 compatible = "pci-generic";
150 reg = <0xf800 0 0 0 0>;
151 emul@1f,0 {
152 compatible = "sandbox,swap-case";
153 };
154 };
155 };
156
Simon Glass25348a42014-10-13 23:42:11 -0600[diff] [blame]157 spi@0 {
158 #address-cells = <1>;
159 #size-cells = <0>;
160 reg = <0>;
161 compatible = "sandbox,spi";
162 cs-gpios = <0>, <&gpio_a 0>;
163 spi.bin@0 {
164 reg = <0>;
165 compatible = "spansion,m25p16", "spi-flash";
166 spi-max-frequency = <40000000>;
167 sandbox,filename = "spi.bin";
168 };
169 };
170
Joe Hershberger4c197242015-03-22 17:09:15 -0500[diff] [blame]171 eth@10002000 {
172 compatible = "sandbox,eth";
173 reg = <0x10002000 0x1000>;
174 fake-host-hwaddr = <0x00 0x00 0x66 0x44 0x22 0x00>;
175 };
176
Joe Hershberger279d2f62015-03-22 17:09:16 -0500[diff] [blame^]177 eth_5: eth@10003000 {
Joe Hershberger4c197242015-03-22 17:09:15 -0500[diff] [blame]178 compatible = "sandbox,eth";
179 reg = <0x10003000 0x1000>;
180 fake-host-hwaddr = <0x00 0x00 0x66 0x44 0x22 0x11>;
181 };
182
183 eth@10004000 {
184 compatible = "sandbox,eth";
185 reg = <0x10004000 0x1000>;
186 fake-host-hwaddr = <0x00 0x00 0x66 0x44 0x22 0x22>;
187 };
188
Simon Glassb2c1cac2014-02-26 15:59:21 -0700[diff] [blame]189};