blob: 94ecf9066028f1f4da7b0e0c9393bd65c44ee485 [file] [log] [blame]
Michal Simek04b7e622015-01-15 10:01:51 +01001/*
2 * (C) Copyright 2014 - 2015 Xilinx, Inc.
3 * Michal Simek <michal.simek@xilinx.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#include <common.h>
9#include <asm/arch/hardware.h>
10#include <asm/arch/sys_proto.h>
Alexander Graf0e2088c2016-03-04 01:09:49 +010011#include <asm/armv8/mmu.h>
Michal Simek04b7e622015-01-15 10:01:51 +010012#include <asm/io.h>
13
14#define ZYNQ_SILICON_VER_MASK 0xF000
15#define ZYNQ_SILICON_VER_SHIFT 12
16
17DECLARE_GLOBAL_DATA_PTR;
18
Alexander Graf0e2088c2016-03-04 01:09:49 +010019static struct mm_region zynqmp_mem_map[] = {
20 {
York Sunc7104e52016-06-24 16:46:22 -070021 .virt = 0x0UL,
22 .phys = 0x0UL,
Alexander Graf0e2088c2016-03-04 01:09:49 +010023 .size = 0x80000000UL,
24 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
25 PTE_BLOCK_INNER_SHARE
26 }, {
York Sunc7104e52016-06-24 16:46:22 -070027 .virt = 0x80000000UL,
28 .phys = 0x80000000UL,
Alexander Graf0e2088c2016-03-04 01:09:49 +010029 .size = 0x70000000UL,
30 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
31 PTE_BLOCK_NON_SHARE |
32 PTE_BLOCK_PXN | PTE_BLOCK_UXN
33 }, {
York Sunc7104e52016-06-24 16:46:22 -070034 .virt = 0xf8000000UL,
35 .phys = 0xf8000000UL,
Alexander Graf0e2088c2016-03-04 01:09:49 +010036 .size = 0x07e00000UL,
37 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
38 PTE_BLOCK_NON_SHARE |
39 PTE_BLOCK_PXN | PTE_BLOCK_UXN
40 }, {
York Sunc7104e52016-06-24 16:46:22 -070041 .virt = 0x400000000UL,
42 .phys = 0x400000000UL,
Alexander Graf0e2088c2016-03-04 01:09:49 +010043 .size = 0x200000000UL,
44 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
45 PTE_BLOCK_NON_SHARE |
46 PTE_BLOCK_PXN | PTE_BLOCK_UXN
47 }, {
York Sunc7104e52016-06-24 16:46:22 -070048 .virt = 0x600000000UL,
49 .phys = 0x600000000UL,
Alexander Graf0e2088c2016-03-04 01:09:49 +010050 .size = 0x800000000UL,
51 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
52 PTE_BLOCK_INNER_SHARE
53 }, {
York Sunc7104e52016-06-24 16:46:22 -070054 .virt = 0xe00000000UL,
55 .phys = 0xe00000000UL,
Alexander Graf0e2088c2016-03-04 01:09:49 +010056 .size = 0xf200000000UL,
57 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
58 PTE_BLOCK_NON_SHARE |
59 PTE_BLOCK_PXN | PTE_BLOCK_UXN
60 }, {
61 /* List terminator */
62 0,
63 }
64};
65struct mm_region *mem_map = zynqmp_mem_map;
66
Michal Simek1a2d5e22016-05-30 10:41:26 +020067u64 get_page_table_size(void)
68{
69 return 0x14000;
70}
71
Michal Simekc23d3f82015-11-05 08:34:35 +010072static unsigned int zynqmp_get_silicon_version_secure(void)
73{
74 u32 ver;
75
76 ver = readl(&csu_base->version);
77 ver &= ZYNQMP_SILICON_VER_MASK;
78 ver >>= ZYNQMP_SILICON_VER_SHIFT;
79
80 return ver;
81}
82
Michal Simek04b7e622015-01-15 10:01:51 +010083unsigned int zynqmp_get_silicon_version(void)
84{
Michal Simekc23d3f82015-11-05 08:34:35 +010085 if (current_el() == 3)
86 return zynqmp_get_silicon_version_secure();
87
Michal Simek04b7e622015-01-15 10:01:51 +010088 gd->cpu_clk = get_tbclk();
89
90 switch (gd->cpu_clk) {
Michal Simek0ca55572015-04-15 14:59:19 +020091 case 0 ... 1000000:
92 return ZYNQMP_CSU_VERSION_VELOCE;
Michal Simek04b7e622015-01-15 10:01:51 +010093 case 50000000:
94 return ZYNQMP_CSU_VERSION_QEMU;
Michal Simek8d2c02d2015-08-20 14:01:39 +020095 case 4000000:
96 return ZYNQMP_CSU_VERSION_EP108;
Michal Simek04b7e622015-01-15 10:01:51 +010097 }
98
Michal Simek8d2c02d2015-08-20 14:01:39 +020099 return ZYNQMP_CSU_VERSION_SILICON;
Michal Simek04b7e622015-01-15 10:01:51 +0100100}
Siva Durga Prasad Paladugu0e39bd72017-02-02 01:10:46 +0530101
102#define ZYNQMP_MMIO_READ 0xC2000014
103#define ZYNQMP_MMIO_WRITE 0xC2000013
104
105#ifndef CONFIG_SPL_BUILD
106int invoke_smc(u32 pm_api_id, u32 arg0, u32 arg1, u32 arg2, u32 arg3,
107 u32 *ret_payload)
108{
109 /*
110 * Added SIP service call Function Identifier
111 * Make sure to stay in x0 register
112 */
113 struct pt_regs regs;
114
115 regs.regs[0] = pm_api_id;
116 regs.regs[1] = ((u64)arg1 << 32) | arg0;
117 regs.regs[2] = ((u64)arg3 << 32) | arg2;
118
119 smc_call(&regs);
120
121 if (ret_payload != NULL) {
122 ret_payload[0] = (u32)regs.regs[0];
123 ret_payload[1] = upper_32_bits(regs.regs[0]);
124 ret_payload[2] = (u32)regs.regs[1];
125 ret_payload[3] = upper_32_bits(regs.regs[1]);
126 ret_payload[4] = (u32)regs.regs[2];
127 }
128
129 return regs.regs[0];
130}
131
Michal Simek8b353302017-02-07 14:32:26 +0100132#define ZYNQMP_SIP_SVC_GET_API_VERSION 0xC2000001
133
134#define ZYNQMP_PM_VERSION_MAJOR 0
135#define ZYNQMP_PM_VERSION_MINOR 3
136#define ZYNQMP_PM_VERSION_MAJOR_SHIFT 16
137#define ZYNQMP_PM_VERSION_MINOR_MASK 0xFFFF
138
139#define ZYNQMP_PM_VERSION \
140 ((ZYNQMP_PM_VERSION_MAJOR << ZYNQMP_PM_VERSION_MAJOR_SHIFT) | \
141 ZYNQMP_PM_VERSION_MINOR)
142
143#if defined(CONFIG_CLK_ZYNQMP)
144void zynqmp_pmufw_version(void)
145{
146 int ret;
147 u32 ret_payload[PAYLOAD_ARG_CNT];
148 u32 pm_api_version;
149
150 ret = invoke_smc(ZYNQMP_SIP_SVC_GET_API_VERSION, 0, 0, 0, 0,
151 ret_payload);
152 pm_api_version = ret_payload[1];
153
154 if (ret)
155 panic("PMUFW is not found - Please load it!\n");
156
157 printf("PMUFW:\tv%d.%d\n",
158 pm_api_version >> ZYNQMP_PM_VERSION_MAJOR_SHIFT,
159 pm_api_version & ZYNQMP_PM_VERSION_MINOR_MASK);
160
161 if (pm_api_version != ZYNQMP_PM_VERSION)
162 panic("PMUFW version error. Expected: v%d.%d\n",
163 ZYNQMP_PM_VERSION_MAJOR, ZYNQMP_PM_VERSION_MINOR);
164}
165#endif
166
Siva Durga Prasad Paladugu0e39bd72017-02-02 01:10:46 +0530167int zynqmp_mmio_write(const u32 address,
168 const u32 mask,
169 const u32 value)
170{
171 return invoke_smc(ZYNQMP_MMIO_WRITE, address, mask, value, 0, NULL);
172}
173
174int zynqmp_mmio_read(const u32 address, u32 *value)
175{
176 u32 ret_payload[PAYLOAD_ARG_CNT];
177 u32 ret;
178
179 if (!value)
180 return -EINVAL;
181
182 ret = invoke_smc(ZYNQMP_MMIO_READ, address, 0, 0, 0, ret_payload);
183 *value = ret_payload[1];
184
185 return ret;
186}
187#else
188int zynqmp_mmio_write(const u32 address,
189 const u32 mask,
190 const u32 value)
191{
192 u32 data;
193 u32 value_local = value;
194
195 zynqmp_mmio_read(address, &data);
196 data &= ~mask;
197 value_local &= mask;
198 value_local |= data;
199 writel(value_local, (ulong)address);
200 return 0;
201}
202
203int zynqmp_mmio_read(const u32 address, u32 *value)
204{
205 *value = readl((ulong)address);
206 return 0;
207}
208#endif