Jagan Teki | d69bf0b | 2018-08-05 14:31:54 +0530 | [diff] [blame] | 1 | // SPDX-License-Identifier: (GPL-2.0+ OR MIT) |
| 2 | /* |
| 3 | * Copyright (C) 2018 Amarula Solutions. |
| 4 | * Author: Jagan Teki <jagan@amarulasolutions.com> |
| 5 | */ |
| 6 | |
| 7 | #include <common.h> |
| 8 | #include <clk-uclass.h> |
| 9 | #include <dm.h> |
| 10 | #include <errno.h> |
Samuel Holland | 12e3faa | 2021-09-12 11:48:43 -0500 | [diff] [blame] | 11 | #include <clk/sunxi.h> |
Jagan Teki | d69bf0b | 2018-08-05 14:31:54 +0530 | [diff] [blame] | 12 | #include <dt-bindings/clock/sun8i-v3s-ccu.h> |
| 13 | #include <dt-bindings/reset/sun8i-v3s-ccu.h> |
Simon Glass | 4dcacfc | 2020-05-10 11:40:13 -0600 | [diff] [blame] | 14 | #include <linux/bitops.h> |
Jagan Teki | d69bf0b | 2018-08-05 14:31:54 +0530 | [diff] [blame] | 15 | |
| 16 | static struct ccu_clk_gate v3s_gates[] = { |
Andre Przywara | ddf33c1 | 2019-01-29 15:54:09 +0000 | [diff] [blame] | 17 | [CLK_BUS_MMC0] = GATE(0x060, BIT(8)), |
| 18 | [CLK_BUS_MMC1] = GATE(0x060, BIT(9)), |
| 19 | [CLK_BUS_MMC2] = GATE(0x060, BIT(10)), |
Jagan Teki | bc12313 | 2019-02-27 20:02:06 +0530 | [diff] [blame] | 20 | [CLK_BUS_SPI0] = GATE(0x060, BIT(20)), |
Jagan Teki | d69bf0b | 2018-08-05 14:31:54 +0530 | [diff] [blame] | 21 | [CLK_BUS_OTG] = GATE(0x060, BIT(24)), |
| 22 | |
Andre Przywara | 3e9aa0b | 2022-05-04 22:10:28 +0100 | [diff] [blame] | 23 | [CLK_BUS_PIO] = GATE(0x068, BIT(5)), |
| 24 | |
Samuel Holland | fa7a7fa | 2021-09-12 09:47:24 -0500 | [diff] [blame] | 25 | [CLK_BUS_I2C0] = GATE(0x06c, BIT(0)), |
| 26 | [CLK_BUS_I2C1] = GATE(0x06c, BIT(1)), |
Jagan Teki | 8cf08ea | 2018-12-30 21:29:24 +0530 | [diff] [blame] | 27 | [CLK_BUS_UART0] = GATE(0x06c, BIT(16)), |
| 28 | [CLK_BUS_UART1] = GATE(0x06c, BIT(17)), |
| 29 | [CLK_BUS_UART2] = GATE(0x06c, BIT(18)), |
| 30 | |
Jagan Teki | bc12313 | 2019-02-27 20:02:06 +0530 | [diff] [blame] | 31 | [CLK_SPI0] = GATE(0x0a0, BIT(31)), |
| 32 | |
Jagan Teki | d69bf0b | 2018-08-05 14:31:54 +0530 | [diff] [blame] | 33 | [CLK_USB_PHY0] = GATE(0x0cc, BIT(8)), |
| 34 | }; |
| 35 | |
| 36 | static struct ccu_reset v3s_resets[] = { |
| 37 | [RST_USB_PHY0] = RESET(0x0cc, BIT(0)), |
| 38 | |
Andre Przywara | ddf33c1 | 2019-01-29 15:54:09 +0000 | [diff] [blame] | 39 | [RST_BUS_MMC0] = RESET(0x2c0, BIT(8)), |
| 40 | [RST_BUS_MMC1] = RESET(0x2c0, BIT(9)), |
| 41 | [RST_BUS_MMC2] = RESET(0x2c0, BIT(10)), |
Jagan Teki | bc12313 | 2019-02-27 20:02:06 +0530 | [diff] [blame] | 42 | [RST_BUS_SPI0] = RESET(0x2c0, BIT(20)), |
Jagan Teki | d69bf0b | 2018-08-05 14:31:54 +0530 | [diff] [blame] | 43 | [RST_BUS_OTG] = RESET(0x2c0, BIT(24)), |
Jagan Teki | b490aa5 | 2018-12-30 21:37:31 +0530 | [diff] [blame] | 44 | |
Samuel Holland | fa7a7fa | 2021-09-12 09:47:24 -0500 | [diff] [blame] | 45 | [RST_BUS_I2C0] = RESET(0x2d8, BIT(0)), |
| 46 | [RST_BUS_I2C1] = RESET(0x2d8, BIT(1)), |
Jagan Teki | b490aa5 | 2018-12-30 21:37:31 +0530 | [diff] [blame] | 47 | [RST_BUS_UART0] = RESET(0x2d8, BIT(16)), |
| 48 | [RST_BUS_UART1] = RESET(0x2d8, BIT(17)), |
| 49 | [RST_BUS_UART2] = RESET(0x2d8, BIT(18)), |
Jagan Teki | d69bf0b | 2018-08-05 14:31:54 +0530 | [diff] [blame] | 50 | }; |
| 51 | |
Samuel Holland | 751c6c6 | 2022-05-09 00:29:34 -0500 | [diff] [blame] | 52 | const struct ccu_desc v3s_ccu_desc = { |
Jagan Teki | d69bf0b | 2018-08-05 14:31:54 +0530 | [diff] [blame] | 53 | .gates = v3s_gates, |
| 54 | .resets = v3s_resets, |
Samuel Holland | 8443650 | 2022-05-09 00:29:31 -0500 | [diff] [blame] | 55 | .num_gates = ARRAY_SIZE(v3s_gates), |
| 56 | .num_resets = ARRAY_SIZE(v3s_resets), |
Jagan Teki | d69bf0b | 2018-08-05 14:31:54 +0530 | [diff] [blame] | 57 | }; |