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git01.mediatek.com / filogic / uboot / 3d8b95051ac4e68fd1cdcd9895f505c0625ac3c9 / drivers / clk / sunxi / clk_v3s.c
  1. 751c6c6 clk: sunxi: Use a single driver for all variants by Samuel Holland · Mon May 09 00:29:34 2022 -0500
  2. 1567fdf reset: sunxi: Get the reset count from the CCU descriptor by Samuel Holland · Mon May 09 00:29:33 2022 -0500
  3. 8443650 clk: sunxi: Store the array sizes in the CCU descriptor by Samuel Holland · Mon May 09 00:29:31 2022 -0500
  4. 3e9aa0b clk: sunxi: add PIO bus gate clocks by Andre Przywara · Wed May 04 22:10:28 2022 +0100
  5. fa7a7fa clk: sunxi: Add support for I2C gates/resets by Samuel Holland · Sun Sep 12 09:47:24 2021 -0500
  6. 12e3faa clk: sunxi: Move header out of arch directory by Samuel Holland · Sun Sep 12 11:48:43 2021 -0500
  7. 8a2b47f dm: treewide: Rename auto_alloc_size members to be shorter by Simon Glass · Thu Dec 03 16:55:17 2020 -0700
  8. 18e4ab6 clk: sunxi: add compatible string for V3 by Icenowy Zheng · Mon Oct 26 22:18:02 2020 +0800
  9. 4dcacfc common: Drop linux/bitops.h from common header by Simon Glass · Sun May 10 11:40:13 2020 -0600
  10. bc12313 clk: sunxi: Implement SPI clocks, resets by Jagan Teki · Wed Feb 27 20:02:06 2019 +0530
  11. ddf33c1 sunxi: clk: add MMC gates/resets by Andre Przywara · Tue Jan 29 15:54:09 2019 +0000
  12. b490aa5 clk: sunxi: Implement UART resets by Jagan Teki · Sun Dec 30 21:37:31 2018 +0530
  13. 8cf08ea clk: sunxi: Implement UART clocks by Jagan Teki · Sun Dec 30 21:29:24 2018 +0530
  14. d69bf0b clk: sunxi: Add Allwinner V3S CLK driver by Jagan Teki · Sun Aug 05 14:31:54 2018 +0530