Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 3d4a2b98fbff726c8bb889ba88f4add35811f9af / . / board / phytec / pcl063 / spl.c
blob: b93cd493f21dc27d04b153399f36b650e1aadbe6 [file] [log] [blame]
Martyn Welch0a14bac2018-12-11 11:34:46 +0000[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2018 Collabora Ltd.
4 *
5 * Based on board/ccv/xpress/spl.c:
6 * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
7 */
8
9#include <common.h>
10#include <spl.h>
11#include <asm/arch/clock.h>
12#include <asm/io.h>
13#include <asm/arch/mx6-ddr.h>
14#include <asm/arch/mx6-pins.h>
15#include <asm/arch/crm_regs.h>
16#include <fsl_esdhc.h>
17
18/* Configuration for Micron MT41K256M16TW-107 IT:P, 32M x 16 x 8 -> 256MiB */
19
20static struct mx6ul_iomux_grp_regs mx6_grp_ioregs = {
21 .grp_addds = 0x00000030,
22 .grp_ddrmode_ctl = 0x00020000,
23 .grp_b0ds = 0x00000030,
24 .grp_ctlds = 0x00000030,
25 .grp_b1ds = 0x00000030,
26 .grp_ddrpke = 0x00000000,
27 .grp_ddrmode = 0x00020000,
28 .grp_ddr_type = 0x000c0000,
29};
30
31static struct mx6ul_iomux_ddr_regs mx6_ddr_ioregs = {
32 .dram_dqm0 = 0x00000030,
33 .dram_dqm1 = 0x00000030,
34 .dram_ras = 0x00000030,
35 .dram_cas = 0x00000030,
36 .dram_odt0 = 0x00000030,
37 .dram_odt1 = 0x00000030,
38 .dram_sdba2 = 0x00000000,
39 .dram_sdclk_0 = 0x00000030,
40 .dram_sdqs0 = 0x00000030,
41 .dram_sdqs1 = 0x00000030,
42 .dram_reset = 0x00000030,
43};
44
45static struct mx6_mmdc_calibration mx6_mmcd_calib = {
46 .p0_mpwldectrl0 = 0x00000000,
47 .p0_mpdgctrl0 = 0x41480148,
48 .p0_mprddlctl = 0x40403E42,
49 .p0_mpwrdlctl = 0x40405852,
50};
51
52struct mx6_ddr_sysinfo ddr_sysinfo = {
53 .dsize = 0, /* Bus size = 16bit */
54 .cs_density = 18,
55 .ncs = 1,
56 .cs1_mirror = 0,
57 .rtt_wr = 1,
58 .rtt_nom = 1,
59 .walat = 1, /* Write additional latency */
60 .ralat = 5, /* Read additional latency */
61 .mif3_mode = 3, /* Command prediction working mode */
62 .bi_on = 1, /* Bank interleaving enabled */
63 .pd_fast_exit = 1,
64 .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */
65 .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
66 .ddr_type = DDR_TYPE_DDR3,
67 .refsel = 1, /* Refresh cycles at 32KHz */
68 .refr = 7, /* 8 refresh commands per refresh cycle */
69};
70
71static struct mx6_ddr3_cfg mem_ddr = {
72 .mem_speed = 933,
73 .density = 4,
74 .width = 16,
75 .banks = 8,
76 .rowaddr = 14,
77 .coladdr = 10,
78 .pagesz = 1,
79 .trcd = 1391,
80 .trcmin = 4791,
81 .trasmin = 3400,
82};
83
84static void ccgr_init(void)
85{
86 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
87
88 writel(0xFFFFFFFF, &ccm->CCGR0);
89 writel(0xFFFFFFFF, &ccm->CCGR1);
90 writel(0xFFFFFFFF, &ccm->CCGR2);
91 writel(0xFFFFFFFF, &ccm->CCGR3);
92 writel(0xFFFFFFFF, &ccm->CCGR4);
93 writel(0xFFFFFFFF, &ccm->CCGR5);
94 writel(0xFFFFFFFF, &ccm->CCGR6);
95}
96
97static void spl_dram_init(void)
98{
99 mx6ul_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs);
100 mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr);
101}
102
103#ifdef CONFIG_FSL_ESDHC
104
105#define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
106 PAD_CTL_PUS_22K_UP | PAD_CTL_SPEED_LOW | \
107 PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | \
108 PAD_CTL_HYS)
109
110static iomux_v3_cfg_t const usdhc1_pads[] = {
111 MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
112 MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
113 MX6_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
114 MX6_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
115 MX6_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
116 MX6_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
117 MX6_PAD_UART1_RTS_B__USDHC1_CD_B | MUX_PAD_CTRL(USDHC_PAD_CTRL),
118};
119
120static struct fsl_esdhc_cfg usdhc_cfg[] = {
121 {
122 .esdhc_base = USDHC1_BASE_ADDR,
123 .max_bus_width = 4,
124 },
125};
126
127int board_mmc_getcd(struct mmc *mmc)
128{
129 return 1;
130}
131
132int board_mmc_init(bd_t *bis)
133{
134 imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
135 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
136
137 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
138}
139
140#endif /* CONFIG_FSL_ESDHC */
141
142void board_init_f(ulong dummy)
143{
144 ccgr_init();
145
146 /* Setup AIPS and disable watchdog */
147 arch_cpu_init();
148
149 /* Setup iomux and fec */
150 board_early_init_f();
151
152 /* Setup GP timer */
153 timer_init();
154
155 /* UART clocks enabled and gd valid - init serial console */
156 preloader_console_init();
157
158 /* DDR initialization */
159 spl_dram_init();
160}