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Jon Loeliger3e2d0912007-04-11 16:50:57 -05001/*
Kumar Galaa9db4ec2011-01-11 00:52:35 -06002 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc.
Jon Loeliger3e2d0912007-04-11 16:50:57 -05003 *
Wolfgang Denkd79de1d2013-07-08 09:37:19 +02004 * SPDX-License-Identifier: GPL-2.0+
Jon Loeliger3e2d0912007-04-11 16:50:57 -05005 */
6
7/*
8 * mpc8544ds board configuration file
9 *
10 */
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
York Sun80bd6612015-08-18 12:35:52 -070014#define CONFIG_DISPLAY_BOARDINFO
15
Jon Loeliger3e2d0912007-04-11 16:50:57 -050016/* High Level Configuration Options */
17#define CONFIG_BOOKE 1 /* BOOKE */
18#define CONFIG_E500 1 /* BOOKE e500 family */
Jon Loeliger3e2d0912007-04-11 16:50:57 -050019#define CONFIG_MPC8544 1
20#define CONFIG_MPC8544DS 1
21
Wolfgang Denk291ba1b2010-10-06 09:05:45 +020022#ifndef CONFIG_SYS_TEXT_BASE
23#define CONFIG_SYS_TEXT_BASE 0xfff80000
24#endif
25
Ed Swarthout52b98522007-07-27 01:50:51 -050026#define CONFIG_PCI 1 /* Enable PCI/PCIE */
27#define CONFIG_PCI1 1 /* PCI controller 1 */
28#define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */
29#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */
30#define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */
31#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
Gabor Juhosb4458732013-05-30 07:06:12 +000032#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
Kumar Gala93166d22007-12-07 12:17:34 -060033#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
Kumar Gala7738d5c2008-10-21 11:33:58 -050034#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
Jon Loeliger3e2d0912007-04-11 16:50:57 -050035
Kumar Gala85af2b52008-01-16 01:16:16 -060036#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
37
Ed Swarthout52b98522007-07-27 01:50:51 -050038#define CONFIG_TSEC_ENET /* tsec ethernet support */
Jon Loeliger3e2d0912007-04-11 16:50:57 -050039#define CONFIG_ENV_OVERWRITE
Ed Swarthout52b98522007-07-27 01:50:51 -050040#define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
Jon Loeliger3e2d0912007-04-11 16:50:57 -050041
Jon Loeliger3e2d0912007-04-11 16:50:57 -050042#ifndef __ASSEMBLY__
43extern unsigned long get_board_sys_clk(unsigned long dummy);
44#endif
45#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */
46
47/*
48 * These can be toggled for performance analysis, otherwise use default.
49 */
Ed Swarthout52b98522007-07-27 01:50:51 -050050#define CONFIG_L2_CACHE /* toggle L2 cache */
Jon Loeliger3e2d0912007-04-11 16:50:57 -050051#define CONFIG_BTB /* toggle branch predition */
Jon Loeliger3e2d0912007-04-11 16:50:57 -050052
53/*
54 * Only possible on E500 Version 2 or newer cores.
55 */
56#define CONFIG_ENABLE_36BIT_PHYS 1
57
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020058#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
59#define CONFIG_SYS_MEMTEST_END 0x00400000
Ed Swarthout52b98522007-07-27 01:50:51 -050060#define CONFIG_PANIC_HANG /* do not reset board on panic */
Jon Loeliger3e2d0912007-04-11 16:50:57 -050061
Timur Tabid8f341c2011-08-04 18:03:41 -050062#define CONFIG_SYS_CCSRBAR 0xe0000000
63#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
Jon Loeliger3e2d0912007-04-11 16:50:57 -050064
Kumar Gala573ad302008-08-26 08:02:30 -050065/* DDR Setup */
York Sunf0626592013-09-30 09:22:09 -070066#define CONFIG_SYS_FSL_DDR2
Kumar Gala573ad302008-08-26 08:02:30 -050067#undef CONFIG_FSL_DDR_INTERACTIVE
68#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
69#define CONFIG_DDR_SPD
70
Dave Liud3ca1242008-10-28 17:53:38 +080071#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
Kumar Gala573ad302008-08-26 08:02:30 -050072#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
73
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +020074#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
75#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
Kumar Gala573ad302008-08-26 08:02:30 -050076#define CONFIG_VERY_BIG_RAM
77
78#define CONFIG_NUM_DDR_CONTROLLERS 1
79#define CONFIG_DIMM_SLOTS_PER_CTLR 1
80#define CONFIG_CHIP_SELECTS_PER_CTRL 2
Jon Loeliger3e2d0912007-04-11 16:50:57 -050081
Kumar Gala573ad302008-08-26 08:02:30 -050082/* I2C addresses of SPD EEPROMs */
Jon Loeliger3e2d0912007-04-11 16:50:57 -050083#define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */
84
Kumar Gala573ad302008-08-26 08:02:30 -050085/* Make sure required options are set */
Jon Loeliger3e2d0912007-04-11 16:50:57 -050086#ifndef CONFIG_SPD_EEPROM
87#error ("CONFIG_SPD_EEPROM is required")
88#endif
89
90#undef CONFIG_CLOCKS_IN_MHZ
91
92/*
93 * Memory map
94 *
95 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
96 *
97 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
98 *
99 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
100 *
101 * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable
102 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
103 *
104 * Localbus cacheable
105 *
106 * 0xf000_0000 0xf3ff_ffff SDRAM 64M Cacheable
107 * 0xf401_0000 0xf401_3fff L1 for stack 4K Cacheable TLB0
108 *
109 * Localbus non-cacheable
110 *
111 * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M non-cacheable
112 * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable
113 * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable
114 *
115 */
116
117/*
118 * Local Bus Definitions
119 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200120#define CONFIG_SYS_BOOT_BLOCK 0xfc000000 /* boot TLB */
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500121
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200122#define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH 8M */
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500123
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200124#define CONFIG_SYS_BR0_PRELIM 0xff801001
125#define CONFIG_SYS_BR1_PRELIM 0xfe801001
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500126
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200127#define CONFIG_SYS_OR0_PRELIM 0xff806e65
128#define CONFIG_SYS_OR1_PRELIM 0xff806e65
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500129
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200130#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500131
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200132#define CONFIG_SYS_FLASH_QUIET_TEST
133#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
134#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
135#undef CONFIG_SYS_FLASH_CHECKSUM
136#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
137#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Kumar Galaded59a12008-06-09 18:55:38 -0500138#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500139
Wolfgang Denk0708bc62010-10-07 21:51:12 +0200140#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500141
Jean-Christophe PLAGNIOL-VILLARD8d94c232008-08-13 01:40:42 +0200142#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200143#define CONFIG_SYS_FLASH_CFI
144#define CONFIG_SYS_FLASH_EMPTY_INFO
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500145
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200146#define CONFIG_SYS_LBC_NONCACHE_BASE 0xf8000000
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500147
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200148#define CONFIG_SYS_BR2_PRELIM 0xf8201001 /* port size 16bit */
149#define CONFIG_SYS_OR2_PRELIM 0xfff06ff7 /* 1MB Compact Flash area*/
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500150
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200151#define CONFIG_SYS_BR3_PRELIM 0xf8100801 /* port size 8bit */
152#define CONFIG_SYS_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500153
Kim Phillips53b34982007-08-21 17:00:17 -0500154#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500155#define PIXIS_BASE 0xf8100000 /* PIXIS registers */
156#define PIXIS_ID 0x0 /* Board ID at offset 0 */
157#define PIXIS_VER 0x1 /* Board version at offset 1 */
158#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
159#define PIXIS_RST 0x4 /* PIXIS Reset Control register */
160#define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch
161 * register */
162#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
163#define PIXIS_VCTL 0x10 /* VELA Control Register */
164#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
165#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
166#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
Kumar Galae21db032009-07-14 22:42:01 -0500167#define PIXIS_VBOOT_FMAP 0x80 /* VBOOT - CFG_FLASHMAP */
168#define PIXIS_VBOOT_FBANK 0x40 /* VBOOT - CFG_FLASHBANK */
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500169#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
170#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
171#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
172#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
Andy Flemingdb2b5bd2008-08-31 16:33:30 -0500173#define PIXIS_VSPEED2 0x1d /* VELA VSpeed 2 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200174#define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/
Andy Flemingdb2b5bd2008-08-31 16:33:30 -0500175#define PIXIS_VSPEED2_TSEC1SER 0x2
176#define PIXIS_VSPEED2_TSEC3SER 0x1
177#define PIXIS_VCFGEN1_TSEC1SER 0x20
178#define PIXIS_VCFGEN1_TSEC3SER 0x40
Liu Yu46269062008-10-10 11:40:58 +0800179#define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER|PIXIS_VSPEED2_TSEC3SER)
180#define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER|PIXIS_VCFGEN1_TSEC3SER)
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500181
182
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200183#define CONFIG_SYS_INIT_RAM_LOCK 1
184#define CONFIG_SYS_INIT_RAM_ADDR 0xf4010000 /* Initial L1 address */
Wolfgang Denk1c2e98e2010-10-26 13:32:32 +0200185#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500186
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500187
Wolfgang Denk0191e472010-10-26 14:34:52 +0200188#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200189#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500190
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200191#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
192#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500193
194/* Serial Port - controlled on board with jumper J8
195 * open - index 2
196 * shorted - index 1
197 */
198#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200199#define CONFIG_SYS_NS16550_SERIAL
200#define CONFIG_SYS_NS16550_REG_SIZE 1
201#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500202
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200203#define CONFIG_SYS_BAUDRATE_TABLE \
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500204 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
205
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200206#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
207#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500208
209/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200210#define CONFIG_SYS_HUSH_PARSER
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500211
212/* pass open firmware flat tree */
Kumar Gala67b349b2007-11-26 17:12:24 -0600213#define CONFIG_OF_LIBFDT 1
214#define CONFIG_OF_BOARD_SETUP 1
215#define CONFIG_OF_STDOUT_VIA_ALIAS 1
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500216
217/* I2C */
Heiko Schocherf2850742012-10-24 13:48:22 +0200218#define CONFIG_SYS_I2C
219#define CONFIG_SYS_I2C_FSL
220#define CONFIG_SYS_FSL_I2C_SPEED 400000
221#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
222#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
223#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200224#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500225
226/*
227 * General PCI
228 * Memory space is mapped 1-1, but I/O space must start from 0.
229 */
Kumar Galaef43b6e2008-12-02 16:08:39 -0600230#define CONFIG_SYS_PCIE_VIRT 0x80000000 /* 1G PCIE TLB */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200231#define CONFIG_SYS_PCIE_PHYS 0x80000000 /* 1G PCIE TLB */
Kumar Galaef43b6e2008-12-02 16:08:39 -0600232#define CONFIG_SYS_PCI_VIRT 0xc0000000 /* 512M PCI TLB */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200233#define CONFIG_SYS_PCI_PHYS 0xc0000000 /* 512M PCI TLB */
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500234
Kumar Galaef43b6e2008-12-02 16:08:39 -0600235#define CONFIG_SYS_PCI1_MEM_VIRT 0xc0000000
Kumar Gala3fe80872008-12-02 16:08:36 -0600236#define CONFIG_SYS_PCI1_MEM_BUS 0xc0000000
Kumar Galaef43b6e2008-12-02 16:08:39 -0600237#define CONFIG_SYS_PCI1_MEM_PHYS 0xc0000000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200238#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
Kumar Gala60ff4642008-12-02 16:08:40 -0600239#define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000
Kumar Gala64bb6d12008-12-02 16:08:37 -0600240#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200241#define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000
242#define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500243
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500244/* controller 2, Slot 1, tgtid 1, Base address 9000 */
Kumar Galacc46bc72010-12-17 06:01:24 -0600245#define CONFIG_SYS_PCIE2_NAME "Slot 1"
Kumar Galaef43b6e2008-12-02 16:08:39 -0600246#define CONFIG_SYS_PCIE2_MEM_VIRT 0x80000000
Kumar Gala3fe80872008-12-02 16:08:36 -0600247#define CONFIG_SYS_PCIE2_MEM_BUS 0x80000000
Kumar Galaef43b6e2008-12-02 16:08:39 -0600248#define CONFIG_SYS_PCIE2_MEM_PHYS 0x80000000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200249#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
Kumar Gala60ff4642008-12-02 16:08:40 -0600250#define CONFIG_SYS_PCIE2_IO_VIRT 0xe1010000
Kumar Gala64bb6d12008-12-02 16:08:37 -0600251#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200252#define CONFIG_SYS_PCIE2_IO_PHYS 0xe1010000
253#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500254
255/* controller 1, Slot 2,tgtid 2, Base address a000 */
Kumar Galacc46bc72010-12-17 06:01:24 -0600256#define CONFIG_SYS_PCIE1_NAME "Slot 2"
Kumar Galaef43b6e2008-12-02 16:08:39 -0600257#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
Kumar Gala3fe80872008-12-02 16:08:36 -0600258#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
Kumar Galaef43b6e2008-12-02 16:08:39 -0600259#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200260#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
Kumar Gala60ff4642008-12-02 16:08:40 -0600261#define CONFIG_SYS_PCIE1_IO_VIRT 0xe1020000
Kumar Gala64bb6d12008-12-02 16:08:37 -0600262#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200263#define CONFIG_SYS_PCIE1_IO_PHYS 0xe1020000
264#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500265
266/* controller 3, direct to uli, tgtid 3, Base address b000 */
Kumar Galacc46bc72010-12-17 06:01:24 -0600267#define CONFIG_SYS_PCIE3_NAME "ULI"
Kumar Galaef43b6e2008-12-02 16:08:39 -0600268#define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
Kumar Gala3fe80872008-12-02 16:08:36 -0600269#define CONFIG_SYS_PCIE3_MEM_BUS 0xb0000000
Kumar Galaef43b6e2008-12-02 16:08:39 -0600270#define CONFIG_SYS_PCIE3_MEM_PHYS 0xb0000000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200271#define CONFIG_SYS_PCIE3_MEM_SIZE 0x00100000 /* 1M */
Kumar Gala60ff4642008-12-02 16:08:40 -0600272#define CONFIG_SYS_PCIE3_IO_VIRT 0xb0100000 /* reuse mem LAW */
Kumar Gala64bb6d12008-12-02 16:08:37 -0600273#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200274#define CONFIG_SYS_PCIE3_IO_PHYS 0xb0100000 /* reuse mem LAW */
275#define CONFIG_SYS_PCIE3_IO_SIZE 0x00100000 /* 1M */
Kumar Galaef43b6e2008-12-02 16:08:39 -0600276#define CONFIG_SYS_PCIE3_MEM_VIRT2 0xb0200000
Kumar Gala3fe80872008-12-02 16:08:36 -0600277#define CONFIG_SYS_PCIE3_MEM_BUS2 0xb0200000
Kumar Galaef43b6e2008-12-02 16:08:39 -0600278#define CONFIG_SYS_PCIE3_MEM_PHYS2 0xb0200000
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200279#define CONFIG_SYS_PCIE3_MEM_SIZE2 0x00200000 /* 1M */
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500280
281#if defined(CONFIG_PCI)
282
Kumar Gala559e5312008-07-14 14:07:03 -0500283/*PCIE video card used*/
Kumar Gala60ff4642008-12-02 16:08:40 -0600284#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT
Kumar Gala559e5312008-07-14 14:07:03 -0500285
286/*PCI video card used*/
Kumar Gala60ff4642008-12-02 16:08:40 -0600287/*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/
Kumar Gala559e5312008-07-14 14:07:03 -0500288
289/* video */
290#define CONFIG_VIDEO
291
292#if defined(CONFIG_VIDEO)
293#define CONFIG_BIOSEMU
294#define CONFIG_CFB_CONSOLE
295#define CONFIG_VIDEO_SW_CURSOR
296#define CONFIG_VGA_AS_SINGLE_DEVICE
297#define CONFIG_ATI_RADEON_FB
298#define CONFIG_VIDEO_LOGO
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200299#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
Kumar Gala559e5312008-07-14 14:07:03 -0500300#endif
301
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500302#define CONFIG_PCI_PNP /* do pci plug-and-play */
303
304#undef CONFIG_EEPRO100
305#undef CONFIG_TULIP
306#define CONFIG_RTL8139
307
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500308#ifndef CONFIG_PCI_PNP
Kumar Gala64bb6d12008-12-02 16:08:37 -0600309 #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS
310 #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500311 #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
312#endif
313
314#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
315#define CONFIG_DOS_PARTITION
316#define CONFIG_SCSI_AHCI
317
318#ifdef CONFIG_SCSI_AHCI
Rob Herring83f66482013-08-24 10:10:54 -0500319#define CONFIG_LIBATA
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500320#define CONFIG_SATA_ULI5288
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200321#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
322#define CONFIG_SYS_SCSI_MAX_LUN 1
323#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
324#define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500325#endif /* SCSCI */
326
327#endif /* CONFIG_PCI */
328
329
330#if defined(CONFIG_TSEC_ENET)
331
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500332#define CONFIG_MII 1 /* MII PHY management */
333#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
Kim Phillips177e58f2007-05-16 16:52:19 -0500334#define CONFIG_TSEC1 1
335#define CONFIG_TSEC1_NAME "eTSEC1"
336#define CONFIG_TSEC3 1
337#define CONFIG_TSEC3_NAME "eTSEC3"
Ed Swarthout52b98522007-07-27 01:50:51 -0500338
Liu Yu46269062008-10-10 11:40:58 +0800339#define CONFIG_PIXIS_SGMII_CMD
Andy Fleming3d19fad2008-08-31 16:33:28 -0500340#define CONFIG_FSL_SGMII_RISER 1
341#define SGMII_RISER_PHY_OFFSET 0x1c
342
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500343#define TSEC1_PHY_ADDR 0
344#define TSEC3_PHY_ADDR 1
345
Andy Fleming09b88df2007-08-15 20:03:25 -0500346#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
347#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
348
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500349#define TSEC1_PHYIDX 0
350#define TSEC3_PHYIDX 0
351
352#define CONFIG_ETHPRIME "eTSEC1"
353
354#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500355#endif /* CONFIG_TSEC_ENET */
356
357/*
358 * Environment
359 */
Jean-Christophe PLAGNIOL-VILLARD53db4cd2008-09-10 22:48:04 +0200360#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200361#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200362#define CONFIG_ENV_ADDR 0xfff80000
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500363#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200364#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x70000)
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500365#endif
Jean-Christophe PLAGNIOL-VILLARD7e1cda62008-09-10 22:48:06 +0200366#define CONFIG_ENV_SIZE 0x2000
367#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) */
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500368
369#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200370#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500371
Jon Loeligere63319f2007-06-13 13:22:08 -0500372/*
Jon Loeligered26c742007-07-10 09:10:49 -0500373 * BOOTP options
374 */
375#define CONFIG_BOOTP_BOOTFILESIZE
376#define CONFIG_BOOTP_BOOTPATH
377#define CONFIG_BOOTP_GATEWAY
378#define CONFIG_BOOTP_HOSTNAME
379
380
381/*
Jon Loeligere63319f2007-06-13 13:22:08 -0500382 * Command line configuration.
383 */
Jon Loeligere63319f2007-06-13 13:22:08 -0500384#define CONFIG_CMD_PING
385#define CONFIG_CMD_I2C
386#define CONFIG_CMD_MII
Kumar Gala489675d2008-09-22 23:40:42 -0500387#define CONFIG_CMD_IRQ
Becky Bruceee888da2010-06-17 11:37:25 -0500388#define CONFIG_CMD_REGINFO
Jon Loeligere63319f2007-06-13 13:22:08 -0500389
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500390#if defined(CONFIG_PCI)
Jon Loeligere63319f2007-06-13 13:22:08 -0500391 #define CONFIG_CMD_PCI
Ed Swarthout52b98522007-07-27 01:50:51 -0500392 #define CONFIG_CMD_SCSI
393 #define CONFIG_CMD_EXT2
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500394#endif
Jon Loeligere63319f2007-06-13 13:22:08 -0500395
Hongtao Jia7cfc5c82012-12-20 19:39:53 +0000396/*
397 * USB
398 */
399#define CONFIG_USB_EHCI
400
401#ifdef CONFIG_USB_EHCI
402#define CONFIG_CMD_USB
403#define CONFIG_USB_EHCI_PCI
404#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
405#define CONFIG_USB_STORAGE
406#define CONFIG_PCI_EHCI_DEVICE 0
407#endif
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500408
409#undef CONFIG_WATCHDOG /* watchdog disabled */
410
411/*
412 * Miscellaneous configurable options
413 */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200414#define CONFIG_SYS_LONGHELP /* undef to save memory */
Kim Phillipsf7758c12010-07-14 19:47:18 -0500415#define CONFIG_CMDLINE_EDITING /* Command-line editing */
416#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200417#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Jon Loeligere63319f2007-06-13 13:22:08 -0500418#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200419#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500420#else
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200421#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500422#endif
Jean-Christophe PLAGNIOL-VILLARD03836942008-10-16 15:01:15 +0200423#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
424#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
425#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500426
427/*
428 * For booting Linux, the board info and command line data
Kumar Gala39ffcc12011-04-28 10:13:41 -0500429 * have to be in the first 64 MB of memory, since this is
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500430 * the maximum mapped by the Linux kernel during initialization.
431 */
Kumar Gala39ffcc12011-04-28 10:13:41 -0500432#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
433#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500434
Jon Loeligere63319f2007-06-13 13:22:08 -0500435#if defined(CONFIG_CMD_KGDB)
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500436#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500437#endif
438
439/*
440 * Environment Configuration
441 */
442
443/* The mac addresses for all ethernet interface */
444#if defined(CONFIG_TSEC_ENET)
Kumar Gala0eb61912007-08-16 11:01:21 -0500445#define CONFIG_HAS_ETH0
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500446#define CONFIG_HAS_ETH1
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500447#endif
448
449#define CONFIG_IPADDR 192.168.1.251
450
451#define CONFIG_HOSTNAME 8544ds_unknown
Joe Hershberger257ff782011-10-13 13:03:47 +0000452#define CONFIG_ROOTPATH "/nfs/mpc85xx"
Joe Hershbergere4da2482011-10-13 13:03:48 +0000453#define CONFIG_BOOTFILE "8544ds/uImage.uboot"
Ed Swarthout52b98522007-07-27 01:50:51 -0500454#define CONFIG_UBOOTPATH 8544ds/u-boot.bin /* TFTP server */
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500455
Kumar Gala937176b2007-11-27 22:42:34 -0600456#define CONFIG_SERVERIP 192.168.1.1
457#define CONFIG_GATEWAYIP 192.168.1.1
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500458#define CONFIG_NETMASK 255.255.0.0
459
460#define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
461
462#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
Ed Swarthout52b98522007-07-27 01:50:51 -0500463#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500464
465#define CONFIG_BAUDRATE 115200
466
Ed Swarthout52b98522007-07-27 01:50:51 -0500467#define CONFIG_EXTRA_ENV_SETTINGS \
Marek Vasut0b3176c2012-09-23 17:41:24 +0200468"netdev=eth0\0" \
469"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
470"tftpflash=tftpboot $loadaddr $uboot; " \
471 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
472 " +$filesize; " \
473 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
474 " +$filesize; " \
475 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
476 " $filesize; " \
477 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
478 " +$filesize; " \
479 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
480 " $filesize\0" \
481"consoledev=ttyS0\0" \
482"ramdiskaddr=2000000\0" \
483"ramdiskfile=8544ds/ramdisk.uboot\0" \
484"fdtaddr=c00000\0" \
485"fdtfile=8544ds/mpc8544ds.dtb\0" \
486"bdev=sda3\0"
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500487
488#define CONFIG_NFSBOOTCOMMAND \
489 "setenv bootargs root=/dev/nfs rw " \
490 "nfsroot=$serverip:$rootpath " \
491 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
492 "console=$consoledev,$baudrate $othbootargs;" \
493 "tftp $loadaddr $bootfile;" \
Kumar Gala937176b2007-11-27 22:42:34 -0600494 "tftp $fdtaddr $fdtfile;" \
495 "bootm $loadaddr - $fdtaddr"
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500496
Ed Swarthout52b98522007-07-27 01:50:51 -0500497#define CONFIG_RAMBOOTCOMMAND \
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500498 "setenv bootargs root=/dev/ram rw " \
499 "console=$consoledev,$baudrate $othbootargs;" \
500 "tftp $ramdiskaddr $ramdiskfile;" \
501 "tftp $loadaddr $bootfile;" \
Kumar Gala937176b2007-11-27 22:42:34 -0600502 "tftp $fdtaddr $fdtfile;" \
503 "bootm $loadaddr $ramdiskaddr $fdtaddr"
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500504
Ed Swarthout52b98522007-07-27 01:50:51 -0500505#define CONFIG_BOOTCOMMAND \
506 "setenv bootargs root=/dev/$bdev rw " \
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500507 "console=$consoledev,$baudrate $othbootargs;" \
508 "tftp $loadaddr $bootfile;" \
Kumar Gala937176b2007-11-27 22:42:34 -0600509 "tftp $fdtaddr $fdtfile;" \
510 "bootm $loadaddr - $fdtaddr"
Jon Loeliger3e2d0912007-04-11 16:50:57 -0500511
512#endif /* __CONFIG_H */