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git01.mediatek.com / filogic / uboot / 3c1b9f1b0a45653bf1e1f41d736dbe03dae308ab / . / arch / arm / dts / rk3036.dtsi
blob: 4f4421768de0ee8d2026399110c1530f3e2ca815 [file] [log] [blame]
huang lin1bce6422015-11-17 14:20:15 +0800[diff] [blame]1/*
2 * SPDX-License-Identifier: GPL-2.0+
3 */
4
5#include <dt-bindings/gpio/gpio.h>
6#include <dt-bindings/interrupt-controller/irq.h>
7#include <dt-bindings/interrupt-controller/arm-gic.h>
8#include <dt-bindings/pinctrl/rockchip.h>
9#include <dt-bindings/clock/rk3036-cru.h>
10#include "skeleton.dtsi"
11
12/ {
13 compatible = "rockchip,rk3036";
14
15 interrupt-parent = <&gic>;
16
17 aliases {
18 gpio0 = &gpio0;
19 gpio1 = &gpio1;
20 gpio2 = &gpio2;
21 i2c1 = &i2c1;
22 serial0 = &uart0;
23 serial1 = &uart1;
24 serial2 = &uart2;
25 mmc0 = &emmc;
Eddie Cai13ecd1e2017-02-20 14:03:01 +0800[diff] [blame]26 mmc1 = &sdmmc;
huang lin1bce6422015-11-17 14:20:15 +0800[diff] [blame]27 };
28
29 memory {
30 device_type = "memory";
31 reg = <0x60000000 0x40000000>;
32 };
33
34 arm-pmu {
35 compatible = "arm,cortex-a7-pmu";
36 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
37 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
38 interrupt-affinity = <&cpu0>, <&cpu1>;
39 };
40
41 cpus {
42 #address-cells = <1>;
43 #size-cells = <0>;
44 enable-method = "rockchip,rk3036-smp";
45
46 cpu0: cpu@f00 {
47 device_type = "cpu";
48 compatible = "arm,cortex-a7";
49 reg = <0xf00>;
50 operating-points = <
51 /* KHz uV */
52 816000 1000000
53 >;
54 #cooling-cells = <2>; /* min followed by max */
55 clock-latency = <40000>;
56 clocks = <&cru ARMCLK>;
57 resets = <&cru SRST_CORE0>;
58 };
59 cpu1: cpu@f01 {
60 device_type = "cpu";
61 compatible = "arm,cortex-a7";
62 reg = <0xf01>;
63 resets = <&cru SRST_CORE1>;
64 };
65 };
66
67 amba {
68 compatible = "arm,amba-bus";
69 #address-cells = <1>;
70 #size-cells = <1>;
71 ranges;
72
73 pdma: pdma@20078000 {
74 compatible = "arm,pl330", "arm,primecell";
75 reg = <0x20078000 0x4000>;
76 arm,pl330-broken-no-flushp;
77 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
78 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
79 #dma-cells = <1>;
80 clocks = <&cru ACLK_DMAC2>;
81 clock-names = "apb_pclk";
82 };
83 };
84
85 xin24m: oscillator {
86 compatible = "fixed-clock";
87 clock-frequency = <24000000>;
88 clock-output-names = "xin24m";
89 #clock-cells = <0>;
90 };
91
92 timer {
93 compatible = "arm,armv7-timer";
94 arm,cpu-registers-not-fw-configured;
95 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
96 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
97 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
98 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
99 clock-frequency = <24000000>;
100 };
101
102 cru: clock-controller@20000000 {
103 compatible = "rockchip,rk3036-cru";
104 reg = <0x20000000 0x1000>;
105 rockchip,grf = <&grf>;
106 #clock-cells = <1>;
107 #reset-cells = <1>;
108 assigned-clocks = <&cru PLL_GPLL>;
109 assigned-clock-rates = <594000000>;
110 };
111
112 uart0: serial@20060000 {
113 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
114 reg = <0x20060000 0x100>;
115 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
116 reg-shift = <2>;
117 reg-io-width = <4>;
118 clock-frequency = <24000000>;
119 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
120 clock-names = "baudclk", "apb_pclk";
121 pinctrl-names = "default";
122 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
123 };
124
125 uart1: serial@20064000 {
126 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
127 reg = <0x20064000 0x100>;
128 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
129 reg-shift = <2>;
130 reg-io-width = <4>;
131 clock-frequency = <24000000>;
132 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
133 clock-names = "baudclk", "apb_pclk";
134 pinctrl-names = "default";
135 pinctrl-0 = <&uart1_xfer>;
136 };
137
138 uart2: serial@20068000 {
139 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
140 reg = <0x20068000 0x100>;
141 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
142 reg-shift = <2>;
143 reg-io-width = <4>;
144 clock-frequency = <24000000>;
145 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
146 clock-names = "baudclk", "apb_pclk";
147 pinctrl-names = "default";
148 pinctrl-0 = <&uart2_xfer>;
149 };
150
151 pwm0: pwm@20050000 {
152 compatible = "rockchip,rk2928-pwm";
153 reg = <0x20050000 0x10>;
154 #pwm-cells = <3>;
155 pinctrl-names = "default";
156 pinctrl-0 = <&pwm0_pin>;
157 clocks = <&cru PCLK_PWM>;
158 clock-names = "pwm";
159 status = "disabled";
160 };
161
162 pwm1: pwm@20050010 {
163 compatible = "rockchip,rk2928-pwm";
164 reg = <0x20050010 0x10>;
165 #pwm-cells = <3>;
166 pinctrl-names = "default";
167 pinctrl-0 = <&pwm1_pin>;
168 clocks = <&cru PCLK_PWM>;
169 clock-names = "pwm";
170 status = "disabled";
171 };
172
173 pwm2: pwm@20050020 {
174 compatible = "rockchip,rk2928-pwm";
175 reg = <0x20050020 0x10>;
176 #pwm-cells = <3>;
177 pinctrl-names = "default";
178 pinctrl-0 = <&pwm2_pin>;
179 clocks = <&cru PCLK_PWM>;
180 clock-names = "pwm";
181 status = "disabled";
182 };
183
184 pwm3: pwm@20050030 {
185 compatible = "rockchip,rk2928-pwm";
186 reg = <0x20050030 0x10>;
187 #pwm-cells = <2>;
188 pinctrl-names = "default";
189 pinctrl-0 = <&pwm3_pin>;
190 clocks = <&cru PCLK_PWM>;
191 clock-names = "pwm";
192 status = "disabled";
193 };
194
195 sram: sram@10080000 {
196 compatible = "rockchip,rk3036-smp-sram", "mmio-sram";
197 reg = <0x10080000 0x2000>;
198 };
199
200 gic: interrupt-controller@10139000 {
201 compatible = "arm,gic-400";
202 interrupt-controller;
203 #interrupt-cells = <3>;
204 #address-cells = <0>;
205
206 reg = <0x10139000 0x1000>,
207 <0x1013a000 0x1000>,
208 <0x1013c000 0x2000>,
209 <0x1013e000 0x2000>;
210 interrupts = <GIC_PPI 9 0xf04>;
211 };
212
213 grf: syscon@20008000 {
214 compatible = "rockchip,rk3036-grf", "syscon";
215 reg = <0x20008000 0x1000>;
216 };
217
218 usb_otg: usb@10180000 {
219 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
220 "snps,dwc2";
221 reg = <0x10180000 0x40000>;
222 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
223 clocks = <&cru HCLK_OTG0>;
224 clock-names = "otg";
225 dr_mode = "otg";
226 g-np-tx-fifo-size = <16>;
227 g-rx-fifo-size = <275>;
228 g-tx-fifo-size = <256 128 128 64 64 32>;
229 g-use-dma;
230 status = "disabled";
231 };
232
233 usb_host: usb@101c0000 {
234 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
235 "snps,dwc2";
236 reg = <0x101c0000 0x40000>;
237 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
238 clocks = <&cru HCLK_OTG1>;
239 clock-names = "otg";
240 dr_mode = "host";
241 status = "disabled";
242 };
243
244 emmc: dwmmc@1021c000 {
245 compatible = "rockchip,rk3288-dw-mshc";
246 clock-frequency = <37500000>;
247 clock-freq-min-max = <400000 37500000>;
248 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
249 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
250 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
251 dmas = <&pdma 12>;
252 dma-names = "rx-tx";
253 fifo-depth = <0x100>;
254 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
255 reg = <0x1021c000 0x4000>;
256 broken-cd;
257 bus-width = <8>;
258 cap-mmc-highspeed;
259 mmc-ddr-1_8v;
260 disable-wp;
huang linb1b71cd2015-11-17 14:20:24 +0800[diff] [blame]261 fifo-mode;
huang lin1bce6422015-11-17 14:20:15 +0800[diff] [blame]262 non-removable;
263 num-slots = <1>;
264 default-sample-phase = <158>;
265 pinctrl-names = "default";
266 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
267 };
268
Eddie Cai13ecd1e2017-02-20 14:03:01 +0800[diff] [blame]269 sdmmc: dwmmc@10214000 {
270 compatible = "rockchip,rk3036-dw-mshc", "rockchip,rk3288-dw-mshc";
271 reg = <0x10214000 0x4000>;
272 clock-frequency = <37500000>;
273 max-frequency = <37500000>;
274 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
275 clock-names = "biu", "ciu";
276 fifo-depth = <0x100>;
277 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
278 status = "disabled";
279 };
280
huang lin1bce6422015-11-17 14:20:15 +0800[diff] [blame]281 pinctrl: pinctrl {
282 compatible = "rockchip,rk3036-pinctrl";
283 rockchip,grf = <&grf>;
284 #address-cells = <1>;
285 #size-cells = <1>;
286 ranges;
287
288 gpio0: gpio0@2007c000 {
289 compatible = "rockchip,gpio-bank";
290 reg = <0x2007c000 0x100>;
291 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
292 clocks = <&cru PCLK_GPIO0>;
293
294 gpio-controller;
295 #gpio-cells = <2>;
296
297 interrupt-controller;
298 #interrupt-cells = <2>;
299 };
300
301 gpio1: gpio1@20080000 {
302 compatible = "rockchip,gpio-bank";
303 reg = <0x20080000 0x100>;
304 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
305 clocks = <&cru PCLK_GPIO1>;
306
307 gpio-controller;
308 #gpio-cells = <2>;
309
310 interrupt-controller;
311 #interrupt-cells = <2>;
312 };
313
314 gpio2: gpio2@20084000 {
315 compatible = "rockchip,gpio-bank";
316 reg = <0x20084000 0x100>;
317 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
318 clocks = <&cru PCLK_GPIO2>;
319
320 gpio-controller;
321 #gpio-cells = <2>;
322
323 interrupt-controller;
324 #interrupt-cells = <2>;
325 };
326
327 pcfg_pull_up: pcfg-pull-up {
328 bias-pull-up;
329 };
330
331 pcfg_pull_down: pcfg-pull-down {
332 bias-pull-down;
333 };
334
335 pcfg_pull_none: pcfg-pull-none {
336 bias-disable;
337 };
338
339 emmc {
340 /*
341 * We run eMMC at max speed; bump up drive strength.
342 * We also have external pulls, so disable the internal ones.
343 */
344 emmc_clk: emmc-clk {
345 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
346 };
347
348 emmc_cmd: emmc-cmd {
349 rockchip,pins = <2 1 RK_FUNC_2 &pcfg_pull_none>;
350 };
351
352 emmc_bus8: emmc-bus8 {
353 rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>,
354 <1 25 RK_FUNC_2 &pcfg_pull_none>,
355 <1 26 RK_FUNC_2 &pcfg_pull_none>,
356 <1 27 RK_FUNC_2 &pcfg_pull_none>;
357 /*
358 <1 28 RK_FUNC_2 &pcfg_pull_up>,
359 <1 29 RK_FUNC_2 &pcfg_pull_up>,
360 <1 30 RK_FUNC_2 &pcfg_pull_up>,
361 <1 31 RK_FUNC_2 &pcfg_pull_up>;
362 */
363 };
364 };
365
366 uart0 {
367 uart0_xfer: uart0-xfer {
368 rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_none>,
369 <0 17 RK_FUNC_1 &pcfg_pull_none>;
370 };
371
372 uart0_cts: uart0-cts {
373 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>;
374 };
375
376 uart0_rts: uart0-rts {
377 rockchip,pins = <0 19 RK_FUNC_1 &pcfg_pull_none>;
378 };
379 };
380
381 uart1 {
382 uart1_xfer: uart1-xfer {
383 rockchip,pins = <2 22 RK_FUNC_1 &pcfg_pull_none>,
384 <2 23 RK_FUNC_1 &pcfg_pull_none>;
385 };
386 /* no rts / cts for uart1 */
387 };
388
389 uart2 {
390 uart2_xfer: uart2-xfer {
391 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_none>,
392 <1 19 RK_FUNC_2 &pcfg_pull_none>;
393 };
394 /* no rts / cts for uart2 */
395 };
396
397 pwm0 {
398 pwm0_pin: pwm0-pin {
399 rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>;
400 };
401 };
402
403 pwm1 {
404 pwm1_pin: pwm1-pin {
405 rockchip,pins = <0 1 RK_FUNC_2 &pcfg_pull_none>;
406 };
407 };
408
409 pwm2 {
410 pwm2_pin: pwm2-pin {
411 rockchip,pins = <0 1 2 &pcfg_pull_none>;
412 };
413 };
414
415 pwm3 {
416 pwm3_pin: pwm3-pin {
417 rockchip,pins = <0 27 1 &pcfg_pull_none>;
418 };
419 };
420
421 i2c1 {
422 i2c1_xfer: i2c1-xfer {
423 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>,
424 <0 3 RK_FUNC_1 &pcfg_pull_none>;
425 };
426 };
427 };
428
429 i2c1: i2c@20056000 {
430 compatible = "rockchip,rk3288-i2c";
431 reg = <0x20056000 0x1000>;
432 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
433 #address-cells = <1>;
434 #size-cells = <0>;
435 clock-names = "i2c";
436 clocks = <&cru PCLK_I2C1>;
437 pinctrl-names = "default";
438 pinctrl-0 = <&i2c1_xfer>;
439 status = "disabled";
440 };
441};