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git01.mediatek.com / filogic / uboot / 1bce642b956a8423c4e980f339ff2a880f9e53cc / . / arch / arm / dts / rk3036.dtsi
blob: 0daae1ec309663b6fa5bf2a7a53b26518bc9747c [file] [log] [blame]
huang lin1bce6422015-11-17 14:20:15 +0800[diff] [blame^]1/*
2 * SPDX-License-Identifier: GPL-2.0+
3 */
4
5#include <dt-bindings/gpio/gpio.h>
6#include <dt-bindings/interrupt-controller/irq.h>
7#include <dt-bindings/interrupt-controller/arm-gic.h>
8#include <dt-bindings/pinctrl/rockchip.h>
9#include <dt-bindings/clock/rk3036-cru.h>
10#include "skeleton.dtsi"
11
12/ {
13 compatible = "rockchip,rk3036";
14
15 interrupt-parent = <&gic>;
16
17 aliases {
18 gpio0 = &gpio0;
19 gpio1 = &gpio1;
20 gpio2 = &gpio2;
21 i2c1 = &i2c1;
22 serial0 = &uart0;
23 serial1 = &uart1;
24 serial2 = &uart2;
25 mmc0 = &emmc;
26 };
27
28 memory {
29 device_type = "memory";
30 reg = <0x60000000 0x40000000>;
31 };
32
33 arm-pmu {
34 compatible = "arm,cortex-a7-pmu";
35 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>,
36 <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
37 interrupt-affinity = <&cpu0>, <&cpu1>;
38 };
39
40 cpus {
41 #address-cells = <1>;
42 #size-cells = <0>;
43 enable-method = "rockchip,rk3036-smp";
44
45 cpu0: cpu@f00 {
46 device_type = "cpu";
47 compatible = "arm,cortex-a7";
48 reg = <0xf00>;
49 operating-points = <
50 /* KHz uV */
51 816000 1000000
52 >;
53 #cooling-cells = <2>; /* min followed by max */
54 clock-latency = <40000>;
55 clocks = <&cru ARMCLK>;
56 resets = <&cru SRST_CORE0>;
57 };
58 cpu1: cpu@f01 {
59 device_type = "cpu";
60 compatible = "arm,cortex-a7";
61 reg = <0xf01>;
62 resets = <&cru SRST_CORE1>;
63 };
64 };
65
66 amba {
67 compatible = "arm,amba-bus";
68 #address-cells = <1>;
69 #size-cells = <1>;
70 ranges;
71
72 pdma: pdma@20078000 {
73 compatible = "arm,pl330", "arm,primecell";
74 reg = <0x20078000 0x4000>;
75 arm,pl330-broken-no-flushp;
76 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
77 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
78 #dma-cells = <1>;
79 clocks = <&cru ACLK_DMAC2>;
80 clock-names = "apb_pclk";
81 };
82 };
83
84 xin24m: oscillator {
85 compatible = "fixed-clock";
86 clock-frequency = <24000000>;
87 clock-output-names = "xin24m";
88 #clock-cells = <0>;
89 };
90
91 timer {
92 compatible = "arm,armv7-timer";
93 arm,cpu-registers-not-fw-configured;
94 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
95 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
96 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
97 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
98 clock-frequency = <24000000>;
99 };
100
101 cru: clock-controller@20000000 {
102 compatible = "rockchip,rk3036-cru";
103 reg = <0x20000000 0x1000>;
104 rockchip,grf = <&grf>;
105 #clock-cells = <1>;
106 #reset-cells = <1>;
107 assigned-clocks = <&cru PLL_GPLL>;
108 assigned-clock-rates = <594000000>;
109 };
110
111 uart0: serial@20060000 {
112 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
113 reg = <0x20060000 0x100>;
114 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
115 reg-shift = <2>;
116 reg-io-width = <4>;
117 clock-frequency = <24000000>;
118 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
119 clock-names = "baudclk", "apb_pclk";
120 pinctrl-names = "default";
121 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
122 };
123
124 uart1: serial@20064000 {
125 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
126 reg = <0x20064000 0x100>;
127 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
128 reg-shift = <2>;
129 reg-io-width = <4>;
130 clock-frequency = <24000000>;
131 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
132 clock-names = "baudclk", "apb_pclk";
133 pinctrl-names = "default";
134 pinctrl-0 = <&uart1_xfer>;
135 };
136
137 uart2: serial@20068000 {
138 compatible = "rockchip,rk3036-uart", "snps,dw-apb-uart";
139 reg = <0x20068000 0x100>;
140 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
141 reg-shift = <2>;
142 reg-io-width = <4>;
143 clock-frequency = <24000000>;
144 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
145 clock-names = "baudclk", "apb_pclk";
146 pinctrl-names = "default";
147 pinctrl-0 = <&uart2_xfer>;
148 };
149
150 pwm0: pwm@20050000 {
151 compatible = "rockchip,rk2928-pwm";
152 reg = <0x20050000 0x10>;
153 #pwm-cells = <3>;
154 pinctrl-names = "default";
155 pinctrl-0 = <&pwm0_pin>;
156 clocks = <&cru PCLK_PWM>;
157 clock-names = "pwm";
158 status = "disabled";
159 };
160
161 pwm1: pwm@20050010 {
162 compatible = "rockchip,rk2928-pwm";
163 reg = <0x20050010 0x10>;
164 #pwm-cells = <3>;
165 pinctrl-names = "default";
166 pinctrl-0 = <&pwm1_pin>;
167 clocks = <&cru PCLK_PWM>;
168 clock-names = "pwm";
169 status = "disabled";
170 };
171
172 pwm2: pwm@20050020 {
173 compatible = "rockchip,rk2928-pwm";
174 reg = <0x20050020 0x10>;
175 #pwm-cells = <3>;
176 pinctrl-names = "default";
177 pinctrl-0 = <&pwm2_pin>;
178 clocks = <&cru PCLK_PWM>;
179 clock-names = "pwm";
180 status = "disabled";
181 };
182
183 pwm3: pwm@20050030 {
184 compatible = "rockchip,rk2928-pwm";
185 reg = <0x20050030 0x10>;
186 #pwm-cells = <2>;
187 pinctrl-names = "default";
188 pinctrl-0 = <&pwm3_pin>;
189 clocks = <&cru PCLK_PWM>;
190 clock-names = "pwm";
191 status = "disabled";
192 };
193
194 sram: sram@10080000 {
195 compatible = "rockchip,rk3036-smp-sram", "mmio-sram";
196 reg = <0x10080000 0x2000>;
197 };
198
199 gic: interrupt-controller@10139000 {
200 compatible = "arm,gic-400";
201 interrupt-controller;
202 #interrupt-cells = <3>;
203 #address-cells = <0>;
204
205 reg = <0x10139000 0x1000>,
206 <0x1013a000 0x1000>,
207 <0x1013c000 0x2000>,
208 <0x1013e000 0x2000>;
209 interrupts = <GIC_PPI 9 0xf04>;
210 };
211
212 grf: syscon@20008000 {
213 compatible = "rockchip,rk3036-grf", "syscon";
214 reg = <0x20008000 0x1000>;
215 };
216
217 usb_otg: usb@10180000 {
218 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
219 "snps,dwc2";
220 reg = <0x10180000 0x40000>;
221 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
222 clocks = <&cru HCLK_OTG0>;
223 clock-names = "otg";
224 dr_mode = "otg";
225 g-np-tx-fifo-size = <16>;
226 g-rx-fifo-size = <275>;
227 g-tx-fifo-size = <256 128 128 64 64 32>;
228 g-use-dma;
229 status = "disabled";
230 };
231
232 usb_host: usb@101c0000 {
233 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
234 "snps,dwc2";
235 reg = <0x101c0000 0x40000>;
236 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
237 clocks = <&cru HCLK_OTG1>;
238 clock-names = "otg";
239 dr_mode = "host";
240 status = "disabled";
241 };
242
243 emmc: dwmmc@1021c000 {
244 compatible = "rockchip,rk3288-dw-mshc";
245 clock-frequency = <37500000>;
246 clock-freq-min-max = <400000 37500000>;
247 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
248 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
249 clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
250 dmas = <&pdma 12>;
251 dma-names = "rx-tx";
252 fifo-depth = <0x100>;
253 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
254 reg = <0x1021c000 0x4000>;
255 broken-cd;
256 bus-width = <8>;
257 cap-mmc-highspeed;
258 mmc-ddr-1_8v;
259 disable-wp;
260 non-removable;
261 num-slots = <1>;
262 default-sample-phase = <158>;
263 pinctrl-names = "default";
264 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
265 };
266
267 pinctrl: pinctrl {
268 compatible = "rockchip,rk3036-pinctrl";
269 rockchip,grf = <&grf>;
270 #address-cells = <1>;
271 #size-cells = <1>;
272 ranges;
273
274 gpio0: gpio0@2007c000 {
275 compatible = "rockchip,gpio-bank";
276 reg = <0x2007c000 0x100>;
277 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
278 clocks = <&cru PCLK_GPIO0>;
279
280 gpio-controller;
281 #gpio-cells = <2>;
282
283 interrupt-controller;
284 #interrupt-cells = <2>;
285 };
286
287 gpio1: gpio1@20080000 {
288 compatible = "rockchip,gpio-bank";
289 reg = <0x20080000 0x100>;
290 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
291 clocks = <&cru PCLK_GPIO1>;
292
293 gpio-controller;
294 #gpio-cells = <2>;
295
296 interrupt-controller;
297 #interrupt-cells = <2>;
298 };
299
300 gpio2: gpio2@20084000 {
301 compatible = "rockchip,gpio-bank";
302 reg = <0x20084000 0x100>;
303 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
304 clocks = <&cru PCLK_GPIO2>;
305
306 gpio-controller;
307 #gpio-cells = <2>;
308
309 interrupt-controller;
310 #interrupt-cells = <2>;
311 };
312
313 pcfg_pull_up: pcfg-pull-up {
314 bias-pull-up;
315 };
316
317 pcfg_pull_down: pcfg-pull-down {
318 bias-pull-down;
319 };
320
321 pcfg_pull_none: pcfg-pull-none {
322 bias-disable;
323 };
324
325 emmc {
326 /*
327 * We run eMMC at max speed; bump up drive strength.
328 * We also have external pulls, so disable the internal ones.
329 */
330 emmc_clk: emmc-clk {
331 rockchip,pins = <2 4 RK_FUNC_2 &pcfg_pull_none>;
332 };
333
334 emmc_cmd: emmc-cmd {
335 rockchip,pins = <2 1 RK_FUNC_2 &pcfg_pull_none>;
336 };
337
338 emmc_bus8: emmc-bus8 {
339 rockchip,pins = <1 24 RK_FUNC_2 &pcfg_pull_none>,
340 <1 25 RK_FUNC_2 &pcfg_pull_none>,
341 <1 26 RK_FUNC_2 &pcfg_pull_none>,
342 <1 27 RK_FUNC_2 &pcfg_pull_none>;
343 /*
344 <1 28 RK_FUNC_2 &pcfg_pull_up>,
345 <1 29 RK_FUNC_2 &pcfg_pull_up>,
346 <1 30 RK_FUNC_2 &pcfg_pull_up>,
347 <1 31 RK_FUNC_2 &pcfg_pull_up>;
348 */
349 };
350 };
351
352 uart0 {
353 uart0_xfer: uart0-xfer {
354 rockchip,pins = <0 16 RK_FUNC_1 &pcfg_pull_none>,
355 <0 17 RK_FUNC_1 &pcfg_pull_none>;
356 };
357
358 uart0_cts: uart0-cts {
359 rockchip,pins = <0 18 RK_FUNC_1 &pcfg_pull_none>;
360 };
361
362 uart0_rts: uart0-rts {
363 rockchip,pins = <0 19 RK_FUNC_1 &pcfg_pull_none>;
364 };
365 };
366
367 uart1 {
368 uart1_xfer: uart1-xfer {
369 rockchip,pins = <2 22 RK_FUNC_1 &pcfg_pull_none>,
370 <2 23 RK_FUNC_1 &pcfg_pull_none>;
371 };
372 /* no rts / cts for uart1 */
373 };
374
375 uart2 {
376 uart2_xfer: uart2-xfer {
377 rockchip,pins = <1 18 RK_FUNC_2 &pcfg_pull_none>,
378 <1 19 RK_FUNC_2 &pcfg_pull_none>;
379 };
380 /* no rts / cts for uart2 */
381 };
382
383 pwm0 {
384 pwm0_pin: pwm0-pin {
385 rockchip,pins = <0 0 RK_FUNC_2 &pcfg_pull_none>;
386 };
387 };
388
389 pwm1 {
390 pwm1_pin: pwm1-pin {
391 rockchip,pins = <0 1 RK_FUNC_2 &pcfg_pull_none>;
392 };
393 };
394
395 pwm2 {
396 pwm2_pin: pwm2-pin {
397 rockchip,pins = <0 1 2 &pcfg_pull_none>;
398 };
399 };
400
401 pwm3 {
402 pwm3_pin: pwm3-pin {
403 rockchip,pins = <0 27 1 &pcfg_pull_none>;
404 };
405 };
406
407 i2c1 {
408 i2c1_xfer: i2c1-xfer {
409 rockchip,pins = <0 2 RK_FUNC_1 &pcfg_pull_none>,
410 <0 3 RK_FUNC_1 &pcfg_pull_none>;
411 };
412 };
413 };
414
415 i2c1: i2c@20056000 {
416 compatible = "rockchip,rk3288-i2c";
417 reg = <0x20056000 0x1000>;
418 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
419 #address-cells = <1>;
420 #size-cells = <0>;
421 clock-names = "i2c";
422 clocks = <&cru PCLK_I2C1>;
423 pinctrl-names = "default";
424 pinctrl-0 = <&i2c1_xfer>;
425 status = "disabled";
426 };
427};