| Bob Liu | 52a310c | 2012-08-16 11:10:41 +0800 | [diff] [blame] | 1 | /* DO NOT EDIT THIS FILE |
| 2 | * Automatically generated by generate-def-headers.xsl |
| 3 | * DO NOT EDIT THIS FILE |
| 4 | */ |
| 5 | |
| 6 | #ifndef __BFIN_DEF_ADSP_BF609_proc__ |
| 7 | #define __BFIN_DEF_ADSP_BF609_proc__ |
| 8 | |
| 9 | #include "../mach-common/ADSP-EDN-core_def.h" |
| 10 | |
| 11 | #define RSI_CLK_CONTROL 0xFFC00604 /* RSI0 Clock Control Register */ |
| 12 | #define RSI_ARGUMENT 0xFFC00608 /* RSI0 Argument Register */ |
| 13 | #define RSI_COMMAND 0xFFC0060C /* RSI0 Command Register */ |
| 14 | #define RSI_RESP_CMD 0xFFC00610 /* RSI0 Response Command Register */ |
| 15 | #define RSI_RESPONSE0 0xFFC00614 /* RSI0 Response 0 Register */ |
| 16 | #define RSI_RESPONSE1 0xFFC00618 /* RSI0 Response 1 Register */ |
| 17 | #define RSI_RESPONSE2 0xFFC0061C /* RSI0 Response 2 Register */ |
| 18 | #define RSI_RESPONSE3 0xFFC00620 /* RSI0 Response 3 Register */ |
| 19 | #define RSI_DATA_TIMER 0xFFC00624 /* RSI0 Data Timer Register */ |
| 20 | #define RSI_DATA_LGTH 0xFFC00628 /* RSI0 Data Length Register */ |
| 21 | #define RSI_DATA_CONTROL 0xFFC0062C /* RSI0 Data Control Register */ |
| 22 | #define RSI_DATA_CNT 0xFFC00630 /* RSI0 Data Count Register */ |
| 23 | #define RSI_STATUS 0xFFC00634 /* RSI0 Status Register */ |
| 24 | #define RSI_STATUSCL 0xFFC00638 /* RSI0 Status Clear Register */ |
| 25 | #define RSI_IMSK0 0xFFC0063C /* RSI0 Interrupt 0 Mask Register */ |
| 26 | #define RSI_IMSK1 0xFFC00640 /* RSI0 Interrupt 1 Mask Register */ |
| 27 | #define RSI_FIFO_CNT 0xFFC00648 /* RSI0 FIFO Counter Register */ |
| 28 | #define RSI_CEATA_CONTROL 0xFFC0064C /* RSI0 contains bit to dis CCS gen */ |
| 29 | #define RSI_BOOT_TCNTR 0xFFC00650 /* RSI0 Boot Timing Counter Register */ |
| 30 | #define RSI_BACK_TOUT 0xFFC00654 /* RSI0 Boot Ack Timeout Register */ |
| 31 | #define RSI_SLP_WKUP_TOUT 0xFFC00658 /* RSI0 Sleep Wakeup Timeout Register */ |
| 32 | #define RSI_BLKSZ 0xFFC0065C /* RSI0 Block Size Register */ |
| 33 | #define RSI_FIFO 0xFFC00680 /* RSI0 Data FIFO Register */ |
| 34 | #define RSI_ESTAT 0xFFC006C0 /* RSI0 Exception Status Register */ |
| 35 | #define RSI_EMASK 0xFFC006C4 /* RSI0 Exception Mask Register */ |
| 36 | #define RSI_CONFIG 0xFFC006C8 /* RSI0 Configuration Register */ |
| 37 | #define RSI_RD_WAIT_EN 0xFFC006CC /* RSI0 Read Wait Enable Register */ |
| 38 | #define RSI_PID0 0xFFC006D0 /* RSI0 Peripheral Id Register */ |
| 39 | #define RSI_PID1 0xFFC006D4 /* RSI0 Peripheral Id Register */ |
| 40 | #define RSI_PID2 0xFFC006D8 /* RSI0 Peripheral Id Register */ |
| 41 | #define RSI_PID3 0xFFC006DC /* RSI0 Peripheral Id Register */ |
| 42 | |
| 43 | #define TWI0_CLKDIV 0xFFC01E00 /* TWI0 SCL Clock Divider */ |
| 44 | #define TWI1_CLKDIV 0xFFC01F00 /* TWI1 SCL Clock Divider */ |
| 45 | |
| 46 | #define UART0_REVID 0xFFC02000 /* UART0 Revision ID Register */ |
| 47 | #define UART0_CTL 0xFFC02004 /* UART0 Control Register */ |
| 48 | #define UART0_STAT 0xFFC02008 /* UART0 Status Register */ |
| 49 | #define UART0_SCR 0xFFC0200C /* UART0 Scratch Register */ |
| 50 | #define UART0_CLK 0xFFC02010 /* UART0 Clock Rate Register */ |
| 51 | #define UART0_IMSK 0xFFC02014 /* UART0 Interrupt Mask Register */ |
| 52 | #define UART0_IMSK_SET 0xFFC02018 /* UART0 Interrupt Mask Set Register */ |
| 53 | #define UART0_IMSK_CLR 0xFFC0201C /* UART0 Interrupt Mask Clear Register */ |
| 54 | #define UART0_RBR 0xFFC02020 /* UART0 Receive Buffer Register */ |
| 55 | #define UART0_THR 0xFFC02024 /* UART0 Transmit Hold Register */ |
| 56 | #define UART0_TAIP 0xFFC02028 /* UART0 TX Address/Insert Pulse Reg */ |
| 57 | #define UART0_TSR 0xFFC0202C /* UART0 Transmit Shift Register */ |
| 58 | #define UART0_RSR 0xFFC02030 /* UART0 Receive Shift Register */ |
| 59 | #define UART0_TXCNT 0xFFC02034 /* UART0 Transmit Counter Register */ |
| 60 | #define UART0_RXCNT 0xFFC02038 /* UART0 Receive Counter Register */ |
| 61 | #define UART1_REVID 0xFFC02400 /* UART1 Revision ID Register */ |
| 62 | #define UART1_CTL 0xFFC02404 /* UART1 Control Register */ |
| 63 | #define UART1_STAT 0xFFC02408 /* UART1 Status Register */ |
| 64 | #define UART1_SCR 0xFFC0240C /* UART1 Scratch Register */ |
| 65 | #define UART1_CLK 0xFFC02410 /* UART1 Clock Rate Register */ |
| 66 | #define UART1_IMSK 0xFFC02414 /* UART1 Interrupt Mask Register */ |
| 67 | #define UART1_IMSK_SET 0xFFC02418 /* UART1 Interrupt Mask Set Register */ |
| 68 | #define UART1_IMSK_CLR 0xFFC0241C /* UART1 Interrupt Mask Clear Register */ |
| 69 | #define UART1_RBR 0xFFC02420 /* UART1 Receive Buffer Register */ |
| 70 | #define UART1_THR 0xFFC02424 /* UART1 Transmit Hold Register */ |
| 71 | #define UART1_TAIP 0xFFC02428 /* UART1 TX Address/Insert Pulse Reg */ |
| 72 | #define UART1_TSR 0xFFC0242C /* UART1 Transmit Shift Register */ |
| 73 | #define UART1_RSR 0xFFC02430 /* UART1 Receive Shift Register */ |
| 74 | #define UART1_TXCNT 0xFFC02434 /* UART1 Transmit Counter Register */ |
| 75 | #define UART1_RXCNT 0xFFC02438 /* UART1 Receive Counter Register */ |
| 76 | |
| 77 | #define PORTA_FER 0xFFC03000 /* PORTA Port x Function Enable */ |
| 78 | #define PORTA_FER_SET 0xFFC03004 /* PORTA Port x Function Enable Set */ |
| 79 | #define PORTA_FER_CLR 0xFFC03008 /* PORTA Port x Function Enable Clear */ |
| 80 | #define PORTA_MUX 0xFFC03030 /* PORTA Port x Multiplexer Control */ |
| 81 | #define PORTB_FER 0xFFC03080 /* PORTB Port x Function Enable */ |
| 82 | #define PORTB_FER_SET 0xFFC03084 /* PORTB Port x Function Enable Set */ |
| 83 | #define PORTB_FER_CLR 0xFFC03088 /* PORTB Port x Function Enable Clear */ |
| 84 | #define PORTB_MUX 0xFFC030B0 /* PORTB Port x Multiplexer Control */ |
| 85 | #define PORTC_FER 0xFFC03100 /* PORTC Port x Function Enable */ |
| 86 | #define PORTC_FER_SET 0xFFC03104 /* PORTC Port x Function Enable Set */ |
| 87 | #define PORTC_FER_CLR 0xFFC03108 /* PORTC Port x Function Enable Clear */ |
| 88 | #define PORTC_MUX 0xFFC03130 /* PORTC Port x Multiplexer Control */ |
| 89 | #define PORTD_FER 0xFFC03180 /* PORTD Port x Function Enable */ |
| 90 | #define PORTD_FER_SET 0xFFC03184 /* PORTD Port x Function Enable Set */ |
| 91 | #define PORTD_FER_CLR 0xFFC03188 /* PORTD Port x Function Enable Clear */ |
| 92 | #define PORTD_MUX 0xFFC031B0 /* PORTD Port x Multiplexer Control */ |
| 93 | #define PORTE_FER 0xFFC03200 /* PORTE Port x Function Enable */ |
| 94 | #define PORTE_FER_SET 0xFFC03204 /* PORTE Port x Function Enable Set */ |
| 95 | #define PORTE_FER_CLR 0xFFC03208 /* PORTE Port x Function Enable Clear */ |
| 96 | #define PORTE_MUX 0xFFC03230 /* PORTE Port x Multiplexer Control */ |
| 97 | #define PORTF_FER 0xFFC03280 /* PORTF Port x Function Enable */ |
| 98 | #define PORTF_FER_SET 0xFFC03284 /* PORTF Port x Function Enable Set */ |
| 99 | #define PORTF_FER_CLR 0xFFC03288 /* PORTF Port x Function Enable Clear */ |
| 100 | #define PORTF_MUX 0xFFC032B0 /* PORTF Port x Multiplexer Control */ |
| 101 | #define PORTG_FER 0xFFC03300 /* PORTG Port x Function Enable */ |
| 102 | #define PORTG_FER_SET 0xFFC03304 /* PORTG Port x Function Enable Set */ |
| 103 | #define PORTG_FER_CLR 0xFFC03308 /* PORTG Port x Function Enable Clear */ |
| 104 | #define PORTG_MUX 0xFFC03330 /* PORTG Port x Multiplexer Control */ |
| 105 | |
| 106 | #define SMC_GCTL 0xFFC16004 /* SMC Control Register */ |
| 107 | #define SMC_GSTAT 0xFFC16008 /* SMC Status Register */ |
| 108 | #define SMC_B0CTL 0xFFC1600C /* SMC Bank0 Control Register */ |
| 109 | #define SMC_B0TIM 0xFFC16010 /* SMC Bank0 Timing Register */ |
| 110 | #define SMC_B0ETIM 0xFFC16014 /* SMC Bank0 Extended Timing Register */ |
| 111 | #define SMC_B1CTL 0xFFC1601C /* SMC BANK1 Control Register */ |
| 112 | #define SMC_B1TIM 0xFFC16020 /* SMC BANK1 Timing Register */ |
| 113 | #define SMC_B1ETIM 0xFFC16024 /* SMC BANK1 Extended Timing Register */ |
| 114 | #define SMC_B2CTL 0xFFC1602C /* SMC BANK2 Control Register */ |
| 115 | #define SMC_B2TIM 0xFFC16030 /* SMC BANK2 Timing Register */ |
| 116 | #define SMC_B2ETIM 0xFFC16034 /* SMC BANK2 Extended Timing Register */ |
| 117 | #define SMC_B3CTL 0xFFC1603C /* SMC BANK3 Control Register */ |
| 118 | #define SMC_B3TIM 0xFFC16040 /* SMC BANK3 Timing Register */ |
| 119 | #define SMC_B3ETIM 0xFFC16044 /* SMC BANK3 Extended Timing Register */ |
| 120 | |
| 121 | #define WDOG_CTL 0xFFC17000 /* WDOG0 Control Register */ |
| 122 | #define WDOG_CNT 0xFFC17004 /* WDOG0 Count Register */ |
| 123 | #define WDOG_STAT 0xFFC17008 /* WDOG0 Watchdog Timer Status Register */ |
| 124 | #define WDOG1_CTL 0xFFC17800 /* WDOG1 Control Register */ |
| 125 | #define WDOG1_CNT 0xFFC17804 /* WDOG1 Count Register */ |
| 126 | #define WDOG1_STAT 0xFFC17808 /* WDOG1 Watchdog Timer Status Register */ |
| 127 | |
| Aaron Wu | d9b3bdb | 2014-07-30 14:39:17 +0800 | [diff] [blame] | 128 | #define SDU0_MSG_SET 0xFFC1F084 /* SDU0 Message Set Register */ |
| 129 | |
| Bob Liu | 52a310c | 2012-08-16 11:10:41 +0800 | [diff] [blame] | 130 | #define EMAC0_MACCFG 0xFFC20000 /* EMAC0 MAC Configuration Register */ |
| 131 | #define EMAC1_MACCFG 0xFFC22000 /* EMAC1 MAC Configuration Register */ |
| 132 | |
| Scott Jiang | a17e7a7 | 2013-04-01 15:55:14 -0400 | [diff] [blame] | 133 | #define SPI0_REGBASE 0xFFC40400 /* SPI0 Base Address */ |
| 134 | #define SPI1_REGBASE 0xFFC40500 /* SPI1 Base Address */ |
| 135 | |
| Bob Liu | 52a310c | 2012-08-16 11:10:41 +0800 | [diff] [blame] | 136 | #define DMA10_DSCPTR_NXT 0xFFC05000 /* DMA10 Pointer to Next Initial Desc */ |
| 137 | #define DMA10_ADDRSTART 0xFFC05004 /* DMA10 Start Address of Current Buf */ |
| 138 | #define DMA10_CFG 0xFFC05008 /* DMA10 Configuration Register */ |
| 139 | #define DMA10_XCNT 0xFFC0500C /* DMA10 Inner Loop Count Start Value */ |
| 140 | #define DMA10_XMOD 0xFFC05010 /* DMA10 Inner Loop Address Increment */ |
| 141 | #define DMA10_YCNT 0xFFC05014 /* DMA10 Outer Loop Count Start Value */ |
| 142 | #define DMA10_YMOD 0xFFC05018 /* DMA10 Outer Loop Address Increment */ |
| 143 | #define DMA10_DSCPTR_CUR 0xFFC05024 /* DMA10 Current Descriptor Pointer */ |
| 144 | #define DMA10_DSCPTR_PRV 0xFFC05028 /* DMA10 Previous Initial Desc Pointer */ |
| 145 | #define DMA10_ADDR_CUR 0xFFC0502C /* DMA10 Current Address */ |
| 146 | #define DMA10_STAT 0xFFC05030 /* DMA10 Status Register */ |
| 147 | #define DMA10_XCNT_CUR 0xFFC05034 /* DMA10 Curr Count(1D) or intra-row(2D)*/ |
| 148 | #define DMA10_YCNT_CUR 0xFFC05038 /* DMA10 Curr Row Count (2D only) */ |
| 149 | #define DMA10_BWLCNT 0xFFC05040 /* DMA10 Bandwidth Limit Count */ |
| 150 | #define DMA10_BWLCNT_CUR 0xFFC05044 /* DMA10 Bandwidth Limit Count Current */ |
| 151 | #define DMA10_BWMCNT 0xFFC05048 /* DMA10 Bandwidth Monitor Count */ |
| 152 | #define DMA10_BWMCNT_CUR 0xFFC0504C /* DMA10 Bandwidth Monitor Count Current*/ |
| 153 | |
| 154 | #define MDMA_S0_NEXT_DESC_PTR DMA21_DSCPTR_NXT |
| 155 | #define DMA21_DSCPTR_NXT 0xFFC09000 /* DMA21 Pointer to Next Initial Desc */ |
| 156 | #define MDMA_D0_NEXT_DESC_PTR DMA22_DSCPTR_NXT |
| 157 | #define DMA22_DSCPTR_NXT 0xFFC09080 /* DMA22 Pointer to Next Initial Desc */ |
| 158 | |
| 159 | #define DMC0_ID 0xFFC80000 /* DMC0 Identification Register */ |
| 160 | #define DMC0_CTL 0xFFC80004 /* DMC0 Control Register */ |
| 161 | #define DMC0_STAT 0xFFC80008 /* DMC0 Status Register */ |
| 162 | #define DMC0_EFFCTL 0xFFC8000C /* DMC0 Efficiency Controller */ |
| 163 | #define DMC0_PRIO 0xFFC80010 /* DMC0 Priority ID Register */ |
| 164 | #define DMC0_PRIOMSK 0xFFC80014 /* DMC0 Priority ID Mask */ |
| 165 | #define DMC0_CFG 0xFFC80040 /* DMC0 SDRAM Configuration */ |
| 166 | #define DMC0_TR0 0xFFC80044 /* DMC0 Timing Register 0 */ |
| 167 | #define DMC0_TR1 0xFFC80048 /* DMC0 Timing Register 1 */ |
| 168 | #define DMC0_TR2 0xFFC8004C /* DMC0 Timing Register 2 */ |
| 169 | #define DMC0_MSK 0xFFC8005C /* DMC0 Mode Register Mask */ |
| 170 | #define DMC0_MR 0xFFC80060 /* DMC0 Mode Shadow register */ |
| 171 | #define DMC0_EMR1 0xFFC80064 /* DMC0 EMR1 Shadow Register */ |
| 172 | #define DMC0_EMR2 0xFFC80068 /* DMC0 EMR2 Shadow Register */ |
| 173 | #define DMC0_EMR3 0xFFC8006C /* DMC0 EMR3 Shadow Register */ |
| 174 | #define DMC0_DLLCTL 0xFFC80080 /* DMC0 DLL Control Register */ |
| 175 | #define DMC0_PADCTL 0xFFC800C0 /* DMC0 PAD Control Register 0 */ |
| 176 | |
| 177 | #define SEC0_CCTL0 0xFFCA4400 /* SEC0 Core Control Register n */ |
| 178 | #define SEC0_CCTL1 0xFFCA4440 /* SEC0 Core Control Register n */ |
| 179 | #define SEC0_FCTL 0xFFCA4010 /* SEC0 Fault Control Register */ |
| 180 | #define SEC0_GCTL 0xFFCA4000 /* SEC0 Global Control Register */ |
| 181 | #define SEC0_SCTL0 0xFFCA4800 /* SEC0 IRQ Source Control Register n */ |
| 182 | |
| 183 | #define RCU0_CTL 0xFFCA6000 /* RCU0 Control Register */ |
| 184 | #define RCU0_STAT 0xFFCA6004 /* RCU0 Status Register */ |
| 185 | #define RCU0_CRCTL 0xFFCA6008 /* RCU0 Core Reset Control Register */ |
| 186 | #define RCU0_CRSTAT 0xFFCA600C /* RCU0 Core Reset Status Register */ |
| 187 | #define RCU0_SIDIS 0xFFCA6010 /* RCU0 Sys Interface Disable Register */ |
| 188 | #define RCU0_SISTAT 0xFFCA6014 /* RCU0 Sys Interface Status Register */ |
| 189 | #define RCU0_SVECT_LCK 0xFFCA6018 /* RCU0 SVECT Lock Register */ |
| 190 | #define RCU0_BCODE 0xFFCA601C /* RCU0 Boot Code Register */ |
| 191 | #define RCU0_SVECT0 0xFFCA6020 /* RCU0 Software Vector Register n */ |
| 192 | #define RCU0_SVECT1 0xFFCA6024 /* RCU0 Software Vector Register n */ |
| 193 | |
| 194 | #define CGU_CTL 0xFFCA8000 /* CGU0 Control Register */ |
| 195 | #define CGU_STAT 0xFFCA8004 /* CGU0 Status Register */ |
| 196 | #define CGU_DIV 0xFFCA8008 /* CGU0 Divisor Register */ |
| 197 | #define CGU_CLKOUTSEL 0xFFCA800C /* CGU0 CLKOUT Select Register */ |
| 198 | |
| 199 | #define DPM0_CTL 0xFFCA9000 /* DPM0 Control Register */ |
| 200 | #define DPM0_STAT 0xFFCA9004 /* DPM0 Status Register */ |
| 201 | #define DPM0_CCBF_DIS 0xFFCA9008 /* DPM0 Core Clock Buffer Disable */ |
| 202 | #define DPM0_CCBF_EN 0xFFCA900C /* DPM0 Core Clock Buffer Enable */ |
| 203 | #define DPM0_CCBF_STAT 0xFFCA9010 /* DPM0 Core Clock Buffer Status */ |
| 204 | #define DPM0_CCBF_STAT_STKY 0xFFCA9014 /* DPM0 Core Clock Buffer Stat Sticky */ |
| 205 | #define DPM0_SCBF_DIS 0xFFCA9018 /* DPM0 System Clock Buffer Disable */ |
| 206 | #define DPM0_WAKE_EN 0xFFCA901C /* DPM0 Wakeup Enable Register */ |
| 207 | #define DPM0_WAKE_POL 0xFFCA9020 /* DPM0 Wakeup Polarity Register */ |
| 208 | #define DPM0_WAKE_STAT 0xFFCA9024 /* DPM0 Wakeup Status Register */ |
| 209 | #define DPM0_HIB_DIS 0xFFCA9028 /* DPM0 Hibernate Disable Register */ |
| 210 | #define DPM0_PGCNTR 0xFFCA902C /* DPM0 Power Good Counter Register */ |
| 211 | #define DPM0_RESTORE0 0xFFCA9030 /* DPM0 Restore Register */ |
| 212 | #define DPM0_RESTORE1 0xFFCA9034 /* DPM0 Restore Register */ |
| 213 | #define DPM0_RESTORE2 0xFFCA9038 /* DPM0 Restore Register */ |
| 214 | #define DPM0_RESTORE3 0xFFCA903C /* DPM0 Restore Register */ |
| 215 | #define DPM0_RESTORE4 0xFFCA9040 /* DPM0 Restore Register */ |
| 216 | #define DPM0_RESTORE5 0xFFCA9044 /* DPM0 Restore Register */ |
| 217 | #define DPM0_RESTORE6 0xFFCA9048 /* DPM0 Restore Register */ |
| 218 | #define DPM0_RESTORE7 0xFFCA904C /* DPM0 Restore Register */ |
| 219 | #define DPM0_RESTORE8 0xFFCA9050 /* DPM0 Restore Register */ |
| 220 | #define DPM0_RESTORE9 0xFFCA9054 /* DPM0 Restore Register */ |
| 221 | #define DPM0_RESTORE10 0xFFCA9058 /* DPM0 Restore Register */ |
| 222 | #define DPM0_RESTORE11 0xFFCA905C /* DPM0 Restore Register */ |
| 223 | #define DPM0_RESTORE12 0xFFCA9060 /* DPM0 Restore Register */ |
| 224 | #define DPM0_RESTORE13 0xFFCA9064 /* DPM0 Restore Register */ |
| 225 | #define DPM0_RESTORE14 0xFFCA9068 /* DPM0 Restore Register */ |
| 226 | #define DPM0_RESTORE15 0xFFCA906C /* DPM0 Restore Register */ |
| 227 | |
| 228 | #define USB_FADDR 0xFFCC1000 /* USB Device Address in Peripheral Mode*/ |
| 229 | #define USB_DMA_IRQ 0xFFCC1200 /* USB Interrupt Register */ |
| 230 | #define USB_VBUS_CTL 0xFFCC1380 /* USB VBus Control */ |
| 231 | #define USB_PHY_CTL 0xFFCC1394 /* USB PHY Control */ |
| 232 | #define USB_PLL_OSC 0xFFCC1398 /* USB PLL and Oscillator Control */ |
| 233 | |
| 234 | |
| 235 | #define CHIPID 0xffc00014 |
| 236 | /* CHIPID Masks */ |
| 237 | #define CHIPID_VERSION 0xF0000000 |
| 238 | #define CHIPID_FAMILY 0x0FFFF000 |
| 239 | #define CHIPID_MANUFACTURE 0x00000FFE |
| 240 | |
| 241 | #define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000->0xFF803FFF Data Bank A SRAM */ |
| 242 | #define L1_DATA_A_SRAM_SIZE 0x8000 |
| 243 | #define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE) |
| 244 | #define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000->0xFF903FFF Data Bank B SRAM */ |
| 245 | #define L1_DATA_B_SRAM_SIZE 0x4000 |
| 246 | #define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE) |
| 247 | |
| 248 | #define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000->0xFFA07FFF Inst Bank A SRAM */ |
| 249 | #define L1_INST_SRAM_SIZE 0x8000 |
| 250 | #define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE) |
| 251 | |
| Sonic Zhang | 8a9561c | 2013-02-05 18:57:49 +0800 | [diff] [blame] | 252 | #define COREB_L1_CODE_START 0xFF600000 |
| 253 | |
| Bob Liu | 52a310c | 2012-08-16 11:10:41 +0800 | [diff] [blame] | 254 | #endif /* __BFIN_DEF_ADSP_BF609_proc__ */ |