1. d9b3bdb bfin: add register define required by core B on dual core BF609 processor by Aaron Wu · Wed Jul 30 14:39:17 2014 +0800
  2. a17e7a7 bf609: add SPI register base address by Scott Jiang · Mon Apr 01 15:55:14 2013 -0400
  3. 8a9561c blackfin: run core1 from L1 code sram start address in uboot init code on core 0 by Sonic Zhang · Tue Feb 05 18:57:49 2013 +0800
  4. 52a310c blackfin: bf60x: new processor header files by Bob Liu · Thu Aug 16 11:10:41 2012 +0800