wdenk | 914be13 | 2004-06-08 00:22:43 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2003 |
| 3 | * Texas Instruments. |
| 4 | * Kshitij Gupta <kshitij@ti.com> |
| 5 | * Configuation settings for the TI OMAP Innovator board. |
| 6 | * |
| 7 | * See file CREDITS for list of people who contributed to this |
| 8 | * project. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or |
| 11 | * modify it under the terms of the GNU General Public License as |
| 12 | * published by the Free Software Foundation; either version 2 of |
| 13 | * the License, or (at your option) any later version. |
| 14 | * |
| 15 | * This program is distributed in the hope that it will be useful, |
| 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 18 | * GNU General Public License for more details. |
| 19 | * |
| 20 | * You should have received a copy of the GNU General Public License |
| 21 | * along with this program; if not, write to the Free Software |
| 22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 23 | * MA 02111-1307 USA |
| 24 | */ |
| 25 | |
| 26 | #ifndef __CONFIG_H |
| 27 | #define __CONFIG_H |
| 28 | |
| 29 | /* |
wdenk | 914be13 | 2004-06-08 00:22:43 +0000 | [diff] [blame] | 30 | * High Level Configuration Options |
| 31 | * (easy to change) |
| 32 | */ |
| 33 | #define CONFIG_ARM926EJS 1 /* This is an arm926ejs CPU core */ |
| 34 | #define CONFIG_OMAP 1 /* in a TI OMAP core */ |
| 35 | #define CONFIG_OMAP1610 1 /* 5912 is same as 1610 */ |
| 36 | #define CONFIG_OSK_OMAP5912 1 /* a OSK Board */ |
| 37 | |
Stefan Roese | 0df367f | 2006-05-10 10:55:16 +0200 | [diff] [blame] | 38 | #define CONFIG_DISPLAY_CPUINFO 1 /* display cpu info (and speed) */ |
| 39 | #define CONFIG_DISPLAY_BOARDINFO 1 /* display board info */ |
| 40 | |
wdenk | 914be13 | 2004-06-08 00:22:43 +0000 | [diff] [blame] | 41 | /* input clock of PLL */ |
| 42 | /* the OMAP5912 OSK has 12MHz input clock */ |
| 43 | #define CONFIG_SYS_CLK_FREQ 12000000 |
| 44 | |
wdenk | 914be13 | 2004-06-08 00:22:43 +0000 | [diff] [blame] | 45 | #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ |
| 46 | #define CONFIG_SETUP_MEMORY_TAGS 1 |
Stefan Roese | 0df367f | 2006-05-10 10:55:16 +0200 | [diff] [blame] | 47 | #define CONFIG_INITRD_TAG 1 /* Required for ramdisk support */ |
wdenk | 914be13 | 2004-06-08 00:22:43 +0000 | [diff] [blame] | 48 | |
| 49 | /* |
| 50 | * Size of malloc() pool |
| 51 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 52 | #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128*1024) |
wdenk | 914be13 | 2004-06-08 00:22:43 +0000 | [diff] [blame] | 53 | |
| 54 | /* |
| 55 | * Hardware drivers |
| 56 | */ |
| 57 | /* |
| 58 | */ |
Nishanth Menon | ee1c20f | 2009-10-16 00:06:37 -0500 | [diff] [blame] | 59 | #define CONFIG_LAN91C96 |
wdenk | 914be13 | 2004-06-08 00:22:43 +0000 | [diff] [blame] | 60 | #define CONFIG_LAN91C96_BASE 0x04800300 |
| 61 | #define CONFIG_LAN91C96_EXT_PHY |
| 62 | |
| 63 | /* |
| 64 | * NS16550 Configuration |
| 65 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 66 | #define CONFIG_SYS_NS16550 |
| 67 | #define CONFIG_SYS_NS16550_SERIAL |
| 68 | #define CONFIG_SYS_NS16550_REG_SIZE (-4) |
| 69 | #define CONFIG_SYS_NS16550_CLK (48000000) /* can be 12M/32Khz or 48Mhz */ |
| 70 | #define CONFIG_SYS_NS16550_COM1 0xfffb0000 /* uart1, bluetooth uart |
wdenk | 914be13 | 2004-06-08 00:22:43 +0000 | [diff] [blame] | 71 | on helen */ |
| 72 | |
| 73 | /* |
| 74 | * select serial console configuration |
| 75 | */ |
| 76 | #define CONFIG_SERIAL1 1 /* we use SERIAL 1 on OMAP5912 OSK */ |
| 77 | |
| 78 | /* allow to overwrite serial and ethaddr */ |
| 79 | #define CONFIG_ENV_OVERWRITE |
| 80 | #define CONFIG_CONS_INDEX 1 |
| 81 | #define CONFIG_BAUDRATE 115200 |
Jon Loeliger | 4bd7e1b | 2007-07-04 22:33:13 -0500 | [diff] [blame] | 82 | |
| 83 | /* |
| 84 | * Command line configuration. |
| 85 | */ |
| 86 | #include <config_cmd_default.h> |
| 87 | |
| 88 | #define CONFIG_CMD_DHCP |
| 89 | |
| 90 | |
Jon Loeliger | c6d535a | 2007-07-09 21:57:31 -0500 | [diff] [blame] | 91 | /* |
| 92 | * BOOTP options |
| 93 | */ |
| 94 | #define CONFIG_BOOTP_SUBNETMASK |
| 95 | #define CONFIG_BOOTP_GATEWAY |
| 96 | #define CONFIG_BOOTP_HOSTNAME |
| 97 | #define CONFIG_BOOTP_BOOTPATH |
| 98 | |
wdenk | 914be13 | 2004-06-08 00:22:43 +0000 | [diff] [blame] | 99 | |
wdenk | 914be13 | 2004-06-08 00:22:43 +0000 | [diff] [blame] | 100 | #include <configs/omap1510.h> |
| 101 | |
| 102 | #define CONFIG_BOOTDELAY 3 |
| 103 | #define CONFIG_BOOTARGS "mem=32M console=ttyS0,115200n8 noinitrd \ |
| 104 | root=/dev/nfs rw nfsroot=157.87.82.48:\ |
| 105 | /home/mwd/myfs/target ip=dhcp" |
| 106 | #define CONFIG_NETMASK 255.255.254.0 /* talk on MY local net */ |
| 107 | #define CONFIG_IPADDR 156.117.97.156 /* static IP I currently own */ |
| 108 | #define CONFIG_SERVERIP 156.117.97.139 /* current IP of my dev pc */ |
| 109 | #define CONFIG_BOOTFILE "uImage" /* file to load */ |
| 110 | |
Jon Loeliger | 4bd7e1b | 2007-07-04 22:33:13 -0500 | [diff] [blame] | 111 | #if defined(CONFIG_CMD_KGDB) |
wdenk | 914be13 | 2004-06-08 00:22:43 +0000 | [diff] [blame] | 112 | #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ |
| 113 | #define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ |
| 114 | #endif |
| 115 | |
| 116 | /* |
| 117 | * Miscellaneous configurable options |
| 118 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 119 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
| 120 | #define CONFIG_SYS_PROMPT "OMAP5912 OSK # " /* Monitor Command Prompt */ |
| 121 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
wdenk | 914be13 | 2004-06-08 00:22:43 +0000 | [diff] [blame] | 122 | /* Print Buffer Size */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 123 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) |
| 124 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
| 125 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
wdenk | 914be13 | 2004-06-08 00:22:43 +0000 | [diff] [blame] | 126 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 127 | #define CONFIG_SYS_MEMTEST_START 0x10000000 /* memtest works on */ |
| 128 | #define CONFIG_SYS_MEMTEST_END 0x12000000 /* 32 MB in DRAM */ |
wdenk | 914be13 | 2004-06-08 00:22:43 +0000 | [diff] [blame] | 129 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 130 | #define CONFIG_SYS_LOAD_ADDR 0x10000000 /* default load address */ |
wdenk | 914be13 | 2004-06-08 00:22:43 +0000 | [diff] [blame] | 131 | |
| 132 | /* The 1610 has 6 timers, they can be driven by the RefClk (12Mhz) or by |
| 133 | * DPLL1. This time is further subdivided by a local divisor. |
| 134 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 135 | #define CONFIG_SYS_TIMERBASE 0xFFFEC500 /* use timer 1 */ |
Ladislav Michl | 993e57d | 2009-03-30 18:58:41 +0200 | [diff] [blame] | 136 | #define CONFIG_SYS_PTV 7 /* 2^(PTV+1), divide by 256 */ |
| 137 | #define CONFIG_SYS_HZ ((CONFIG_SYS_CLK_FREQ)/(2 << CONFIG_SYS_PTV)) |
wdenk | 914be13 | 2004-06-08 00:22:43 +0000 | [diff] [blame] | 138 | |
| 139 | /*----------------------------------------------------------------------- |
wdenk | 914be13 | 2004-06-08 00:22:43 +0000 | [diff] [blame] | 140 | * Physical Memory Map |
| 141 | */ |
| 142 | #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ |
Stefan Roese | 0df367f | 2006-05-10 10:55:16 +0200 | [diff] [blame] | 143 | #define PHYS_SDRAM_1 0x10000000 /* SDRAM Bank #1 */ |
wdenk | 914be13 | 2004-06-08 00:22:43 +0000 | [diff] [blame] | 144 | #define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ |
| 145 | |
Stefan Roese | 0df367f | 2006-05-10 10:55:16 +0200 | [diff] [blame] | 146 | #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ |
| 147 | #define PHYS_FLASH_2 0x01000000 /* Flash Bank #2 */ |
| 148 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 149 | #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 |
wdenk | 914be13 | 2004-06-08 00:22:43 +0000 | [diff] [blame] | 150 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 151 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE /* Monitor at beginning of flash */ |
wdenk | 914be13 | 2004-06-08 00:22:43 +0000 | [diff] [blame] | 152 | |
Aneesh V | cdde3e9 | 2011-06-09 08:54:48 -0400 | [diff] [blame] | 153 | #define PHYS_SRAM 0x20000000 |
| 154 | |
wdenk | 914be13 | 2004-06-08 00:22:43 +0000 | [diff] [blame] | 155 | /*----------------------------------------------------------------------- |
Stefan Roese | 0df367f | 2006-05-10 10:55:16 +0200 | [diff] [blame] | 156 | * FLASH driver setup |
wdenk | 914be13 | 2004-06-08 00:22:43 +0000 | [diff] [blame] | 157 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 158 | #define CONFIG_SYS_FLASH_CFI 1 /* Flash memory is CFI compliant */ |
Jean-Christophe PLAGNIOL-VILLARD | 8d94c23 | 2008-08-13 01:40:42 +0200 | [diff] [blame] | 159 | #define CONFIG_FLASH_CFI_DRIVER 1 /* Use drivers/mtd/cfi_flash.c */ |
Stefan Roese | 0df367f | 2006-05-10 10:55:16 +0200 | [diff] [blame] | 160 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 161 | #define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 } |
Stefan Roese | 0df367f | 2006-05-10 10:55:16 +0200 | [diff] [blame] | 162 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 163 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
wdenk | 914be13 | 2004-06-08 00:22:43 +0000 | [diff] [blame] | 164 | #define PHYS_FLASH_SIZE 0x02000000 /* 32MB */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 165 | #define CONFIG_SYS_MAX_FLASH_SECT (259) /* max number of sectors on one chip */ |
Stefan Roese | 0df367f | 2006-05-10 10:55:16 +0200 | [diff] [blame] | 166 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 167 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */ |
| 168 | #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use hardware sector protection */ |
Stefan Roese | 0df367f | 2006-05-10 10:55:16 +0200 | [diff] [blame] | 169 | |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 170 | #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
wdenk | 914be13 | 2004-06-08 00:22:43 +0000 | [diff] [blame] | 171 | |
| 172 | /* timeout values are in ticks */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 173 | #define CONFIG_SYS_FLASH_ERASE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ |
| 174 | #define CONFIG_SYS_FLASH_WRITE_TOUT (20*CONFIG_SYS_HZ) /* Timeout for Flash Write */ |
wdenk | 914be13 | 2004-06-08 00:22:43 +0000 | [diff] [blame] | 175 | |
Stefan Roese | 0df367f | 2006-05-10 10:55:16 +0200 | [diff] [blame] | 176 | /*----------------------------------------------------------------------- |
| 177 | * FLASH and environment organization |
| 178 | */ |
Jean-Christophe PLAGNIOL-VILLARD | 53db4cd | 2008-09-10 22:48:04 +0200 | [diff] [blame] | 179 | #define CONFIG_ENV_IS_IN_FLASH 1 |
Stefan Roese | 0df367f | 2006-05-10 10:55:16 +0200 | [diff] [blame] | 180 | /* addr of environment */ |
Jean-Christophe PLAGNIOL-VILLARD | 0383694 | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 181 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x020000) |
Stefan Roese | 0df367f | 2006-05-10 10:55:16 +0200 | [diff] [blame] | 182 | |
Jean-Christophe PLAGNIOL-VILLARD | 7e1cda6 | 2008-09-10 22:48:06 +0200 | [diff] [blame] | 183 | #define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment Sector */ |
| 184 | #define CONFIG_ENV_OFFSET 0x20000 /* environment starts here */ |
wdenk | 914be13 | 2004-06-08 00:22:43 +0000 | [diff] [blame] | 185 | |
Aneesh V | cdde3e9 | 2011-06-09 08:54:48 -0400 | [diff] [blame] | 186 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
| 187 | #define CONFIG_SYS_INIT_SP_ADDR PHYS_SRAM |
| 188 | |
wdenk | 914be13 | 2004-06-08 00:22:43 +0000 | [diff] [blame] | 189 | #endif /* __CONFIG_H */ |