| Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| Michal Simek | a4ad96e | 2017-11-02 10:54:48 +0100 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2013 - 2017 Xilinx. |
| 4 | * |
| 5 | * Configuration settings for the Xilinx Zynq CSE board. |
| 6 | * See zynq-common.h for Zynq common configs |
| Michal Simek | a4ad96e | 2017-11-02 10:54:48 +0100 | [diff] [blame] | 7 | */ |
| 8 | |
| 9 | #ifndef __CONFIG_ZYNQ_CSE_H |
| 10 | #define __CONFIG_ZYNQ_CSE_H |
| 11 | |
| Michal Simek | a4ad96e | 2017-11-02 10:54:48 +0100 | [diff] [blame] | 12 | #include <configs/zynq-common.h> |
| 13 | |
| 14 | /* Undef unneeded configs */ |
| Tom Rini | c9edebe | 2022-12-04 10:03:50 -0500 | [diff] [blame] | 15 | #undef CFG_EXTRA_ENV_SETTINGS |
| Michal Simek | a4ad96e | 2017-11-02 10:54:48 +0100 | [diff] [blame] | 16 | |
| Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 17 | #undef CFG_SYS_INIT_RAM_ADDR |
| 18 | #undef CFG_SYS_INIT_RAM_SIZE |
| 19 | #define CFG_SYS_INIT_RAM_ADDR 0xFFFDE000 |
| 20 | #define CFG_SYS_INIT_RAM_SIZE 0x1000 |
| Michal Simek | a4ad96e | 2017-11-02 10:54:48 +0100 | [diff] [blame] | 21 | |
| Michal Simek | a4ad96e | 2017-11-02 10:54:48 +0100 | [diff] [blame] | 22 | #endif /* __CONFIG_ZYNQ_CSE_H */ |