blob: 2f5843f9ec31622d8a3d397a3fd8366ee752ae62 [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Michal Simeka4ad96e2017-11-02 10:54:48 +01002/*
3 * (C) Copyright 2013 - 2017 Xilinx.
4 *
5 * Configuration settings for the Xilinx Zynq CSE board.
6 * See zynq-common.h for Zynq common configs
Michal Simeka4ad96e2017-11-02 10:54:48 +01007 */
8
9#ifndef __CONFIG_ZYNQ_CSE_H
10#define __CONFIG_ZYNQ_CSE_H
11
12#define CONFIG_SKIP_LOWLEVEL_INIT
13#define CONFIG_SYS_DCACHE_OFF
14#define CONFIG_SYS_ICACHE_OFF
15
16#include <configs/zynq-common.h>
17
18/* Undef unneeded configs */
19#undef CONFIG_EXTRA_ENV_SETTINGS
20#undef CONFIG_BOARD_LATE_INIT
Michal Simeka4ad96e2017-11-02 10:54:48 +010021#undef CONFIG_ENV_SIZE
Michal Simeka4ad96e2017-11-02 10:54:48 +010022#undef CONFIG_ZLIB
23#undef CONFIG_GZIP
24
Michal Simeka4ad96e2017-11-02 10:54:48 +010025#undef CONFIG_SYS_CBSIZE
26#undef CONFIG_BOOTM_VXWORKS
27#undef CONFIG_BOOTM_LINUX
28
29#define CONFIG_SYS_CBSIZE 1024
30
31#define CONFIG_ENV_SIZE 400
32#undef CONFIG_SYS_INIT_RAM_ADDR
33#undef CONFIG_SYS_INIT_RAM_SIZE
34#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFDE000
35#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
36#undef CONFIG_SPL_BSS_START_ADDR
37#undef CONFIG_SPL_BSS_MAX_SIZE
38#define CONFIG_SPL_BSS_START_ADDR 0x20000
39#define CONFIG_SPL_BSS_MAX_SIZE 0x8000
40
41#undef CONFIG_SYS_MALLOC_LEN
42#define CONFIG_SYS_MALLOC_LEN 0x1000
43
44#define CONFIG_SYS_SDRAM_BASE 0xfffc0000
45#define CONFIG_SYS_SDRAM_SIZE 0x40000
46
47#endif /* __CONFIG_ZYNQ_CSE_H */