Gitiles
Code Review Sign In
git01.mediatek.com / filogic / uboot / 3a27d4b157baec15f6d3a958b38b76fe77fc9ce6 / . / arch / arm / dts / stm32h7-u-boot.dtsi
blob: dea4db396c1b101575cbdb38e26da50dc8112c03 [file] [log] [blame]
Patrice Chotard92a12ff2018-12-06 11:59:42 +0100[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2
3#include <dt-bindings/memory/stm32-sdram.h>
4
Patrice Chotard0dca06e2017-09-13 18:00:11 +0200[diff] [blame]5/{
6 clocks {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]7 bootph-all;
Patrice Chotard0dca06e2017-09-13 18:00:11 +0200[diff] [blame]8 };
9
Patrice Chotard92a12ff2018-12-06 11:59:42 +0100[diff] [blame]10 aliases {
11 gpio0 = &gpioa;
12 gpio1 = &gpiob;
13 gpio2 = &gpioc;
14 gpio3 = &gpiod;
15 gpio4 = &gpioe;
16 gpio5 = &gpiof;
17 gpio6 = &gpiog;
18 gpio7 = &gpioh;
19 gpio8 = &gpioi;
20 gpio9 = &gpioj;
21 gpio10 = &gpiok;
22 mmc0 = &sdmmc1;
dillon min8423bfb2021-04-09 15:28:40 +0800[diff] [blame]23 pinctrl0 = &pinctrl;
Patrice Chotard92a12ff2018-12-06 11:59:42 +0100[diff] [blame]24 };
25
Patrice Chotard0dca06e2017-09-13 18:00:11 +0200[diff] [blame]26 soc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]27 bootph-all;
Patrice Chotard0dca06e2017-09-13 18:00:11 +0200[diff] [blame]28 pin-controller {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]29 bootph-all;
Patrice Chotard0dca06e2017-09-13 18:00:11 +0200[diff] [blame]30 };
Patrice Chotard92a12ff2018-12-06 11:59:42 +0100[diff] [blame]31
32 fmc: fmc@52004000 {
33 compatible = "st,stm32h7-fmc";
34 reg = <0x52004000 0x1000>;
35 clocks = <&rcc FMC_CK>;
36
37 pinctrl-0 = <&fmc_pins>;
38 pinctrl-names = "default";
39 status = "okay";
Patrice Chotard92a12ff2018-12-06 11:59:42 +0100[diff] [blame]40 };
Patrice Chotard0dca06e2017-09-13 18:00:11 +0200[diff] [blame]41 };
42};
43
44&clk_hse {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]45 bootph-all;
Patrice Chotard0dca06e2017-09-13 18:00:11 +0200[diff] [blame]46};
47
Patrice Chotard0dca06e2017-09-13 18:00:11 +0200[diff] [blame]48&clk_i2s {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]49 bootph-all;
Patrice Chotard0dca06e2017-09-13 18:00:11 +0200[diff] [blame]50};
51
Patrice Chotard92a12ff2018-12-06 11:59:42 +0100[diff] [blame]52&clk_lse {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]53 bootph-all;
Patrice Chotard0dca06e2017-09-13 18:00:11 +0200[diff] [blame]54};
55
Patrice Chotard0dca06e2017-09-13 18:00:11 +0200[diff] [blame]56
57&fmc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]58 bootph-all;
Patrice Chotard0dca06e2017-09-13 18:00:11 +0200[diff] [blame]59};
60
Patrice Chotard0dca06e2017-09-13 18:00:11 +0200[diff] [blame]61&gpioa {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]62 bootph-all;
Patrice Chotard044d7af2018-12-06 11:53:39 +0100[diff] [blame]63 compatible = "st,stm32-gpio";
Patrice Chotard0dca06e2017-09-13 18:00:11 +0200[diff] [blame]64};
65
66&gpiob {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]67 bootph-all;
Patrice Chotard044d7af2018-12-06 11:53:39 +0100[diff] [blame]68 compatible = "st,stm32-gpio";
Patrice Chotard0dca06e2017-09-13 18:00:11 +0200[diff] [blame]69};
70
71&gpioc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]72 bootph-all;
Patrice Chotard044d7af2018-12-06 11:53:39 +0100[diff] [blame]73 compatible = "st,stm32-gpio";
Patrice Chotard0dca06e2017-09-13 18:00:11 +0200[diff] [blame]74};
75
76&gpiod {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]77 bootph-all;
Patrice Chotard044d7af2018-12-06 11:53:39 +0100[diff] [blame]78 compatible = "st,stm32-gpio";
Patrice Chotard0dca06e2017-09-13 18:00:11 +0200[diff] [blame]79};
80
81&gpioe {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]82 bootph-all;
Patrice Chotard044d7af2018-12-06 11:53:39 +0100[diff] [blame]83 compatible = "st,stm32-gpio";
Patrice Chotard0dca06e2017-09-13 18:00:11 +0200[diff] [blame]84};
85
86&gpiof {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]87 bootph-all;
Patrice Chotard044d7af2018-12-06 11:53:39 +0100[diff] [blame]88 compatible = "st,stm32-gpio";
Patrice Chotard0dca06e2017-09-13 18:00:11 +0200[diff] [blame]89};
90
91&gpiog {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]92 bootph-all;
Patrice Chotard044d7af2018-12-06 11:53:39 +0100[diff] [blame]93 compatible = "st,stm32-gpio";
Patrice Chotard0dca06e2017-09-13 18:00:11 +0200[diff] [blame]94};
95
96&gpioh {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]97 bootph-all;
Patrice Chotard044d7af2018-12-06 11:53:39 +0100[diff] [blame]98 compatible = "st,stm32-gpio";
Patrice Chotard0dca06e2017-09-13 18:00:11 +0200[diff] [blame]99};
100
101&gpioi {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]102 bootph-all;
Patrice Chotard044d7af2018-12-06 11:53:39 +0100[diff] [blame]103 compatible = "st,stm32-gpio";
Patrice Chotard0dca06e2017-09-13 18:00:11 +0200[diff] [blame]104};
105
106&gpioj {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]107 bootph-all;
Patrice Chotard044d7af2018-12-06 11:53:39 +0100[diff] [blame]108 compatible = "st,stm32-gpio";
Patrice Chotard0dca06e2017-09-13 18:00:11 +0200[diff] [blame]109};
110
111&gpiok {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]112 bootph-all;
Patrice Chotard044d7af2018-12-06 11:53:39 +0100[diff] [blame]113 compatible = "st,stm32-gpio";
Patrice Chotard0dca06e2017-09-13 18:00:11 +0200[diff] [blame]114};
Patrice Chotard92a12ff2018-12-06 11:59:42 +0100[diff] [blame]115
Patrice Chotard92a12ff2018-12-06 11:59:42 +0100[diff] [blame]116&pwrcfg {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]117 bootph-all;
Patrice Chotard92a12ff2018-12-06 11:59:42 +0100[diff] [blame]118};
119
120&rcc {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]121 bootph-all;
Patrice Chotard92a12ff2018-12-06 11:59:42 +0100[diff] [blame]122};
Patrick Delaunayc5c90692019-11-06 16:16:32 +0100[diff] [blame]123
124&sdmmc1 {
125 compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
126};
Patrice Chotard82270812020-11-06 08:11:59 +0100[diff] [blame]127
128&timer5 {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]129 bootph-all;
Patrice Chotard82270812020-11-06 08:11:59 +0100[diff] [blame]130};
dillon min8423bfb2021-04-09 15:28:40 +0800[diff] [blame]131
132&pinctrl {
Simon Glassd3a98cb2023-02-13 08:56:33 -0700[diff] [blame]133 bootph-all;
dillon min8423bfb2021-04-09 15:28:40 +0800[diff] [blame]134};