Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 1 | #include "skeleton.dtsi" |
Clément Léger | e664bce | 2022-03-31 10:55:08 +0200 | [diff] [blame] | 2 | #include <dt-bindings/interrupt-controller/irq.h> |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 3 | |
| 4 | / { |
| 5 | model = "Atmel SAMA5D2 family SoC"; |
| 6 | compatible = "atmel,sama5d2"; |
Clément Léger | 8cde616 | 2022-03-31 10:55:07 +0200 | [diff] [blame] | 7 | interrupt-parent = <&aic>; |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 8 | |
| 9 | aliases { |
| 10 | spi0 = &spi0; |
| 11 | spi1 = &qspi0; |
Eugen Hristev | 235e897 | 2019-08-26 06:47:03 +0000 | [diff] [blame] | 12 | spi2 = &qspi1; |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 13 | i2c0 = &i2c0; |
| 14 | i2c1 = &i2c1; |
| 15 | }; |
| 16 | |
| 17 | clocks { |
| 18 | slow_xtal: slow_xtal { |
| 19 | compatible = "fixed-clock"; |
| 20 | #clock-cells = <0>; |
| 21 | clock-frequency = <0>; |
| 22 | }; |
| 23 | |
| 24 | main_xtal: main_xtal { |
| 25 | compatible = "fixed-clock"; |
| 26 | #clock-cells = <0>; |
| 27 | clock-frequency = <0>; |
| 28 | }; |
| 29 | }; |
| 30 | |
| 31 | ahb { |
| 32 | compatible = "simple-bus"; |
| 33 | #address-cells = <1>; |
| 34 | #size-cells = <1>; |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 35 | bootph-all; |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 36 | |
Eugen Hristev | 21de284 | 2021-08-17 13:29:24 +0300 | [diff] [blame] | 37 | usb1: ohci@400000 { |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 38 | compatible = "atmel,at91rm9200-ohci", "usb-ohci"; |
| 39 | reg = <0x00400000 0x100000>; |
| 40 | clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>; |
| 41 | clock-names = "ohci_clk", "hclk", "uhpck"; |
| 42 | status = "disabled"; |
| 43 | }; |
| 44 | |
Eugen Hristev | 21de284 | 2021-08-17 13:29:24 +0300 | [diff] [blame] | 45 | usb2: ehci@500000 { |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 46 | compatible = "atmel,at91sam9g45-ehci", "usb-ehci"; |
| 47 | reg = <0x00500000 0x100000>; |
| 48 | clocks = <&utmi>, <&uhphs_clk>; |
| 49 | clock-names = "usb_clk", "ehci_clk"; |
| 50 | status = "disabled"; |
| 51 | }; |
| 52 | |
| 53 | sdmmc0: sdio-host@a0000000 { |
| 54 | compatible = "atmel,sama5d2-sdhci"; |
| 55 | reg = <0xa0000000 0x300>; |
| 56 | clocks = <&sdmmc0_hclk>, <&sdmmc0_gclk>, <&main>; |
| 57 | clock-names = "hclock", "multclk", "baseclk"; |
| 58 | status = "disabled"; |
| 59 | }; |
| 60 | |
| 61 | sdmmc1: sdio-host@b0000000 { |
| 62 | compatible = "atmel,sama5d2-sdhci"; |
| 63 | reg = <0xb0000000 0x300>; |
| 64 | clocks = <&sdmmc1_hclk>, <&sdmmc1_gclk>, <&main>; |
| 65 | clock-names = "hclock", "multclk", "baseclk"; |
| 66 | status = "disabled"; |
| 67 | }; |
| 68 | |
| 69 | apb { |
| 70 | compatible = "simple-bus"; |
| 71 | #address-cells = <1>; |
| 72 | #size-cells = <1>; |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 73 | bootph-all; |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 74 | |
Wenyou Yang | 3ec18a6 | 2017-09-18 15:25:57 +0800 | [diff] [blame] | 75 | hlcdc: hlcdc@f0000000 { |
| 76 | compatible = "atmel,at91sam9x5-hlcdc"; |
| 77 | reg = <0xf0000000 0x2000>; |
| 78 | clocks = <&lcdc_clk>; |
| 79 | status = "disabled"; |
| 80 | }; |
| 81 | |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 82 | pmc: pmc@f0014000 { |
| 83 | compatible = "atmel,sama5d2-pmc", "syscon"; |
| 84 | reg = <0xf0014000 0x160>; |
| 85 | #address-cells = <1>; |
| 86 | #size-cells = <0>; |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 87 | bootph-all; |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 88 | |
| 89 | main: mainck { |
| 90 | compatible = "atmel,at91sam9x5-clk-main"; |
| 91 | #clock-cells = <0>; |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 92 | bootph-all; |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 93 | }; |
| 94 | |
Wenyou Yang | 354e10c | 2016-09-18 15:37:47 +0800 | [diff] [blame] | 95 | plla: pllack@0 { |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 96 | compatible = "atmel,sama5d3-clk-pll"; |
| 97 | #clock-cells = <0>; |
| 98 | clocks = <&main>; |
| 99 | reg = <0>; |
| 100 | atmel,clk-input-range = <12000000 12000000>; |
| 101 | #atmel,pll-clk-output-range-cells = <4>; |
| 102 | atmel,pll-clk-output-ranges = <600000000 1200000000 0 0>; |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 103 | bootph-all; |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 104 | }; |
| 105 | |
| 106 | plladiv: plladivck { |
| 107 | compatible = "atmel,at91sam9x5-clk-plldiv"; |
| 108 | #clock-cells = <0>; |
| 109 | clocks = <&plla>; |
| 110 | }; |
| 111 | |
| 112 | audio_pll_frac: audiopll_fracck { |
| 113 | compatible = "atmel,sama5d2-clk-audio-pll-frac"; |
| 114 | #clock-cells = <0>; |
| 115 | clocks = <&main>; |
| 116 | }; |
| 117 | |
| 118 | audio_pll_pad: audiopll_padck { |
| 119 | compatible = "atmel,sama5d2-clk-audio-pll-pad"; |
| 120 | #clock-cells = <0>; |
| 121 | clocks = <&audio_pll_frac>; |
| 122 | }; |
| 123 | |
| 124 | audio_pll_pmc: audiopll_pmcck { |
| 125 | compatible = "atmel,sama5d2-clk-audio-pll-pmc"; |
| 126 | #clock-cells = <0>; |
| 127 | clocks = <&audio_pll_frac>; |
| 128 | }; |
| 129 | |
| 130 | utmi: utmick { |
| 131 | compatible = "atmel,at91sam9x5-clk-utmi"; |
| 132 | #clock-cells = <0>; |
| 133 | clocks = <&main>; |
Wenyou Yang | 75648fb | 2017-09-05 18:30:08 +0800 | [diff] [blame] | 134 | regmap-sfr = <&sfr>; |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 135 | bootph-all; |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 136 | }; |
| 137 | |
| 138 | mck: masterck { |
| 139 | compatible = "atmel,at91sam9x5-clk-master"; |
| 140 | #clock-cells = <0>; |
| 141 | clocks = <&main>, <&plladiv>, <&utmi>; |
| 142 | atmel,clk-output-range = <124000000 166000000>; |
| 143 | atmel,clk-divisors = <1 2 4 3>; |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 144 | bootph-all; |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 145 | }; |
| 146 | |
| 147 | h32ck: h32mxck { |
| 148 | #clock-cells = <0>; |
| 149 | compatible = "atmel,sama5d4-clk-h32mx"; |
| 150 | clocks = <&mck>; |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 151 | bootph-all; |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 152 | }; |
| 153 | |
| 154 | usb: usbck { |
| 155 | compatible = "atmel,at91sam9x5-clk-usb"; |
| 156 | #clock-cells = <0>; |
| 157 | clocks = <&plladiv>, <&utmi>; |
| 158 | }; |
| 159 | |
| 160 | prog: progck { |
| 161 | compatible = "atmel,at91sam9x5-clk-programmable"; |
| 162 | #address-cells = <1>; |
| 163 | #size-cells = <0>; |
| 164 | interrupt-parent = <&pmc>; |
| 165 | clocks = <&main>, <&plladiv>, <&utmi>, <&mck>; |
| 166 | |
Wenyou Yang | 354e10c | 2016-09-18 15:37:47 +0800 | [diff] [blame] | 167 | prog0: prog@0 { |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 168 | #clock-cells = <0>; |
| 169 | reg = <0>; |
| 170 | }; |
| 171 | |
Wenyou Yang | 354e10c | 2016-09-18 15:37:47 +0800 | [diff] [blame] | 172 | prog1: prog@1 { |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 173 | #clock-cells = <0>; |
| 174 | reg = <1>; |
| 175 | }; |
| 176 | |
Wenyou Yang | 354e10c | 2016-09-18 15:37:47 +0800 | [diff] [blame] | 177 | prog2: prog@2 { |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 178 | #clock-cells = <0>; |
| 179 | reg = <2>; |
| 180 | }; |
| 181 | }; |
| 182 | |
| 183 | systemck { |
| 184 | compatible = "atmel,at91rm9200-clk-system"; |
| 185 | #address-cells = <1>; |
| 186 | #size-cells = <0>; |
| 187 | |
Wenyou Yang | 354e10c | 2016-09-18 15:37:47 +0800 | [diff] [blame] | 188 | ddrck: ddrck@2 { |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 189 | #clock-cells = <0>; |
| 190 | reg = <2>; |
| 191 | clocks = <&mck>; |
| 192 | }; |
| 193 | |
Wenyou Yang | 354e10c | 2016-09-18 15:37:47 +0800 | [diff] [blame] | 194 | lcdck: lcdck@3 { |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 195 | #clock-cells = <0>; |
| 196 | reg = <3>; |
| 197 | clocks = <&mck>; |
| 198 | }; |
| 199 | |
Wenyou Yang | 354e10c | 2016-09-18 15:37:47 +0800 | [diff] [blame] | 200 | uhpck: uhpck@6 { |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 201 | #clock-cells = <0>; |
| 202 | reg = <6>; |
| 203 | clocks = <&usb>; |
| 204 | }; |
| 205 | |
Wenyou Yang | 354e10c | 2016-09-18 15:37:47 +0800 | [diff] [blame] | 206 | udpck: udpck@7 { |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 207 | #clock-cells = <0>; |
| 208 | reg = <7>; |
| 209 | clocks = <&usb>; |
| 210 | }; |
| 211 | |
Wenyou Yang | 354e10c | 2016-09-18 15:37:47 +0800 | [diff] [blame] | 212 | pck0: pck0@8 { |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 213 | #clock-cells = <0>; |
| 214 | reg = <8>; |
| 215 | clocks = <&prog0>; |
| 216 | }; |
| 217 | |
Wenyou Yang | 354e10c | 2016-09-18 15:37:47 +0800 | [diff] [blame] | 218 | pck1: pck1@9 { |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 219 | #clock-cells = <0>; |
| 220 | reg = <9>; |
| 221 | clocks = <&prog1>; |
| 222 | }; |
| 223 | |
Wenyou Yang | 354e10c | 2016-09-18 15:37:47 +0800 | [diff] [blame] | 224 | pck2: pck2@10 { |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 225 | #clock-cells = <0>; |
| 226 | reg = <10>; |
| 227 | clocks = <&prog2>; |
| 228 | }; |
| 229 | |
Wenyou Yang | 354e10c | 2016-09-18 15:37:47 +0800 | [diff] [blame] | 230 | iscck: iscck@18 { |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 231 | #clock-cells = <0>; |
| 232 | reg = <18>; |
| 233 | clocks = <&mck>; |
| 234 | }; |
| 235 | }; |
| 236 | |
| 237 | periph32ck { |
| 238 | compatible = "atmel,at91sam9x5-clk-peripheral"; |
| 239 | #address-cells = <1>; |
| 240 | #size-cells = <0>; |
| 241 | clocks = <&h32ck>; |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 242 | bootph-all; |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 243 | |
Wenyou Yang | 354e10c | 2016-09-18 15:37:47 +0800 | [diff] [blame] | 244 | macb0_clk: macb0_clk@5 { |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 245 | #clock-cells = <0>; |
| 246 | reg = <5>; |
| 247 | atmel,clk-output-range = <0 83000000>; |
| 248 | }; |
| 249 | |
Wenyou Yang | 354e10c | 2016-09-18 15:37:47 +0800 | [diff] [blame] | 250 | tdes_clk: tdes_clk@11 { |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 251 | #clock-cells = <0>; |
| 252 | reg = <11>; |
| 253 | atmel,clk-output-range = <0 83000000>; |
| 254 | }; |
| 255 | |
Wenyou Yang | 354e10c | 2016-09-18 15:37:47 +0800 | [diff] [blame] | 256 | matrix1_clk: matrix1_clk@14 { |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 257 | #clock-cells = <0>; |
| 258 | reg = <14>; |
| 259 | }; |
| 260 | |
Wenyou Yang | 354e10c | 2016-09-18 15:37:47 +0800 | [diff] [blame] | 261 | hsmc_clk: hsmc_clk@17 { |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 262 | #clock-cells = <0>; |
| 263 | reg = <17>; |
| 264 | }; |
| 265 | |
Wenyou Yang | 354e10c | 2016-09-18 15:37:47 +0800 | [diff] [blame] | 266 | pioA_clk: pioA_clk@18 { |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 267 | #clock-cells = <0>; |
| 268 | reg = <18>; |
| 269 | atmel,clk-output-range = <0 83000000>; |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 270 | bootph-all; |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 271 | }; |
| 272 | |
Wenyou Yang | 354e10c | 2016-09-18 15:37:47 +0800 | [diff] [blame] | 273 | flx0_clk: flx0_clk@19 { |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 274 | #clock-cells = <0>; |
| 275 | reg = <19>; |
| 276 | atmel,clk-output-range = <0 83000000>; |
| 277 | }; |
| 278 | |
Wenyou Yang | 354e10c | 2016-09-18 15:37:47 +0800 | [diff] [blame] | 279 | flx1_clk: flx1_clk@20 { |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 280 | #clock-cells = <0>; |
| 281 | reg = <20>; |
| 282 | atmel,clk-output-range = <0 83000000>; |
| 283 | }; |
| 284 | |
Wenyou Yang | 354e10c | 2016-09-18 15:37:47 +0800 | [diff] [blame] | 285 | flx2_clk: flx2_clk@21 { |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 286 | #clock-cells = <0>; |
| 287 | reg = <21>; |
| 288 | atmel,clk-output-range = <0 83000000>; |
| 289 | }; |
| 290 | |
Wenyou Yang | 354e10c | 2016-09-18 15:37:47 +0800 | [diff] [blame] | 291 | flx3_clk: flx3_clk@22 { |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 292 | #clock-cells = <0>; |
| 293 | reg = <22>; |
| 294 | atmel,clk-output-range = <0 83000000>; |
| 295 | }; |
| 296 | |
Wenyou Yang | 354e10c | 2016-09-18 15:37:47 +0800 | [diff] [blame] | 297 | flx4_clk: flx4_clk@23 { |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 298 | #clock-cells = <0>; |
| 299 | reg = <23>; |
| 300 | atmel,clk-output-range = <0 83000000>; |
| 301 | }; |
| 302 | |
Wenyou Yang | 354e10c | 2016-09-18 15:37:47 +0800 | [diff] [blame] | 303 | uart0_clk: uart0_clk@24 { |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 304 | #clock-cells = <0>; |
| 305 | reg = <24>; |
| 306 | atmel,clk-output-range = <0 83000000>; |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 307 | bootph-all; |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 308 | }; |
| 309 | |
Wenyou Yang | 354e10c | 2016-09-18 15:37:47 +0800 | [diff] [blame] | 310 | uart1_clk: uart1_clk@25 { |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 311 | #clock-cells = <0>; |
| 312 | reg = <25>; |
| 313 | atmel,clk-output-range = <0 83000000>; |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 314 | bootph-all; |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 315 | }; |
| 316 | |
Wenyou Yang | 354e10c | 2016-09-18 15:37:47 +0800 | [diff] [blame] | 317 | uart2_clk: uart2_clk@26 { |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 318 | #clock-cells = <0>; |
| 319 | reg = <26>; |
| 320 | atmel,clk-output-range = <0 83000000>; |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 321 | bootph-all; |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 322 | }; |
| 323 | |
Wenyou Yang | 354e10c | 2016-09-18 15:37:47 +0800 | [diff] [blame] | 324 | uart3_clk: uart3_clk@27 { |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 325 | #clock-cells = <0>; |
| 326 | reg = <27>; |
| 327 | atmel,clk-output-range = <0 83000000>; |
| 328 | }; |
| 329 | |
Wenyou Yang | 354e10c | 2016-09-18 15:37:47 +0800 | [diff] [blame] | 330 | uart4_clk: uart4_clk@28 { |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 331 | #clock-cells = <0>; |
| 332 | reg = <28>; |
| 333 | atmel,clk-output-range = <0 83000000>; |
| 334 | }; |
| 335 | |
Wenyou Yang | 354e10c | 2016-09-18 15:37:47 +0800 | [diff] [blame] | 336 | twi0_clk: twi0_clk@29 { |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 337 | reg = <29>; |
| 338 | #clock-cells = <0>; |
| 339 | atmel,clk-output-range = <0 83000000>; |
| 340 | }; |
| 341 | |
Wenyou Yang | 354e10c | 2016-09-18 15:37:47 +0800 | [diff] [blame] | 342 | twi1_clk: twi1_clk@30 { |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 343 | #clock-cells = <0>; |
| 344 | reg = <30>; |
| 345 | atmel,clk-output-range = <0 83000000>; |
| 346 | }; |
| 347 | |
Wenyou Yang | 354e10c | 2016-09-18 15:37:47 +0800 | [diff] [blame] | 348 | spi0_clk: spi0_clk@33 { |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 349 | #clock-cells = <0>; |
| 350 | reg = <33>; |
| 351 | atmel,clk-output-range = <0 83000000>; |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 352 | bootph-all; |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 353 | }; |
| 354 | |
Wenyou Yang | 354e10c | 2016-09-18 15:37:47 +0800 | [diff] [blame] | 355 | spi1_clk: spi1_clk@34 { |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 356 | #clock-cells = <0>; |
| 357 | reg = <34>; |
| 358 | atmel,clk-output-range = <0 83000000>; |
| 359 | }; |
| 360 | |
Wenyou Yang | 354e10c | 2016-09-18 15:37:47 +0800 | [diff] [blame] | 361 | tcb0_clk: tcb0_clk@35 { |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 362 | #clock-cells = <0>; |
| 363 | reg = <35>; |
| 364 | atmel,clk-output-range = <0 83000000>; |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 365 | bootph-all; |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 366 | }; |
| 367 | |
Wenyou Yang | 354e10c | 2016-09-18 15:37:47 +0800 | [diff] [blame] | 368 | tcb1_clk: tcb1_clk@36 { |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 369 | #clock-cells = <0>; |
| 370 | reg = <36>; |
| 371 | atmel,clk-output-range = <0 83000000>; |
| 372 | }; |
| 373 | |
Wenyou Yang | 354e10c | 2016-09-18 15:37:47 +0800 | [diff] [blame] | 374 | pwm_clk: pwm_clk@38 { |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 375 | #clock-cells = <0>; |
| 376 | reg = <38>; |
| 377 | atmel,clk-output-range = <0 83000000>; |
| 378 | }; |
| 379 | |
Wenyou Yang | 354e10c | 2016-09-18 15:37:47 +0800 | [diff] [blame] | 380 | adc_clk: adc_clk@40 { |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 381 | #clock-cells = <0>; |
| 382 | reg = <40>; |
| 383 | atmel,clk-output-range = <0 83000000>; |
| 384 | }; |
| 385 | |
Wenyou Yang | 354e10c | 2016-09-18 15:37:47 +0800 | [diff] [blame] | 386 | uhphs_clk: uhphs_clk@41 { |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 387 | #clock-cells = <0>; |
| 388 | reg = <41>; |
| 389 | atmel,clk-output-range = <0 83000000>; |
| 390 | }; |
| 391 | |
Wenyou Yang | 354e10c | 2016-09-18 15:37:47 +0800 | [diff] [blame] | 392 | udphs_clk: udphs_clk@42 { |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 393 | #clock-cells = <0>; |
| 394 | reg = <42>; |
| 395 | atmel,clk-output-range = <0 83000000>; |
| 396 | }; |
| 397 | |
Wenyou Yang | 354e10c | 2016-09-18 15:37:47 +0800 | [diff] [blame] | 398 | ssc0_clk: ssc0_clk@43 { |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 399 | #clock-cells = <0>; |
| 400 | reg = <43>; |
| 401 | atmel,clk-output-range = <0 83000000>; |
| 402 | }; |
| 403 | |
Wenyou Yang | 354e10c | 2016-09-18 15:37:47 +0800 | [diff] [blame] | 404 | ssc1_clk: ssc1_clk@44 { |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 405 | #clock-cells = <0>; |
| 406 | reg = <44>; |
| 407 | atmel,clk-output-range = <0 83000000>; |
| 408 | }; |
| 409 | |
Wenyou Yang | 354e10c | 2016-09-18 15:37:47 +0800 | [diff] [blame] | 410 | trng_clk: trng_clk@47 { |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 411 | #clock-cells = <0>; |
| 412 | reg = <47>; |
| 413 | atmel,clk-output-range = <0 83000000>; |
| 414 | }; |
| 415 | |
Wenyou Yang | 354e10c | 2016-09-18 15:37:47 +0800 | [diff] [blame] | 416 | pdmic_clk: pdmic_clk@48 { |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 417 | #clock-cells = <0>; |
| 418 | reg = <48>; |
| 419 | atmel,clk-output-range = <0 83000000>; |
| 420 | }; |
| 421 | |
Wenyou Yang | 354e10c | 2016-09-18 15:37:47 +0800 | [diff] [blame] | 422 | i2s0_clk: i2s0_clk@54 { |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 423 | #clock-cells = <0>; |
| 424 | reg = <54>; |
| 425 | atmel,clk-output-range = <0 83000000>; |
| 426 | }; |
| 427 | |
Wenyou Yang | 354e10c | 2016-09-18 15:37:47 +0800 | [diff] [blame] | 428 | i2s1_clk: i2s1_clk@55 { |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 429 | #clock-cells = <0>; |
| 430 | reg = <55>; |
| 431 | atmel,clk-output-range = <0 83000000>; |
| 432 | }; |
| 433 | |
Wenyou Yang | 354e10c | 2016-09-18 15:37:47 +0800 | [diff] [blame] | 434 | can0_clk: can0_clk@56 { |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 435 | #clock-cells = <0>; |
| 436 | reg = <56>; |
| 437 | atmel,clk-output-range = <0 83000000>; |
| 438 | }; |
| 439 | |
Wenyou Yang | 354e10c | 2016-09-18 15:37:47 +0800 | [diff] [blame] | 440 | can1_clk: can1_clk@57 { |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 441 | #clock-cells = <0>; |
| 442 | reg = <57>; |
| 443 | atmel,clk-output-range = <0 83000000>; |
| 444 | }; |
| 445 | |
Wenyou Yang | 354e10c | 2016-09-18 15:37:47 +0800 | [diff] [blame] | 446 | classd_clk: classd_clk@59 { |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 447 | #clock-cells = <0>; |
| 448 | reg = <59>; |
| 449 | atmel,clk-output-range = <0 83000000>; |
| 450 | }; |
| 451 | }; |
| 452 | |
| 453 | periph64ck { |
| 454 | compatible = "atmel,at91sam9x5-clk-peripheral"; |
| 455 | #address-cells = <1>; |
| 456 | #size-cells = <0>; |
| 457 | clocks = <&mck>; |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 458 | bootph-all; |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 459 | |
Wenyou Yang | 354e10c | 2016-09-18 15:37:47 +0800 | [diff] [blame] | 460 | dma0_clk: dma0_clk@6 { |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 461 | #clock-cells = <0>; |
| 462 | reg = <6>; |
| 463 | }; |
| 464 | |
Wenyou Yang | 354e10c | 2016-09-18 15:37:47 +0800 | [diff] [blame] | 465 | dma1_clk: dma1_clk@7 { |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 466 | #clock-cells = <0>; |
| 467 | reg = <7>; |
| 468 | }; |
| 469 | |
Wenyou Yang | 354e10c | 2016-09-18 15:37:47 +0800 | [diff] [blame] | 470 | aes_clk: aes_clk@9 { |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 471 | #clock-cells = <0>; |
| 472 | reg = <9>; |
| 473 | }; |
| 474 | |
Wenyou Yang | 354e10c | 2016-09-18 15:37:47 +0800 | [diff] [blame] | 475 | aesb_clk: aesb_clk@10 { |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 476 | #clock-cells = <0>; |
| 477 | reg = <10>; |
| 478 | }; |
| 479 | |
Wenyou Yang | 354e10c | 2016-09-18 15:37:47 +0800 | [diff] [blame] | 480 | sha_clk: sha_clk@12 { |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 481 | #clock-cells = <0>; |
| 482 | reg = <12>; |
| 483 | }; |
| 484 | |
Wenyou Yang | 354e10c | 2016-09-18 15:37:47 +0800 | [diff] [blame] | 485 | mpddr_clk: mpddr_clk@13 { |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 486 | #clock-cells = <0>; |
| 487 | reg = <13>; |
| 488 | }; |
| 489 | |
Wenyou Yang | 354e10c | 2016-09-18 15:37:47 +0800 | [diff] [blame] | 490 | matrix0_clk: matrix0_clk@15 { |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 491 | #clock-cells = <0>; |
| 492 | reg = <15>; |
| 493 | }; |
| 494 | |
Wenyou Yang | 354e10c | 2016-09-18 15:37:47 +0800 | [diff] [blame] | 495 | sdmmc0_hclk: sdmmc0_hclk@31 { |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 496 | #clock-cells = <0>; |
| 497 | reg = <31>; |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 498 | bootph-all; |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 499 | }; |
| 500 | |
Wenyou Yang | 354e10c | 2016-09-18 15:37:47 +0800 | [diff] [blame] | 501 | sdmmc1_hclk: sdmmc1_hclk@32 { |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 502 | #clock-cells = <0>; |
| 503 | reg = <32>; |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 504 | bootph-all; |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 505 | }; |
| 506 | |
Wenyou Yang | 354e10c | 2016-09-18 15:37:47 +0800 | [diff] [blame] | 507 | lcdc_clk: lcdc_clk@45 { |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 508 | #clock-cells = <0>; |
| 509 | reg = <45>; |
| 510 | }; |
| 511 | |
Wenyou Yang | 354e10c | 2016-09-18 15:37:47 +0800 | [diff] [blame] | 512 | isc_clk: isc_clk@46 { |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 513 | #clock-cells = <0>; |
| 514 | reg = <46>; |
| 515 | }; |
| 516 | |
Wenyou Yang | 354e10c | 2016-09-18 15:37:47 +0800 | [diff] [blame] | 517 | qspi0_clk: qspi0_clk@52 { |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 518 | #clock-cells = <0>; |
| 519 | reg = <52>; |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 520 | bootph-all; |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 521 | }; |
| 522 | |
Wenyou Yang | 354e10c | 2016-09-18 15:37:47 +0800 | [diff] [blame] | 523 | qspi1_clk: qspi1_clk@53 { |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 524 | #clock-cells = <0>; |
| 525 | reg = <53>; |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 526 | bootph-all; |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 527 | }; |
| 528 | }; |
| 529 | |
| 530 | gck { |
| 531 | compatible = "atmel,sama5d2-clk-generated"; |
| 532 | #address-cells = <1>; |
| 533 | #size-cells = <0>; |
| 534 | interrupt-parent = <&pmc>; |
| 535 | clocks = <&main>, <&plla>, <&utmi>, <&mck>; |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 536 | bootph-all; |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 537 | |
Wenyou Yang | 354e10c | 2016-09-18 15:37:47 +0800 | [diff] [blame] | 538 | sdmmc0_gclk: sdmmc0_gclk@31 { |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 539 | #clock-cells = <0>; |
| 540 | reg = <31>; |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 541 | bootph-all; |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 542 | }; |
| 543 | |
Wenyou Yang | 354e10c | 2016-09-18 15:37:47 +0800 | [diff] [blame] | 544 | sdmmc1_gclk: sdmmc1_gclk@32 { |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 545 | #clock-cells = <0>; |
| 546 | reg = <32>; |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 547 | bootph-all; |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 548 | }; |
| 549 | |
Wenyou Yang | 354e10c | 2016-09-18 15:37:47 +0800 | [diff] [blame] | 550 | tcb0_gclk: tcb0_gclk@35 { |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 551 | #clock-cells = <0>; |
| 552 | reg = <35>; |
| 553 | atmel,clk-output-range = <0 83000000>; |
| 554 | }; |
| 555 | |
Wenyou Yang | 354e10c | 2016-09-18 15:37:47 +0800 | [diff] [blame] | 556 | tcb1_gclk: tcb1_gclk@36 { |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 557 | #clock-cells = <0>; |
| 558 | reg = <36>; |
| 559 | atmel,clk-output-range = <0 83000000>; |
| 560 | }; |
| 561 | |
Wenyou Yang | 354e10c | 2016-09-18 15:37:47 +0800 | [diff] [blame] | 562 | pwm_gclk: pwm_gclk@38 { |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 563 | #clock-cells = <0>; |
| 564 | reg = <38>; |
| 565 | atmel,clk-output-range = <0 83000000>; |
| 566 | }; |
| 567 | |
Wenyou Yang | 354e10c | 2016-09-18 15:37:47 +0800 | [diff] [blame] | 568 | pdmic_gclk: pdmic_gclk@48 { |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 569 | #clock-cells = <0>; |
| 570 | reg = <48>; |
| 571 | }; |
| 572 | |
Wenyou Yang | 354e10c | 2016-09-18 15:37:47 +0800 | [diff] [blame] | 573 | i2s0_gclk: i2s0_gclk@54 { |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 574 | #clock-cells = <0>; |
| 575 | reg = <54>; |
| 576 | }; |
| 577 | |
Wenyou Yang | 354e10c | 2016-09-18 15:37:47 +0800 | [diff] [blame] | 578 | i2s1_gclk: i2s1_gclk@55 { |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 579 | #clock-cells = <0>; |
| 580 | reg = <55>; |
| 581 | }; |
| 582 | |
Wenyou Yang | 354e10c | 2016-09-18 15:37:47 +0800 | [diff] [blame] | 583 | can0_gclk: can0_gclk@56 { |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 584 | #clock-cells = <0>; |
| 585 | reg = <56>; |
| 586 | atmel,clk-output-range = <0 80000000>; |
| 587 | }; |
| 588 | |
Wenyou Yang | 354e10c | 2016-09-18 15:37:47 +0800 | [diff] [blame] | 589 | can1_gclk: can1_gclk@57 { |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 590 | #clock-cells = <0>; |
| 591 | reg = <57>; |
| 592 | atmel,clk-output-range = <0 80000000>; |
| 593 | }; |
| 594 | |
Wenyou Yang | 354e10c | 2016-09-18 15:37:47 +0800 | [diff] [blame] | 595 | classd_gclk: classd_gclk@59 { |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 596 | #clock-cells = <0>; |
| 597 | reg = <59>; |
| 598 | atmel,clk-output-range = <0 100000000>; |
| 599 | }; |
| 600 | }; |
| 601 | }; |
| 602 | |
| 603 | qspi0: spi@f0020000 { |
| 604 | compatible = "atmel,sama5d2-qspi"; |
| 605 | reg = <0xf0020000 0x100>, <0xd0000000 0x08000000>; |
| 606 | reg-names = "qspi_base", "qspi_mmap"; |
| 607 | #address-cells = <1>; |
| 608 | #size-cells = <0>; |
| 609 | clocks = <&qspi0_clk>; |
| 610 | status = "disabled"; |
| 611 | }; |
| 612 | |
Wenyou Yang | eebb073 | 2017-09-13 14:58:54 +0800 | [diff] [blame] | 613 | qspi1: spi@f0024000 { |
| 614 | compatible = "atmel,sama5d2-qspi"; |
| 615 | reg = <0xf0024000 0x100>, <0xd8000000 0x08000000>; |
| 616 | reg-names = "qspi_base", "qspi_mmap"; |
| 617 | #address-cells = <1>; |
| 618 | #size-cells = <0>; |
| 619 | clocks = <&qspi1_clk>; |
| 620 | status = "disabled"; |
| 621 | }; |
| 622 | |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 623 | spi0: spi@f8000000 { |
| 624 | compatible = "atmel,at91rm9200-spi"; |
| 625 | reg = <0xf8000000 0x100>; |
| 626 | clocks = <&spi0_clk>; |
| 627 | clock-names = "spi_clk"; |
| 628 | #address-cells = <1>; |
| 629 | #size-cells = <0>; |
| 630 | status = "disabled"; |
| 631 | }; |
| 632 | |
| 633 | macb0: ethernet@f8008000 { |
| 634 | compatible = "cdns,macb"; |
| 635 | reg = <0xf8008000 0x1000>; |
| 636 | #address-cells = <1>; |
| 637 | #size-cells = <0>; |
| 638 | clocks = <&macb0_clk>, <&macb0_clk>; |
| 639 | clock-names = "hclk", "pclk"; |
| 640 | status = "disabled"; |
| 641 | }; |
| 642 | |
Clément Léger | e664bce | 2022-03-31 10:55:08 +0200 | [diff] [blame] | 643 | tcb0: timer@f800c000 { |
| 644 | compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon"; |
| 645 | reg = <0xf800c000 0x100>; |
| 646 | interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>; |
| 647 | clocks = <&tcb0_clk>, <&tcb0_gclk>, <&clk32k>; |
| 648 | clock-names = "t0_clk", "gclk", "slow_clk"; |
| 649 | #address-cells = <1>; |
| 650 | #size-cells = <0>; |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 651 | bootph-all; |
Clément Léger | e664bce | 2022-03-31 10:55:08 +0200 | [diff] [blame] | 652 | |
| 653 | timer0: timer@0 { |
| 654 | compatible = "atmel,tcb-timer"; |
| 655 | reg = <0>, <1>; |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 656 | bootph-all; |
Clément Léger | e664bce | 2022-03-31 10:55:08 +0200 | [diff] [blame] | 657 | }; |
| 658 | }; |
| 659 | |
Ludovic Desroches | 1240d88 | 2017-11-17 14:57:12 +0800 | [diff] [blame] | 660 | uart0: serial@f801c000 { |
| 661 | compatible = "atmel,at91sam9260-usart"; |
| 662 | reg = <0xf801c000 0x100>; |
| 663 | clocks = <&uart0_clk>; |
| 664 | clock-names = "usart"; |
| 665 | status = "disabled"; |
| 666 | }; |
| 667 | |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 668 | uart1: serial@f8020000 { |
| 669 | compatible = "atmel,at91sam9260-usart"; |
| 670 | reg = <0xf8020000 0x100>; |
Wenyou Yang | 4e3524d | 2017-03-23 14:26:22 +0800 | [diff] [blame] | 671 | clocks = <&uart1_clk>; |
| 672 | clock-names = "usart"; |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 673 | status = "disabled"; |
| 674 | }; |
| 675 | |
Ludovic Desroches | 1240d88 | 2017-11-17 14:57:12 +0800 | [diff] [blame] | 676 | uart2: serial@f8024000 { |
| 677 | compatible = "atmel,at91sam9260-usart"; |
| 678 | reg = <0xf8024000 0x100>; |
| 679 | clocks = <&uart2_clk>; |
| 680 | clock-names = "usart"; |
| 681 | status = "disabled"; |
| 682 | }; |
| 683 | |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 684 | i2c0: i2c@f8028000 { |
| 685 | compatible = "atmel,sama5d2-i2c"; |
| 686 | reg = <0xf8028000 0x100>; |
| 687 | #address-cells = <1>; |
| 688 | #size-cells = <0>; |
| 689 | clocks = <&twi0_clk>; |
| 690 | status = "disabled"; |
| 691 | }; |
| 692 | |
Dan Sneddon | f09aa3f | 2021-09-20 16:28:46 -0700 | [diff] [blame] | 693 | pwm0: pwm@f802c000 { |
| 694 | compatible = "atmel,sama5d2-pwm"; |
| 695 | reg = <0xf802c000 0x4000>; |
| 696 | clocks = <&pwm_clk>; |
| 697 | #pwm-cells = <3>; |
| 698 | status = "disabled"; |
| 699 | }; |
| 700 | |
Wenyou.Yang@microchip.com | 272167d | 2017-08-15 17:40:27 +0800 | [diff] [blame] | 701 | rstc@f8048000 { |
| 702 | compatible = "atmel,sama5d3-rstc"; |
| 703 | reg = <0xf8048000 0x10>; |
| 704 | clocks = <&clk32k>; |
| 705 | }; |
| 706 | |
| 707 | shdwc@f8048010 { |
| 708 | compatible = "atmel,sama5d2-shdwc"; |
| 709 | reg = <0xf8048010 0x10>; |
| 710 | clocks = <&clk32k>; |
| 711 | #address-cells = <1>; |
| 712 | #size-cells = <0>; |
| 713 | atmel,wakeup-rtc-timer; |
| 714 | }; |
| 715 | |
| 716 | pit: timer@f8048030 { |
| 717 | compatible = "atmel,at91sam9260-pit"; |
| 718 | reg = <0xf8048030 0x10>; |
| 719 | clocks = <&h32ck>; |
| 720 | }; |
| 721 | |
| 722 | watchdog@f8048040 { |
| 723 | compatible = "atmel,sama5d4-wdt"; |
| 724 | reg = <0xf8048040 0x10>; |
| 725 | clocks = <&clk32k>; |
| 726 | status = "disabled"; |
| 727 | }; |
| 728 | |
Wenyou Yang | 75648fb | 2017-09-05 18:30:08 +0800 | [diff] [blame] | 729 | sfr: sfr@f8030000 { |
| 730 | compatible = "atmel,sama5d2-sfr", "syscon"; |
| 731 | reg = <0xf8030000 0x98>; |
| 732 | }; |
| 733 | |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 734 | sckc@f8048050 { |
| 735 | compatible = "atmel,at91sam9x5-sckc"; |
| 736 | reg = <0xf8048050 0x4>; |
| 737 | |
| 738 | slow_rc_osc: slow_rc_osc { |
| 739 | compatible = "atmel,at91sam9x5-clk-slow-rc-osc"; |
| 740 | #clock-cells = <0>; |
| 741 | clock-frequency = <32768>; |
| 742 | clock-accuracy = <250000000>; |
| 743 | atmel,startup-time-usec = <75>; |
| 744 | }; |
| 745 | |
| 746 | slow_osc: slow_osc { |
| 747 | compatible = "atmel,at91sam9x5-clk-slow-osc"; |
| 748 | #clock-cells = <0>; |
| 749 | clocks = <&slow_xtal>; |
| 750 | atmel,startup-time-usec = <1200000>; |
| 751 | }; |
| 752 | |
| 753 | clk32k: slowck { |
| 754 | compatible = "atmel,at91sam9x5-clk-slow"; |
| 755 | #clock-cells = <0>; |
| 756 | clocks = <&slow_rc_osc &slow_osc>; |
| 757 | }; |
| 758 | }; |
| 759 | |
| 760 | spi1: spi@fc000000 { |
| 761 | compatible = "atmel,at91rm9200-spi"; |
| 762 | reg = <0xfc000000 0x100>; |
| 763 | #address-cells = <1>; |
| 764 | #size-cells = <0>; |
| 765 | status = "disabled"; |
| 766 | }; |
| 767 | |
Wenyou Yang | eebb073 | 2017-09-13 14:58:54 +0800 | [diff] [blame] | 768 | uart3: serial@fc008000 { |
| 769 | compatible = "atmel,at91sam9260-usart"; |
| 770 | reg = <0xfc008000 0x100>; |
| 771 | clocks = <&uart3_clk>; |
| 772 | clock-names = "usart"; |
| 773 | status = "disabled"; |
| 774 | }; |
| 775 | |
Tiaki Rice | d5d8cab | 2020-05-08 01:56:32 +0000 | [diff] [blame] | 776 | uart4: serial@fc00c000 { |
| 777 | compatible = "atmel,at91sam9260-usart"; |
| 778 | reg = <0xfc00c000 0x100>; |
| 779 | clocks = <&uart4_clk>; |
| 780 | clock-names = "usart"; |
| 781 | status = "disabled"; |
| 782 | }; |
| 783 | |
Clément Léger | 8cde616 | 2022-03-31 10:55:07 +0200 | [diff] [blame] | 784 | aic: interrupt-controller@fc020000 { |
| 785 | #interrupt-cells = <3>; |
| 786 | compatible = "atmel,sama5d2-aic"; |
| 787 | interrupt-controller; |
| 788 | reg = <0xfc020000 0x200>; |
| 789 | atmel,external-irqs = <49>; |
| 790 | }; |
| 791 | |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 792 | i2c1: i2c@fc028000 { |
| 793 | compatible = "atmel,sama5d2-i2c"; |
| 794 | reg = <0xfc028000 0x100>; |
| 795 | #address-cells = <1>; |
| 796 | #size-cells = <0>; |
| 797 | clocks = <&twi1_clk>; |
| 798 | status = "disabled"; |
| 799 | }; |
| 800 | |
Sergiu Moga | 7c8ad0e | 2022-09-01 17:22:39 +0300 | [diff] [blame] | 801 | pioA: pinctrl@fc038000 { |
| 802 | compatible = "atmel,sama5d2-pinctrl"; |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 803 | reg = <0xfc038000 0x600>; |
| 804 | clocks = <&pioA_clk>; |
| 805 | gpio-controller; |
| 806 | #gpio-cells = <2>; |
Simon Glass | d3a98cb | 2023-02-13 08:56:33 -0700 | [diff] [blame] | 807 | bootph-all; |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 808 | }; |
| 809 | }; |
| 810 | }; |
Eugen Hristev | 8ab0bd7 | 2018-09-18 10:35:53 +0300 | [diff] [blame] | 811 | |
| 812 | onewire_tm: onewire { |
| 813 | compatible = "w1-gpio"; |
| 814 | status = "disabled"; |
| 815 | }; |
Wenyou Yang | 86ba221 | 2016-07-25 17:46:17 +0800 | [diff] [blame] | 816 | }; |