blob: dd6468ed96aaea4ed4cc278bddc7e7185adf9b16 [file] [log] [blame]
Wenyou Yang86ba2212016-07-25 17:46:17 +08001#include "skeleton.dtsi"
Clément Légere664bce2022-03-31 10:55:08 +02002#include <dt-bindings/interrupt-controller/irq.h>
Wenyou Yang86ba2212016-07-25 17:46:17 +08003
4/ {
5 model = "Atmel SAMA5D2 family SoC";
6 compatible = "atmel,sama5d2";
Clément Léger8cde6162022-03-31 10:55:07 +02007 interrupt-parent = <&aic>;
Wenyou Yang86ba2212016-07-25 17:46:17 +08008
9 aliases {
10 spi0 = &spi0;
11 spi1 = &qspi0;
Eugen Hristev235e8972019-08-26 06:47:03 +000012 spi2 = &qspi1;
Wenyou Yang86ba2212016-07-25 17:46:17 +080013 i2c0 = &i2c0;
14 i2c1 = &i2c1;
15 };
16
17 clocks {
18 slow_xtal: slow_xtal {
19 compatible = "fixed-clock";
20 #clock-cells = <0>;
21 clock-frequency = <0>;
22 };
23
24 main_xtal: main_xtal {
25 compatible = "fixed-clock";
26 #clock-cells = <0>;
27 clock-frequency = <0>;
28 };
29 };
30
31 ahb {
32 compatible = "simple-bus";
33 #address-cells = <1>;
34 #size-cells = <1>;
Simon Glassd3a98cb2023-02-13 08:56:33 -070035 bootph-all;
Wenyou Yang86ba2212016-07-25 17:46:17 +080036
Eugen Hristev21de2842021-08-17 13:29:24 +030037 usb1: ohci@400000 {
Wenyou Yang86ba2212016-07-25 17:46:17 +080038 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
39 reg = <0x00400000 0x100000>;
40 clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
41 clock-names = "ohci_clk", "hclk", "uhpck";
42 status = "disabled";
43 };
44
Eugen Hristev21de2842021-08-17 13:29:24 +030045 usb2: ehci@500000 {
Wenyou Yang86ba2212016-07-25 17:46:17 +080046 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
47 reg = <0x00500000 0x100000>;
48 clocks = <&utmi>, <&uhphs_clk>;
49 clock-names = "usb_clk", "ehci_clk";
50 status = "disabled";
51 };
52
53 sdmmc0: sdio-host@a0000000 {
54 compatible = "atmel,sama5d2-sdhci";
55 reg = <0xa0000000 0x300>;
56 clocks = <&sdmmc0_hclk>, <&sdmmc0_gclk>, <&main>;
57 clock-names = "hclock", "multclk", "baseclk";
58 status = "disabled";
59 };
60
61 sdmmc1: sdio-host@b0000000 {
62 compatible = "atmel,sama5d2-sdhci";
63 reg = <0xb0000000 0x300>;
64 clocks = <&sdmmc1_hclk>, <&sdmmc1_gclk>, <&main>;
65 clock-names = "hclock", "multclk", "baseclk";
66 status = "disabled";
67 };
68
69 apb {
70 compatible = "simple-bus";
71 #address-cells = <1>;
72 #size-cells = <1>;
Simon Glassd3a98cb2023-02-13 08:56:33 -070073 bootph-all;
Wenyou Yang86ba2212016-07-25 17:46:17 +080074
Wenyou Yang3ec18a62017-09-18 15:25:57 +080075 hlcdc: hlcdc@f0000000 {
76 compatible = "atmel,at91sam9x5-hlcdc";
77 reg = <0xf0000000 0x2000>;
78 clocks = <&lcdc_clk>;
79 status = "disabled";
80 };
81
Wenyou Yang86ba2212016-07-25 17:46:17 +080082 pmc: pmc@f0014000 {
83 compatible = "atmel,sama5d2-pmc", "syscon";
84 reg = <0xf0014000 0x160>;
85 #address-cells = <1>;
86 #size-cells = <0>;
Simon Glassd3a98cb2023-02-13 08:56:33 -070087 bootph-all;
Wenyou Yang86ba2212016-07-25 17:46:17 +080088
89 main: mainck {
90 compatible = "atmel,at91sam9x5-clk-main";
91 #clock-cells = <0>;
Simon Glassd3a98cb2023-02-13 08:56:33 -070092 bootph-all;
Wenyou Yang86ba2212016-07-25 17:46:17 +080093 };
94
Wenyou Yang354e10c2016-09-18 15:37:47 +080095 plla: pllack@0 {
Wenyou Yang86ba2212016-07-25 17:46:17 +080096 compatible = "atmel,sama5d3-clk-pll";
97 #clock-cells = <0>;
98 clocks = <&main>;
99 reg = <0>;
100 atmel,clk-input-range = <12000000 12000000>;
101 #atmel,pll-clk-output-range-cells = <4>;
102 atmel,pll-clk-output-ranges = <600000000 1200000000 0 0>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700103 bootph-all;
Wenyou Yang86ba2212016-07-25 17:46:17 +0800104 };
105
106 plladiv: plladivck {
107 compatible = "atmel,at91sam9x5-clk-plldiv";
108 #clock-cells = <0>;
109 clocks = <&plla>;
110 };
111
112 audio_pll_frac: audiopll_fracck {
113 compatible = "atmel,sama5d2-clk-audio-pll-frac";
114 #clock-cells = <0>;
115 clocks = <&main>;
116 };
117
118 audio_pll_pad: audiopll_padck {
119 compatible = "atmel,sama5d2-clk-audio-pll-pad";
120 #clock-cells = <0>;
121 clocks = <&audio_pll_frac>;
122 };
123
124 audio_pll_pmc: audiopll_pmcck {
125 compatible = "atmel,sama5d2-clk-audio-pll-pmc";
126 #clock-cells = <0>;
127 clocks = <&audio_pll_frac>;
128 };
129
130 utmi: utmick {
131 compatible = "atmel,at91sam9x5-clk-utmi";
132 #clock-cells = <0>;
133 clocks = <&main>;
Wenyou Yang75648fb2017-09-05 18:30:08 +0800134 regmap-sfr = <&sfr>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700135 bootph-all;
Wenyou Yang86ba2212016-07-25 17:46:17 +0800136 };
137
138 mck: masterck {
139 compatible = "atmel,at91sam9x5-clk-master";
140 #clock-cells = <0>;
141 clocks = <&main>, <&plladiv>, <&utmi>;
142 atmel,clk-output-range = <124000000 166000000>;
143 atmel,clk-divisors = <1 2 4 3>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700144 bootph-all;
Wenyou Yang86ba2212016-07-25 17:46:17 +0800145 };
146
147 h32ck: h32mxck {
148 #clock-cells = <0>;
149 compatible = "atmel,sama5d4-clk-h32mx";
150 clocks = <&mck>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700151 bootph-all;
Wenyou Yang86ba2212016-07-25 17:46:17 +0800152 };
153
154 usb: usbck {
155 compatible = "atmel,at91sam9x5-clk-usb";
156 #clock-cells = <0>;
157 clocks = <&plladiv>, <&utmi>;
158 };
159
160 prog: progck {
161 compatible = "atmel,at91sam9x5-clk-programmable";
162 #address-cells = <1>;
163 #size-cells = <0>;
164 interrupt-parent = <&pmc>;
165 clocks = <&main>, <&plladiv>, <&utmi>, <&mck>;
166
Wenyou Yang354e10c2016-09-18 15:37:47 +0800167 prog0: prog@0 {
Wenyou Yang86ba2212016-07-25 17:46:17 +0800168 #clock-cells = <0>;
169 reg = <0>;
170 };
171
Wenyou Yang354e10c2016-09-18 15:37:47 +0800172 prog1: prog@1 {
Wenyou Yang86ba2212016-07-25 17:46:17 +0800173 #clock-cells = <0>;
174 reg = <1>;
175 };
176
Wenyou Yang354e10c2016-09-18 15:37:47 +0800177 prog2: prog@2 {
Wenyou Yang86ba2212016-07-25 17:46:17 +0800178 #clock-cells = <0>;
179 reg = <2>;
180 };
181 };
182
183 systemck {
184 compatible = "atmel,at91rm9200-clk-system";
185 #address-cells = <1>;
186 #size-cells = <0>;
187
Wenyou Yang354e10c2016-09-18 15:37:47 +0800188 ddrck: ddrck@2 {
Wenyou Yang86ba2212016-07-25 17:46:17 +0800189 #clock-cells = <0>;
190 reg = <2>;
191 clocks = <&mck>;
192 };
193
Wenyou Yang354e10c2016-09-18 15:37:47 +0800194 lcdck: lcdck@3 {
Wenyou Yang86ba2212016-07-25 17:46:17 +0800195 #clock-cells = <0>;
196 reg = <3>;
197 clocks = <&mck>;
198 };
199
Wenyou Yang354e10c2016-09-18 15:37:47 +0800200 uhpck: uhpck@6 {
Wenyou Yang86ba2212016-07-25 17:46:17 +0800201 #clock-cells = <0>;
202 reg = <6>;
203 clocks = <&usb>;
204 };
205
Wenyou Yang354e10c2016-09-18 15:37:47 +0800206 udpck: udpck@7 {
Wenyou Yang86ba2212016-07-25 17:46:17 +0800207 #clock-cells = <0>;
208 reg = <7>;
209 clocks = <&usb>;
210 };
211
Wenyou Yang354e10c2016-09-18 15:37:47 +0800212 pck0: pck0@8 {
Wenyou Yang86ba2212016-07-25 17:46:17 +0800213 #clock-cells = <0>;
214 reg = <8>;
215 clocks = <&prog0>;
216 };
217
Wenyou Yang354e10c2016-09-18 15:37:47 +0800218 pck1: pck1@9 {
Wenyou Yang86ba2212016-07-25 17:46:17 +0800219 #clock-cells = <0>;
220 reg = <9>;
221 clocks = <&prog1>;
222 };
223
Wenyou Yang354e10c2016-09-18 15:37:47 +0800224 pck2: pck2@10 {
Wenyou Yang86ba2212016-07-25 17:46:17 +0800225 #clock-cells = <0>;
226 reg = <10>;
227 clocks = <&prog2>;
228 };
229
Wenyou Yang354e10c2016-09-18 15:37:47 +0800230 iscck: iscck@18 {
Wenyou Yang86ba2212016-07-25 17:46:17 +0800231 #clock-cells = <0>;
232 reg = <18>;
233 clocks = <&mck>;
234 };
235 };
236
237 periph32ck {
238 compatible = "atmel,at91sam9x5-clk-peripheral";
239 #address-cells = <1>;
240 #size-cells = <0>;
241 clocks = <&h32ck>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700242 bootph-all;
Wenyou Yang86ba2212016-07-25 17:46:17 +0800243
Wenyou Yang354e10c2016-09-18 15:37:47 +0800244 macb0_clk: macb0_clk@5 {
Wenyou Yang86ba2212016-07-25 17:46:17 +0800245 #clock-cells = <0>;
246 reg = <5>;
247 atmel,clk-output-range = <0 83000000>;
248 };
249
Wenyou Yang354e10c2016-09-18 15:37:47 +0800250 tdes_clk: tdes_clk@11 {
Wenyou Yang86ba2212016-07-25 17:46:17 +0800251 #clock-cells = <0>;
252 reg = <11>;
253 atmel,clk-output-range = <0 83000000>;
254 };
255
Wenyou Yang354e10c2016-09-18 15:37:47 +0800256 matrix1_clk: matrix1_clk@14 {
Wenyou Yang86ba2212016-07-25 17:46:17 +0800257 #clock-cells = <0>;
258 reg = <14>;
259 };
260
Wenyou Yang354e10c2016-09-18 15:37:47 +0800261 hsmc_clk: hsmc_clk@17 {
Wenyou Yang86ba2212016-07-25 17:46:17 +0800262 #clock-cells = <0>;
263 reg = <17>;
264 };
265
Wenyou Yang354e10c2016-09-18 15:37:47 +0800266 pioA_clk: pioA_clk@18 {
Wenyou Yang86ba2212016-07-25 17:46:17 +0800267 #clock-cells = <0>;
268 reg = <18>;
269 atmel,clk-output-range = <0 83000000>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700270 bootph-all;
Wenyou Yang86ba2212016-07-25 17:46:17 +0800271 };
272
Wenyou Yang354e10c2016-09-18 15:37:47 +0800273 flx0_clk: flx0_clk@19 {
Wenyou Yang86ba2212016-07-25 17:46:17 +0800274 #clock-cells = <0>;
275 reg = <19>;
276 atmel,clk-output-range = <0 83000000>;
277 };
278
Wenyou Yang354e10c2016-09-18 15:37:47 +0800279 flx1_clk: flx1_clk@20 {
Wenyou Yang86ba2212016-07-25 17:46:17 +0800280 #clock-cells = <0>;
281 reg = <20>;
282 atmel,clk-output-range = <0 83000000>;
283 };
284
Wenyou Yang354e10c2016-09-18 15:37:47 +0800285 flx2_clk: flx2_clk@21 {
Wenyou Yang86ba2212016-07-25 17:46:17 +0800286 #clock-cells = <0>;
287 reg = <21>;
288 atmel,clk-output-range = <0 83000000>;
289 };
290
Wenyou Yang354e10c2016-09-18 15:37:47 +0800291 flx3_clk: flx3_clk@22 {
Wenyou Yang86ba2212016-07-25 17:46:17 +0800292 #clock-cells = <0>;
293 reg = <22>;
294 atmel,clk-output-range = <0 83000000>;
295 };
296
Wenyou Yang354e10c2016-09-18 15:37:47 +0800297 flx4_clk: flx4_clk@23 {
Wenyou Yang86ba2212016-07-25 17:46:17 +0800298 #clock-cells = <0>;
299 reg = <23>;
300 atmel,clk-output-range = <0 83000000>;
301 };
302
Wenyou Yang354e10c2016-09-18 15:37:47 +0800303 uart0_clk: uart0_clk@24 {
Wenyou Yang86ba2212016-07-25 17:46:17 +0800304 #clock-cells = <0>;
305 reg = <24>;
306 atmel,clk-output-range = <0 83000000>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700307 bootph-all;
Wenyou Yang86ba2212016-07-25 17:46:17 +0800308 };
309
Wenyou Yang354e10c2016-09-18 15:37:47 +0800310 uart1_clk: uart1_clk@25 {
Wenyou Yang86ba2212016-07-25 17:46:17 +0800311 #clock-cells = <0>;
312 reg = <25>;
313 atmel,clk-output-range = <0 83000000>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700314 bootph-all;
Wenyou Yang86ba2212016-07-25 17:46:17 +0800315 };
316
Wenyou Yang354e10c2016-09-18 15:37:47 +0800317 uart2_clk: uart2_clk@26 {
Wenyou Yang86ba2212016-07-25 17:46:17 +0800318 #clock-cells = <0>;
319 reg = <26>;
320 atmel,clk-output-range = <0 83000000>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700321 bootph-all;
Wenyou Yang86ba2212016-07-25 17:46:17 +0800322 };
323
Wenyou Yang354e10c2016-09-18 15:37:47 +0800324 uart3_clk: uart3_clk@27 {
Wenyou Yang86ba2212016-07-25 17:46:17 +0800325 #clock-cells = <0>;
326 reg = <27>;
327 atmel,clk-output-range = <0 83000000>;
328 };
329
Wenyou Yang354e10c2016-09-18 15:37:47 +0800330 uart4_clk: uart4_clk@28 {
Wenyou Yang86ba2212016-07-25 17:46:17 +0800331 #clock-cells = <0>;
332 reg = <28>;
333 atmel,clk-output-range = <0 83000000>;
334 };
335
Wenyou Yang354e10c2016-09-18 15:37:47 +0800336 twi0_clk: twi0_clk@29 {
Wenyou Yang86ba2212016-07-25 17:46:17 +0800337 reg = <29>;
338 #clock-cells = <0>;
339 atmel,clk-output-range = <0 83000000>;
340 };
341
Wenyou Yang354e10c2016-09-18 15:37:47 +0800342 twi1_clk: twi1_clk@30 {
Wenyou Yang86ba2212016-07-25 17:46:17 +0800343 #clock-cells = <0>;
344 reg = <30>;
345 atmel,clk-output-range = <0 83000000>;
346 };
347
Wenyou Yang354e10c2016-09-18 15:37:47 +0800348 spi0_clk: spi0_clk@33 {
Wenyou Yang86ba2212016-07-25 17:46:17 +0800349 #clock-cells = <0>;
350 reg = <33>;
351 atmel,clk-output-range = <0 83000000>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700352 bootph-all;
Wenyou Yang86ba2212016-07-25 17:46:17 +0800353 };
354
Wenyou Yang354e10c2016-09-18 15:37:47 +0800355 spi1_clk: spi1_clk@34 {
Wenyou Yang86ba2212016-07-25 17:46:17 +0800356 #clock-cells = <0>;
357 reg = <34>;
358 atmel,clk-output-range = <0 83000000>;
359 };
360
Wenyou Yang354e10c2016-09-18 15:37:47 +0800361 tcb0_clk: tcb0_clk@35 {
Wenyou Yang86ba2212016-07-25 17:46:17 +0800362 #clock-cells = <0>;
363 reg = <35>;
364 atmel,clk-output-range = <0 83000000>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700365 bootph-all;
Wenyou Yang86ba2212016-07-25 17:46:17 +0800366 };
367
Wenyou Yang354e10c2016-09-18 15:37:47 +0800368 tcb1_clk: tcb1_clk@36 {
Wenyou Yang86ba2212016-07-25 17:46:17 +0800369 #clock-cells = <0>;
370 reg = <36>;
371 atmel,clk-output-range = <0 83000000>;
372 };
373
Wenyou Yang354e10c2016-09-18 15:37:47 +0800374 pwm_clk: pwm_clk@38 {
Wenyou Yang86ba2212016-07-25 17:46:17 +0800375 #clock-cells = <0>;
376 reg = <38>;
377 atmel,clk-output-range = <0 83000000>;
378 };
379
Wenyou Yang354e10c2016-09-18 15:37:47 +0800380 adc_clk: adc_clk@40 {
Wenyou Yang86ba2212016-07-25 17:46:17 +0800381 #clock-cells = <0>;
382 reg = <40>;
383 atmel,clk-output-range = <0 83000000>;
384 };
385
Wenyou Yang354e10c2016-09-18 15:37:47 +0800386 uhphs_clk: uhphs_clk@41 {
Wenyou Yang86ba2212016-07-25 17:46:17 +0800387 #clock-cells = <0>;
388 reg = <41>;
389 atmel,clk-output-range = <0 83000000>;
390 };
391
Wenyou Yang354e10c2016-09-18 15:37:47 +0800392 udphs_clk: udphs_clk@42 {
Wenyou Yang86ba2212016-07-25 17:46:17 +0800393 #clock-cells = <0>;
394 reg = <42>;
395 atmel,clk-output-range = <0 83000000>;
396 };
397
Wenyou Yang354e10c2016-09-18 15:37:47 +0800398 ssc0_clk: ssc0_clk@43 {
Wenyou Yang86ba2212016-07-25 17:46:17 +0800399 #clock-cells = <0>;
400 reg = <43>;
401 atmel,clk-output-range = <0 83000000>;
402 };
403
Wenyou Yang354e10c2016-09-18 15:37:47 +0800404 ssc1_clk: ssc1_clk@44 {
Wenyou Yang86ba2212016-07-25 17:46:17 +0800405 #clock-cells = <0>;
406 reg = <44>;
407 atmel,clk-output-range = <0 83000000>;
408 };
409
Wenyou Yang354e10c2016-09-18 15:37:47 +0800410 trng_clk: trng_clk@47 {
Wenyou Yang86ba2212016-07-25 17:46:17 +0800411 #clock-cells = <0>;
412 reg = <47>;
413 atmel,clk-output-range = <0 83000000>;
414 };
415
Wenyou Yang354e10c2016-09-18 15:37:47 +0800416 pdmic_clk: pdmic_clk@48 {
Wenyou Yang86ba2212016-07-25 17:46:17 +0800417 #clock-cells = <0>;
418 reg = <48>;
419 atmel,clk-output-range = <0 83000000>;
420 };
421
Wenyou Yang354e10c2016-09-18 15:37:47 +0800422 i2s0_clk: i2s0_clk@54 {
Wenyou Yang86ba2212016-07-25 17:46:17 +0800423 #clock-cells = <0>;
424 reg = <54>;
425 atmel,clk-output-range = <0 83000000>;
426 };
427
Wenyou Yang354e10c2016-09-18 15:37:47 +0800428 i2s1_clk: i2s1_clk@55 {
Wenyou Yang86ba2212016-07-25 17:46:17 +0800429 #clock-cells = <0>;
430 reg = <55>;
431 atmel,clk-output-range = <0 83000000>;
432 };
433
Wenyou Yang354e10c2016-09-18 15:37:47 +0800434 can0_clk: can0_clk@56 {
Wenyou Yang86ba2212016-07-25 17:46:17 +0800435 #clock-cells = <0>;
436 reg = <56>;
437 atmel,clk-output-range = <0 83000000>;
438 };
439
Wenyou Yang354e10c2016-09-18 15:37:47 +0800440 can1_clk: can1_clk@57 {
Wenyou Yang86ba2212016-07-25 17:46:17 +0800441 #clock-cells = <0>;
442 reg = <57>;
443 atmel,clk-output-range = <0 83000000>;
444 };
445
Wenyou Yang354e10c2016-09-18 15:37:47 +0800446 classd_clk: classd_clk@59 {
Wenyou Yang86ba2212016-07-25 17:46:17 +0800447 #clock-cells = <0>;
448 reg = <59>;
449 atmel,clk-output-range = <0 83000000>;
450 };
451 };
452
453 periph64ck {
454 compatible = "atmel,at91sam9x5-clk-peripheral";
455 #address-cells = <1>;
456 #size-cells = <0>;
457 clocks = <&mck>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700458 bootph-all;
Wenyou Yang86ba2212016-07-25 17:46:17 +0800459
Wenyou Yang354e10c2016-09-18 15:37:47 +0800460 dma0_clk: dma0_clk@6 {
Wenyou Yang86ba2212016-07-25 17:46:17 +0800461 #clock-cells = <0>;
462 reg = <6>;
463 };
464
Wenyou Yang354e10c2016-09-18 15:37:47 +0800465 dma1_clk: dma1_clk@7 {
Wenyou Yang86ba2212016-07-25 17:46:17 +0800466 #clock-cells = <0>;
467 reg = <7>;
468 };
469
Wenyou Yang354e10c2016-09-18 15:37:47 +0800470 aes_clk: aes_clk@9 {
Wenyou Yang86ba2212016-07-25 17:46:17 +0800471 #clock-cells = <0>;
472 reg = <9>;
473 };
474
Wenyou Yang354e10c2016-09-18 15:37:47 +0800475 aesb_clk: aesb_clk@10 {
Wenyou Yang86ba2212016-07-25 17:46:17 +0800476 #clock-cells = <0>;
477 reg = <10>;
478 };
479
Wenyou Yang354e10c2016-09-18 15:37:47 +0800480 sha_clk: sha_clk@12 {
Wenyou Yang86ba2212016-07-25 17:46:17 +0800481 #clock-cells = <0>;
482 reg = <12>;
483 };
484
Wenyou Yang354e10c2016-09-18 15:37:47 +0800485 mpddr_clk: mpddr_clk@13 {
Wenyou Yang86ba2212016-07-25 17:46:17 +0800486 #clock-cells = <0>;
487 reg = <13>;
488 };
489
Wenyou Yang354e10c2016-09-18 15:37:47 +0800490 matrix0_clk: matrix0_clk@15 {
Wenyou Yang86ba2212016-07-25 17:46:17 +0800491 #clock-cells = <0>;
492 reg = <15>;
493 };
494
Wenyou Yang354e10c2016-09-18 15:37:47 +0800495 sdmmc0_hclk: sdmmc0_hclk@31 {
Wenyou Yang86ba2212016-07-25 17:46:17 +0800496 #clock-cells = <0>;
497 reg = <31>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700498 bootph-all;
Wenyou Yang86ba2212016-07-25 17:46:17 +0800499 };
500
Wenyou Yang354e10c2016-09-18 15:37:47 +0800501 sdmmc1_hclk: sdmmc1_hclk@32 {
Wenyou Yang86ba2212016-07-25 17:46:17 +0800502 #clock-cells = <0>;
503 reg = <32>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700504 bootph-all;
Wenyou Yang86ba2212016-07-25 17:46:17 +0800505 };
506
Wenyou Yang354e10c2016-09-18 15:37:47 +0800507 lcdc_clk: lcdc_clk@45 {
Wenyou Yang86ba2212016-07-25 17:46:17 +0800508 #clock-cells = <0>;
509 reg = <45>;
510 };
511
Wenyou Yang354e10c2016-09-18 15:37:47 +0800512 isc_clk: isc_clk@46 {
Wenyou Yang86ba2212016-07-25 17:46:17 +0800513 #clock-cells = <0>;
514 reg = <46>;
515 };
516
Wenyou Yang354e10c2016-09-18 15:37:47 +0800517 qspi0_clk: qspi0_clk@52 {
Wenyou Yang86ba2212016-07-25 17:46:17 +0800518 #clock-cells = <0>;
519 reg = <52>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700520 bootph-all;
Wenyou Yang86ba2212016-07-25 17:46:17 +0800521 };
522
Wenyou Yang354e10c2016-09-18 15:37:47 +0800523 qspi1_clk: qspi1_clk@53 {
Wenyou Yang86ba2212016-07-25 17:46:17 +0800524 #clock-cells = <0>;
525 reg = <53>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700526 bootph-all;
Wenyou Yang86ba2212016-07-25 17:46:17 +0800527 };
528 };
529
530 gck {
531 compatible = "atmel,sama5d2-clk-generated";
532 #address-cells = <1>;
533 #size-cells = <0>;
534 interrupt-parent = <&pmc>;
535 clocks = <&main>, <&plla>, <&utmi>, <&mck>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700536 bootph-all;
Wenyou Yang86ba2212016-07-25 17:46:17 +0800537
Wenyou Yang354e10c2016-09-18 15:37:47 +0800538 sdmmc0_gclk: sdmmc0_gclk@31 {
Wenyou Yang86ba2212016-07-25 17:46:17 +0800539 #clock-cells = <0>;
540 reg = <31>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700541 bootph-all;
Wenyou Yang86ba2212016-07-25 17:46:17 +0800542 };
543
Wenyou Yang354e10c2016-09-18 15:37:47 +0800544 sdmmc1_gclk: sdmmc1_gclk@32 {
Wenyou Yang86ba2212016-07-25 17:46:17 +0800545 #clock-cells = <0>;
546 reg = <32>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700547 bootph-all;
Wenyou Yang86ba2212016-07-25 17:46:17 +0800548 };
549
Wenyou Yang354e10c2016-09-18 15:37:47 +0800550 tcb0_gclk: tcb0_gclk@35 {
Wenyou Yang86ba2212016-07-25 17:46:17 +0800551 #clock-cells = <0>;
552 reg = <35>;
553 atmel,clk-output-range = <0 83000000>;
554 };
555
Wenyou Yang354e10c2016-09-18 15:37:47 +0800556 tcb1_gclk: tcb1_gclk@36 {
Wenyou Yang86ba2212016-07-25 17:46:17 +0800557 #clock-cells = <0>;
558 reg = <36>;
559 atmel,clk-output-range = <0 83000000>;
560 };
561
Wenyou Yang354e10c2016-09-18 15:37:47 +0800562 pwm_gclk: pwm_gclk@38 {
Wenyou Yang86ba2212016-07-25 17:46:17 +0800563 #clock-cells = <0>;
564 reg = <38>;
565 atmel,clk-output-range = <0 83000000>;
566 };
567
Wenyou Yang354e10c2016-09-18 15:37:47 +0800568 pdmic_gclk: pdmic_gclk@48 {
Wenyou Yang86ba2212016-07-25 17:46:17 +0800569 #clock-cells = <0>;
570 reg = <48>;
571 };
572
Wenyou Yang354e10c2016-09-18 15:37:47 +0800573 i2s0_gclk: i2s0_gclk@54 {
Wenyou Yang86ba2212016-07-25 17:46:17 +0800574 #clock-cells = <0>;
575 reg = <54>;
576 };
577
Wenyou Yang354e10c2016-09-18 15:37:47 +0800578 i2s1_gclk: i2s1_gclk@55 {
Wenyou Yang86ba2212016-07-25 17:46:17 +0800579 #clock-cells = <0>;
580 reg = <55>;
581 };
582
Wenyou Yang354e10c2016-09-18 15:37:47 +0800583 can0_gclk: can0_gclk@56 {
Wenyou Yang86ba2212016-07-25 17:46:17 +0800584 #clock-cells = <0>;
585 reg = <56>;
586 atmel,clk-output-range = <0 80000000>;
587 };
588
Wenyou Yang354e10c2016-09-18 15:37:47 +0800589 can1_gclk: can1_gclk@57 {
Wenyou Yang86ba2212016-07-25 17:46:17 +0800590 #clock-cells = <0>;
591 reg = <57>;
592 atmel,clk-output-range = <0 80000000>;
593 };
594
Wenyou Yang354e10c2016-09-18 15:37:47 +0800595 classd_gclk: classd_gclk@59 {
Wenyou Yang86ba2212016-07-25 17:46:17 +0800596 #clock-cells = <0>;
597 reg = <59>;
598 atmel,clk-output-range = <0 100000000>;
599 };
600 };
601 };
602
603 qspi0: spi@f0020000 {
604 compatible = "atmel,sama5d2-qspi";
605 reg = <0xf0020000 0x100>, <0xd0000000 0x08000000>;
606 reg-names = "qspi_base", "qspi_mmap";
607 #address-cells = <1>;
608 #size-cells = <0>;
609 clocks = <&qspi0_clk>;
610 status = "disabled";
611 };
612
Wenyou Yangeebb0732017-09-13 14:58:54 +0800613 qspi1: spi@f0024000 {
614 compatible = "atmel,sama5d2-qspi";
615 reg = <0xf0024000 0x100>, <0xd8000000 0x08000000>;
616 reg-names = "qspi_base", "qspi_mmap";
617 #address-cells = <1>;
618 #size-cells = <0>;
619 clocks = <&qspi1_clk>;
620 status = "disabled";
621 };
622
Wenyou Yang86ba2212016-07-25 17:46:17 +0800623 spi0: spi@f8000000 {
624 compatible = "atmel,at91rm9200-spi";
625 reg = <0xf8000000 0x100>;
626 clocks = <&spi0_clk>;
627 clock-names = "spi_clk";
628 #address-cells = <1>;
629 #size-cells = <0>;
630 status = "disabled";
631 };
632
633 macb0: ethernet@f8008000 {
634 compatible = "cdns,macb";
635 reg = <0xf8008000 0x1000>;
636 #address-cells = <1>;
637 #size-cells = <0>;
638 clocks = <&macb0_clk>, <&macb0_clk>;
639 clock-names = "hclk", "pclk";
640 status = "disabled";
641 };
642
Clément Légere664bce2022-03-31 10:55:08 +0200643 tcb0: timer@f800c000 {
644 compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon";
645 reg = <0xf800c000 0x100>;
646 interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>;
647 clocks = <&tcb0_clk>, <&tcb0_gclk>, <&clk32k>;
648 clock-names = "t0_clk", "gclk", "slow_clk";
649 #address-cells = <1>;
650 #size-cells = <0>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700651 bootph-all;
Clément Légere664bce2022-03-31 10:55:08 +0200652
653 timer0: timer@0 {
654 compatible = "atmel,tcb-timer";
655 reg = <0>, <1>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700656 bootph-all;
Clément Légere664bce2022-03-31 10:55:08 +0200657 };
658 };
659
Ludovic Desroches1240d882017-11-17 14:57:12 +0800660 uart0: serial@f801c000 {
661 compatible = "atmel,at91sam9260-usart";
662 reg = <0xf801c000 0x100>;
663 clocks = <&uart0_clk>;
664 clock-names = "usart";
665 status = "disabled";
666 };
667
Wenyou Yang86ba2212016-07-25 17:46:17 +0800668 uart1: serial@f8020000 {
669 compatible = "atmel,at91sam9260-usart";
670 reg = <0xf8020000 0x100>;
Wenyou Yang4e3524d2017-03-23 14:26:22 +0800671 clocks = <&uart1_clk>;
672 clock-names = "usart";
Wenyou Yang86ba2212016-07-25 17:46:17 +0800673 status = "disabled";
674 };
675
Ludovic Desroches1240d882017-11-17 14:57:12 +0800676 uart2: serial@f8024000 {
677 compatible = "atmel,at91sam9260-usart";
678 reg = <0xf8024000 0x100>;
679 clocks = <&uart2_clk>;
680 clock-names = "usart";
681 status = "disabled";
682 };
683
Wenyou Yang86ba2212016-07-25 17:46:17 +0800684 i2c0: i2c@f8028000 {
685 compatible = "atmel,sama5d2-i2c";
686 reg = <0xf8028000 0x100>;
687 #address-cells = <1>;
688 #size-cells = <0>;
689 clocks = <&twi0_clk>;
690 status = "disabled";
691 };
692
Dan Sneddonf09aa3f2021-09-20 16:28:46 -0700693 pwm0: pwm@f802c000 {
694 compatible = "atmel,sama5d2-pwm";
695 reg = <0xf802c000 0x4000>;
696 clocks = <&pwm_clk>;
697 #pwm-cells = <3>;
698 status = "disabled";
699 };
700
Wenyou.Yang@microchip.com272167d2017-08-15 17:40:27 +0800701 rstc@f8048000 {
702 compatible = "atmel,sama5d3-rstc";
703 reg = <0xf8048000 0x10>;
704 clocks = <&clk32k>;
705 };
706
707 shdwc@f8048010 {
708 compatible = "atmel,sama5d2-shdwc";
709 reg = <0xf8048010 0x10>;
710 clocks = <&clk32k>;
711 #address-cells = <1>;
712 #size-cells = <0>;
713 atmel,wakeup-rtc-timer;
714 };
715
716 pit: timer@f8048030 {
717 compatible = "atmel,at91sam9260-pit";
718 reg = <0xf8048030 0x10>;
719 clocks = <&h32ck>;
720 };
721
722 watchdog@f8048040 {
723 compatible = "atmel,sama5d4-wdt";
724 reg = <0xf8048040 0x10>;
725 clocks = <&clk32k>;
726 status = "disabled";
727 };
728
Wenyou Yang75648fb2017-09-05 18:30:08 +0800729 sfr: sfr@f8030000 {
730 compatible = "atmel,sama5d2-sfr", "syscon";
731 reg = <0xf8030000 0x98>;
732 };
733
Wenyou Yang86ba2212016-07-25 17:46:17 +0800734 sckc@f8048050 {
735 compatible = "atmel,at91sam9x5-sckc";
736 reg = <0xf8048050 0x4>;
737
738 slow_rc_osc: slow_rc_osc {
739 compatible = "atmel,at91sam9x5-clk-slow-rc-osc";
740 #clock-cells = <0>;
741 clock-frequency = <32768>;
742 clock-accuracy = <250000000>;
743 atmel,startup-time-usec = <75>;
744 };
745
746 slow_osc: slow_osc {
747 compatible = "atmel,at91sam9x5-clk-slow-osc";
748 #clock-cells = <0>;
749 clocks = <&slow_xtal>;
750 atmel,startup-time-usec = <1200000>;
751 };
752
753 clk32k: slowck {
754 compatible = "atmel,at91sam9x5-clk-slow";
755 #clock-cells = <0>;
756 clocks = <&slow_rc_osc &slow_osc>;
757 };
758 };
759
760 spi1: spi@fc000000 {
761 compatible = "atmel,at91rm9200-spi";
762 reg = <0xfc000000 0x100>;
763 #address-cells = <1>;
764 #size-cells = <0>;
765 status = "disabled";
766 };
767
Wenyou Yangeebb0732017-09-13 14:58:54 +0800768 uart3: serial@fc008000 {
769 compatible = "atmel,at91sam9260-usart";
770 reg = <0xfc008000 0x100>;
771 clocks = <&uart3_clk>;
772 clock-names = "usart";
773 status = "disabled";
774 };
775
Tiaki Riced5d8cab2020-05-08 01:56:32 +0000776 uart4: serial@fc00c000 {
777 compatible = "atmel,at91sam9260-usart";
778 reg = <0xfc00c000 0x100>;
779 clocks = <&uart4_clk>;
780 clock-names = "usart";
781 status = "disabled";
782 };
783
Clément Léger8cde6162022-03-31 10:55:07 +0200784 aic: interrupt-controller@fc020000 {
785 #interrupt-cells = <3>;
786 compatible = "atmel,sama5d2-aic";
787 interrupt-controller;
788 reg = <0xfc020000 0x200>;
789 atmel,external-irqs = <49>;
790 };
791
Wenyou Yang86ba2212016-07-25 17:46:17 +0800792 i2c1: i2c@fc028000 {
793 compatible = "atmel,sama5d2-i2c";
794 reg = <0xfc028000 0x100>;
795 #address-cells = <1>;
796 #size-cells = <0>;
797 clocks = <&twi1_clk>;
798 status = "disabled";
799 };
800
Sergiu Moga7c8ad0e2022-09-01 17:22:39 +0300801 pioA: pinctrl@fc038000 {
802 compatible = "atmel,sama5d2-pinctrl";
Wenyou Yang86ba2212016-07-25 17:46:17 +0800803 reg = <0xfc038000 0x600>;
804 clocks = <&pioA_clk>;
805 gpio-controller;
806 #gpio-cells = <2>;
Simon Glassd3a98cb2023-02-13 08:56:33 -0700807 bootph-all;
Wenyou Yang86ba2212016-07-25 17:46:17 +0800808 };
809 };
810 };
Eugen Hristev8ab0bd72018-09-18 10:35:53 +0300811
812 onewire_tm: onewire {
813 compatible = "w1-gpio";
814 status = "disabled";
815 };
Wenyou Yang86ba2212016-07-25 17:46:17 +0800816};