| Khoronzhuk, Ivan | 50df5cc | 2014-07-09 19:48:40 +0300 | [diff] [blame] | 1 | /* |
| 2 | * DDR3 |
| 3 | * |
| 4 | * (C) Copyright 2014 |
| 5 | * Texas Instruments Incorporated, <www.ti.com> |
| 6 | * |
| 7 | * SPDX-License-Identifier: GPL-2.0+ |
| 8 | */ |
| 9 | |
| 10 | #ifndef _DDR3_H_ |
| 11 | #define _DDR3_H_ |
| 12 | |
| 13 | #include <asm/arch/hardware.h> |
| 14 | |
| 15 | struct ddr3_phy_config { |
| 16 | unsigned int pllcr; |
| 17 | unsigned int pgcr1_mask; |
| 18 | unsigned int pgcr1_val; |
| 19 | unsigned int ptr0; |
| 20 | unsigned int ptr1; |
| 21 | unsigned int ptr2; |
| 22 | unsigned int ptr3; |
| 23 | unsigned int ptr4; |
| 24 | unsigned int dcr_mask; |
| 25 | unsigned int dcr_val; |
| 26 | unsigned int dtpr0; |
| 27 | unsigned int dtpr1; |
| 28 | unsigned int dtpr2; |
| 29 | unsigned int mr0; |
| 30 | unsigned int mr1; |
| 31 | unsigned int mr2; |
| 32 | unsigned int dtcr; |
| 33 | unsigned int pgcr2; |
| 34 | unsigned int zq0cr1; |
| 35 | unsigned int zq1cr1; |
| 36 | unsigned int zq2cr1; |
| 37 | unsigned int pir_v1; |
| 38 | unsigned int pir_v2; |
| 39 | }; |
| 40 | |
| 41 | struct ddr3_emif_config { |
| 42 | unsigned int sdcfg; |
| 43 | unsigned int sdtim1; |
| 44 | unsigned int sdtim2; |
| 45 | unsigned int sdtim3; |
| 46 | unsigned int sdtim4; |
| 47 | unsigned int zqcfg; |
| 48 | unsigned int sdrfc; |
| 49 | }; |
| 50 | |
| 51 | void ddr3_init(void); |
| Hao Zhang | d6c508c | 2014-07-09 19:48:41 +0300 | [diff] [blame] | 52 | void ddr3_reset_ddrphy(void); |
| Murali Karicheri | 39f4520 | 2014-09-10 15:54:59 +0300 | [diff] [blame^] | 53 | void ddr3_err_reset_workaround(void); |
| Khoronzhuk, Ivan | 50df5cc | 2014-07-09 19:48:40 +0300 | [diff] [blame] | 54 | void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg); |
| 55 | void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg); |
| 56 | |
| 57 | #endif |