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git01.mediatek.com / filogic / uboot / 39c5bef6d9d625c137f9dc5c99a0984d5b4507c6 / . / board / altera / cyclone5-socdk / qts / pinmux_config.h
blob: ec64ae17a1671bddd5646c5ac003af1e52b6f15d [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -0400[diff] [blame]1/* SPDX-License-Identifier: BSD-3-Clause */
Chin Liang See967b4df2013-09-11 11:26:10 -0500[diff] [blame]2/*
Marek Vasut372f70d2015-08-10 21:21:07 +0200[diff] [blame]3 * Altera SoCFPGA PinMux configuration
Chin Liang See967b4df2013-09-11 11:26:10 -0500[diff] [blame]4 */
Chin Liang See967b4df2013-09-11 11:26:10 -0500[diff] [blame]5
Marek Vasut372f70d2015-08-10 21:21:07 +0200[diff] [blame]6#ifndef __SOCFPGA_PINMUX_CONFIG_H__
7#define __SOCFPGA_PINMUX_CONFIG_H__
Chin Liang See967b4df2013-09-11 11:26:10 -0500[diff] [blame]8
Marek Vasut7b648732015-08-10 22:17:46 +0200[diff] [blame]9const u8 sys_mgr_init_table[] = {
Dinh Nguyend28f4a72016-05-10 15:13:59 -0500[diff] [blame]10 0, /* EMACIO0 */
shengjiangwud88311a2015-12-23 10:37:31 +0800[diff] [blame]11 2, /* EMACIO1 */
12 2, /* EMACIO2 */
13 2, /* EMACIO3 */
14 2, /* EMACIO4 */
15 2, /* EMACIO5 */
16 2, /* EMACIO6 */
17 2, /* EMACIO7 */
18 2, /* EMACIO8 */
Dinh Nguyend28f4a72016-05-10 15:13:59 -0500[diff] [blame]19 0, /* EMACIO9 */
shengjiangwud88311a2015-12-23 10:37:31 +0800[diff] [blame]20 2, /* EMACIO10 */
21 2, /* EMACIO11 */
22 2, /* EMACIO12 */
23 2, /* EMACIO13 */
Marek Vasut372f70d2015-08-10 21:21:07 +0200[diff] [blame]24 0, /* EMACIO14 */
25 0, /* EMACIO15 */
26 0, /* EMACIO16 */
27 0, /* EMACIO17 */
28 0, /* EMACIO18 */
29 0, /* EMACIO19 */
30 3, /* FLASHIO0 */
31 0, /* FLASHIO1 */
32 3, /* FLASHIO2 */
33 3, /* FLASHIO3 */
Dinh Nguyend28f4a72016-05-10 15:13:59 -0500[diff] [blame]34 0, /* FLASHIO4 */
35 0, /* FLASHIO5 */
36 0, /* FLASHIO6 */
37 0, /* FLASHIO7 */
Marek Vasut372f70d2015-08-10 21:21:07 +0200[diff] [blame]38 0, /* FLASHIO8 */
39 3, /* FLASHIO9 */
40 3, /* FLASHIO10 */
41 3, /* FLASHIO11 */
Dinh Nguyend28f4a72016-05-10 15:13:59 -0500[diff] [blame]42 3, /* GENERALIO0 */
43 3, /* GENERALIO1 */
44 3, /* GENERALIO2 */
45 3, /* GENERALIO3 */
46 3, /* GENERALIO4 */
47 3, /* GENERALIO5 */
48 3, /* GENERALIO6 */
49 3, /* GENERALIO7 */
50 3, /* GENERALIO8 */
51 3, /* GENERALIO9 */
52 3, /* GENERALIO10 */
53 3, /* GENERALIO11 */
54 3, /* GENERALIO12 */
Marek Vasut372f70d2015-08-10 21:21:07 +0200[diff] [blame]55 2, /* GENERALIO13 */
56 2, /* GENERALIO14 */
Chin Liang See544a9e42015-12-23 22:07:49 +0800[diff] [blame]57 3, /* GENERALIO15 */
58 3, /* GENERALIO16 */
Marek Vasut372f70d2015-08-10 21:21:07 +0200[diff] [blame]59 2, /* GENERALIO17 */
60 2, /* GENERALIO18 */
61 0, /* GENERALIO19 */
62 0, /* GENERALIO20 */
63 0, /* GENERALIO21 */
64 0, /* GENERALIO22 */
65 0, /* GENERALIO23 */
66 0, /* GENERALIO24 */
67 0, /* GENERALIO25 */
68 0, /* GENERALIO26 */
69 0, /* GENERALIO27 */
70 0, /* GENERALIO28 */
71 0, /* GENERALIO29 */
72 0, /* GENERALIO30 */
73 0, /* GENERALIO31 */
shengjiangwuc213f632015-12-22 15:22:02 +0800[diff] [blame]74 2, /* MIXED1IO0 */
75 2, /* MIXED1IO1 */
76 2, /* MIXED1IO2 */
77 2, /* MIXED1IO3 */
78 2, /* MIXED1IO4 */
79 2, /* MIXED1IO5 */
80 2, /* MIXED1IO6 */
81 2, /* MIXED1IO7 */
82 2, /* MIXED1IO8 */
83 2, /* MIXED1IO9 */
84 2, /* MIXED1IO10 */
85 2, /* MIXED1IO11 */
86 2, /* MIXED1IO12 */
87 2, /* MIXED1IO13 */
Marek Vasut372f70d2015-08-10 21:21:07 +0200[diff] [blame]88 0, /* MIXED1IO14 */
shengjiangwu418db662015-12-22 17:18:09 +0800[diff] [blame]89 3, /* MIXED1IO15 */
90 3, /* MIXED1IO16 */
91 3, /* MIXED1IO17 */
92 3, /* MIXED1IO18 */
93 3, /* MIXED1IO19 */
94 3, /* MIXED1IO20 */
Marek Vasut372f70d2015-08-10 21:21:07 +0200[diff] [blame]95 0, /* MIXED1IO21 */
96 0, /* MIXED2IO0 */
97 0, /* MIXED2IO1 */
98 0, /* MIXED2IO2 */
99 0, /* MIXED2IO3 */
100 0, /* MIXED2IO4 */
101 0, /* MIXED2IO5 */
102 0, /* MIXED2IO6 */
103 0, /* MIXED2IO7 */
104 0, /* GPLINMUX48 */
105 0, /* GPLINMUX49 */
106 0, /* GPLINMUX50 */
107 0, /* GPLINMUX51 */
108 0, /* GPLINMUX52 */
109 0, /* GPLINMUX53 */
110 0, /* GPLINMUX54 */
111 0, /* GPLINMUX55 */
112 0, /* GPLINMUX56 */
113 0, /* GPLINMUX57 */
114 0, /* GPLINMUX58 */
115 0, /* GPLINMUX59 */
116 0, /* GPLINMUX60 */
117 0, /* GPLINMUX61 */
118 0, /* GPLINMUX62 */
119 0, /* GPLINMUX63 */
120 0, /* GPLINMUX64 */
121 0, /* GPLINMUX65 */
122 0, /* GPLINMUX66 */
123 0, /* GPLINMUX67 */
124 0, /* GPLINMUX68 */
125 0, /* GPLINMUX69 */
126 0, /* GPLINMUX70 */
127 1, /* GPLMUX0 */
128 1, /* GPLMUX1 */
129 1, /* GPLMUX2 */
130 1, /* GPLMUX3 */
131 1, /* GPLMUX4 */
132 1, /* GPLMUX5 */
133 1, /* GPLMUX6 */
134 1, /* GPLMUX7 */
135 1, /* GPLMUX8 */
136 1, /* GPLMUX9 */
137 1, /* GPLMUX10 */
138 1, /* GPLMUX11 */
139 1, /* GPLMUX12 */
140 1, /* GPLMUX13 */
141 1, /* GPLMUX14 */
142 1, /* GPLMUX15 */
143 1, /* GPLMUX16 */
144 1, /* GPLMUX17 */
145 1, /* GPLMUX18 */
146 1, /* GPLMUX19 */
147 1, /* GPLMUX20 */
148 1, /* GPLMUX21 */
149 1, /* GPLMUX22 */
150 1, /* GPLMUX23 */
151 1, /* GPLMUX24 */
152 1, /* GPLMUX25 */
153 1, /* GPLMUX26 */
154 1, /* GPLMUX27 */
155 1, /* GPLMUX28 */
156 1, /* GPLMUX29 */
157 1, /* GPLMUX30 */
158 1, /* GPLMUX31 */
159 1, /* GPLMUX32 */
160 1, /* GPLMUX33 */
161 1, /* GPLMUX34 */
162 1, /* GPLMUX35 */
163 1, /* GPLMUX36 */
164 1, /* GPLMUX37 */
165 1, /* GPLMUX38 */
166 1, /* GPLMUX39 */
167 1, /* GPLMUX40 */
168 1, /* GPLMUX41 */
169 1, /* GPLMUX42 */
170 1, /* GPLMUX43 */
171 1, /* GPLMUX44 */
172 1, /* GPLMUX45 */
173 1, /* GPLMUX46 */
174 1, /* GPLMUX47 */
175 1, /* GPLMUX48 */
176 1, /* GPLMUX49 */
177 1, /* GPLMUX50 */
178 1, /* GPLMUX51 */
179 1, /* GPLMUX52 */
180 1, /* GPLMUX53 */
181 1, /* GPLMUX54 */
182 1, /* GPLMUX55 */
183 1, /* GPLMUX56 */
184 1, /* GPLMUX57 */
185 1, /* GPLMUX58 */
186 1, /* GPLMUX59 */
187 1, /* GPLMUX60 */
188 1, /* GPLMUX61 */
189 1, /* GPLMUX62 */
190 1, /* GPLMUX63 */
191 1, /* GPLMUX64 */
192 1, /* GPLMUX65 */
193 1, /* GPLMUX66 */
194 1, /* GPLMUX67 */
195 1, /* GPLMUX68 */
196 1, /* GPLMUX69 */
197 1, /* GPLMUX70 */
198 0, /* NANDUSEFPGA */
199 0, /* UART0USEFPGA */
200 0, /* RGMII1USEFPGA */
201 0, /* SPIS0USEFPGA */
202 0, /* CAN0USEFPGA */
203 0, /* I2C0USEFPGA */
204 0, /* SDMMCUSEFPGA */
205 0, /* QSPIUSEFPGA */
206 0, /* SPIS1USEFPGA */
207 0, /* RGMII0USEFPGA */
208 0, /* UART1USEFPGA */
209 0, /* CAN1USEFPGA */
210 0, /* USB1USEFPGA */
211 0, /* I2C3USEFPGA */
212 0, /* I2C2USEFPGA */
213 0, /* I2C1USEFPGA */
214 0, /* SPIM1USEFPGA */
215 0, /* USB0USEFPGA */
216 0 /* SPIM0USEFPGA */
217};
218#endif /* __SOCFPGA_PINMUX_CONFIG_H__ */