Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Bo Shen | 42aafb3 | 2012-07-05 17:21:46 +0000 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2012 Atmel Corporation |
| 4 | * |
| 5 | * Configuation settings for the AT91SAM9X5EK board. |
Bo Shen | 42aafb3 | 2012-07-05 17:21:46 +0000 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #ifndef __CONFIG_H__ |
| 9 | #define __CONFIG_H__ |
| 10 | |
Bo Shen | 42aafb3 | 2012-07-05 17:21:46 +0000 | [diff] [blame] | 11 | /* ARM asynchronous clock */ |
| 12 | #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 |
| 13 | #define CONFIG_SYS_AT91_MAIN_CLOCK 12000000 /* 12 MHz crystal */ |
Bo Shen | 42aafb3 | 2012-07-05 17:21:46 +0000 | [diff] [blame] | 14 | |
Bo Shen | 42aafb3 | 2012-07-05 17:21:46 +0000 | [diff] [blame] | 15 | #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ |
| 16 | #define CONFIG_SETUP_MEMORY_TAGS |
| 17 | #define CONFIG_INITRD_TAG |
| 18 | #define CONFIG_SKIP_LOWLEVEL_INIT |
Bo Shen | 42aafb3 | 2012-07-05 17:21:46 +0000 | [diff] [blame] | 19 | |
| 20 | /* general purpose I/O */ |
| 21 | #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ |
Bo Shen | 42aafb3 | 2012-07-05 17:21:46 +0000 | [diff] [blame] | 22 | |
Bo Shen | 42aafb3 | 2012-07-05 17:21:46 +0000 | [diff] [blame] | 23 | /* |
| 24 | * BOOTP options |
| 25 | */ |
| 26 | #define CONFIG_BOOTP_BOOTFILESIZE |
Bo Shen | 42aafb3 | 2012-07-05 17:21:46 +0000 | [diff] [blame] | 27 | |
| 28 | /* |
Tom Rini | ceed5d2 | 2017-05-12 22:33:27 -0400 | [diff] [blame] | 29 | * define CONFIG_USB_EHCI_HCD to enable USB Hi-Speed (aka 2.0) |
Richard Genoud | 1e34e83 | 2012-11-29 23:18:34 +0000 | [diff] [blame] | 30 | * NB: in this case, USB 1.1 devices won't be recognized. |
| 31 | */ |
| 32 | |
Bo Shen | 42aafb3 | 2012-07-05 17:21:46 +0000 | [diff] [blame] | 33 | /* SDRAM */ |
Bo Shen | 42aafb3 | 2012-07-05 17:21:46 +0000 | [diff] [blame] | 34 | #define CONFIG_SYS_SDRAM_BASE 0x20000000 |
| 35 | #define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 megs */ |
| 36 | |
| 37 | #define CONFIG_SYS_INIT_SP_ADDR \ |
Wenyou Yang | f345e28 | 2017-04-18 14:51:54 +0800 | [diff] [blame] | 38 | (CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE) |
Bo Shen | 42aafb3 | 2012-07-05 17:21:46 +0000 | [diff] [blame] | 39 | |
| 40 | /* DataFlash */ |
Bo Shen | 42aafb3 | 2012-07-05 17:21:46 +0000 | [diff] [blame] | 41 | |
Bo Shen | 42aafb3 | 2012-07-05 17:21:46 +0000 | [diff] [blame] | 42 | /* NAND flash */ |
| 43 | #ifdef CONFIG_CMD_NAND |
Bo Shen | 42aafb3 | 2012-07-05 17:21:46 +0000 | [diff] [blame] | 44 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
| 45 | #define CONFIG_SYS_NAND_BASE 0x40000000 |
| 46 | #define CONFIG_SYS_NAND_DBW_8 1 |
| 47 | /* our ALE is AD21 */ |
| 48 | #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) |
| 49 | /* our CLE is AD22 */ |
| 50 | #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) |
| 51 | #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4 |
| 52 | #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5 |
Tom Rini | 00448d2 | 2017-07-28 21:31:42 -0400 | [diff] [blame] | 53 | #endif |
| 54 | |
Richard Genoud | 1e34e83 | 2012-11-29 23:18:34 +0000 | [diff] [blame] | 55 | /* USB */ |
| 56 | #ifdef CONFIG_CMD_USB |
Tom Rini | ceed5d2 | 2017-05-12 22:33:27 -0400 | [diff] [blame] | 57 | #ifndef CONFIG_USB_EHCI_HCD |
Bo Shen | 4a985df | 2013-10-21 16:14:00 +0800 | [diff] [blame] | 58 | #define CONFIG_USB_ATMEL |
| 59 | #define CONFIG_USB_ATMEL_CLK_SEL_UPLL |
Richard Genoud | 1e34e83 | 2012-11-29 23:18:34 +0000 | [diff] [blame] | 60 | #define CONFIG_USB_OHCI_NEW |
| 61 | #define CONFIG_SYS_USB_OHCI_CPU_INIT |
| 62 | #define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI |
| 63 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9x5" |
| 64 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3 |
| 65 | #endif |
Richard Genoud | 1e34e83 | 2012-11-29 23:18:34 +0000 | [diff] [blame] | 66 | #endif |
| 67 | |
Bo Shen | 42aafb3 | 2012-07-05 17:21:46 +0000 | [diff] [blame] | 68 | #define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */ |
| 69 | |
| 70 | #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE |
| 71 | #define CONFIG_SYS_MEMTEST_END 0x26e00000 |
| 72 | |
Wenyou Yang | e035ea7 | 2017-09-14 11:07:44 +0800 | [diff] [blame] | 73 | #ifdef CONFIG_NAND_BOOT |
Bo Shen | 42aafb3 | 2012-07-05 17:21:46 +0000 | [diff] [blame] | 74 | /* bootstrap + u-boot + env + linux in nandflash */ |
Nicolas Ferre | 6492244 | 2018-05-09 10:30:25 +0300 | [diff] [blame] | 75 | #define CONFIG_ENV_OFFSET 0x140000 |
Bo Shen | 42aafb3 | 2012-07-05 17:21:46 +0000 | [diff] [blame] | 76 | #define CONFIG_ENV_OFFSET_REDUND 0x100000 |
| 77 | #define CONFIG_ENV_SIZE 0x20000 /* 1 sector = 128 kB */ |
| 78 | #define CONFIG_BOOTCOMMAND "nand read " \ |
Eugen.Hristev@microchip.com | dc9a493 | 2018-10-23 07:41:33 +0000 | [diff] [blame] | 79 | "0x22000000 0x200000 0x600000; " \ |
| 80 | "nand read 0x21000000 0x180000 0x20000; " \ |
| 81 | "bootz 0x22000000 - 0x21000000" |
Wenyou Yang | e035ea7 | 2017-09-14 11:07:44 +0800 | [diff] [blame] | 82 | #elif defined(CONFIG_SPI_BOOT) |
Bo Shen | 4a73e58 | 2012-08-19 20:32:24 +0000 | [diff] [blame] | 83 | /* bootstrap + u-boot + env + linux in spi flash */ |
Bo Shen | 4a73e58 | 2012-08-19 20:32:24 +0000 | [diff] [blame] | 84 | #define CONFIG_ENV_OFFSET 0x5000 |
| 85 | #define CONFIG_ENV_SIZE 0x3000 |
| 86 | #define CONFIG_ENV_SECT_SIZE 0x1000 |
Bo Shen | 4a73e58 | 2012-08-19 20:32:24 +0000 | [diff] [blame] | 87 | #define CONFIG_BOOTCOMMAND "sf probe 0; " \ |
| 88 | "sf read 0x22000000 0x100000 0x300000; " \ |
| 89 | "bootm 0x22000000" |
Bo Shen | 0a9f8ac | 2012-12-06 21:37:04 +0000 | [diff] [blame] | 90 | #elif defined(CONFIG_SYS_USE_DATAFLASH) |
| 91 | /* bootstrap + u-boot + env + linux in data flash */ |
Bo Shen | 0a9f8ac | 2012-12-06 21:37:04 +0000 | [diff] [blame] | 92 | #define CONFIG_ENV_OFFSET 0x4200 |
| 93 | #define CONFIG_ENV_SIZE 0x4200 |
| 94 | #define CONFIG_ENV_SECT_SIZE 0x210 |
Bo Shen | 0a9f8ac | 2012-12-06 21:37:04 +0000 | [diff] [blame] | 95 | #define CONFIG_BOOTCOMMAND "sf probe 0; " \ |
| 96 | "sf read 0x22000000 0x84000 0x294000; " \ |
| 97 | "bootm 0x22000000" |
Wenyou Yang | e035ea7 | 2017-09-14 11:07:44 +0800 | [diff] [blame] | 98 | #else /* CONFIG_SD_BOOT */ |
Wu, Josh | 9d68189 | 2012-11-02 00:17:27 +0000 | [diff] [blame] | 99 | /* bootstrap + u-boot + env + linux in mmc */ |
Wu, Josh | df0ef74 | 2015-01-20 10:33:33 +0800 | [diff] [blame] | 100 | #define CONFIG_ENV_SIZE 0x4000 |
Bo Shen | 42aafb3 | 2012-07-05 17:21:46 +0000 | [diff] [blame] | 101 | #endif |
| 102 | |
Bo Shen | 42aafb3 | 2012-07-05 17:21:46 +0000 | [diff] [blame] | 103 | /* |
| 104 | * Size of malloc() pool |
| 105 | */ |
| 106 | #define CONFIG_SYS_MALLOC_LEN (512 * 1024 + 0x1000) |
| 107 | |
Bo Shen | 9a3b1fe | 2015-03-27 14:23:35 +0800 | [diff] [blame] | 108 | /* SPL */ |
Bo Shen | 9a3b1fe | 2015-03-27 14:23:35 +0800 | [diff] [blame] | 109 | #define CONFIG_SPL_MAX_SIZE 0x6000 |
| 110 | #define CONFIG_SPL_STACK 0x308000 |
| 111 | |
| 112 | #define CONFIG_SPL_BSS_START_ADDR 0x20000000 |
| 113 | #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 |
| 114 | #define CONFIG_SYS_SPL_MALLOC_START 0x20080000 |
| 115 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 |
| 116 | |
Bo Shen | 9a3b1fe | 2015-03-27 14:23:35 +0800 | [diff] [blame] | 117 | #define CONFIG_SYS_MONITOR_LEN (512 << 10) |
| 118 | |
| 119 | #define CONFIG_SYS_MASTER_CLOCK 132096000 |
| 120 | #define CONFIG_SYS_AT91_PLLA 0x20c73f03 |
| 121 | #define CONFIG_SYS_MCKR 0x1301 |
| 122 | #define CONFIG_SYS_MCKR_CSS 0x1302 |
| 123 | |
Wenyou Yang | e035ea7 | 2017-09-14 11:07:44 +0800 | [diff] [blame] | 124 | #ifdef CONFIG_SD_BOOT |
Bo Shen | 9a3b1fe | 2015-03-27 14:23:35 +0800 | [diff] [blame] | 125 | #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 |
| 126 | #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" |
Bo Shen | 9a3b1fe | 2015-03-27 14:23:35 +0800 | [diff] [blame] | 127 | |
Wenyou Yang | e035ea7 | 2017-09-14 11:07:44 +0800 | [diff] [blame] | 128 | #elif CONFIG_SPI_BOOT |
Wenyou Yang | e035ea7 | 2017-09-14 11:07:44 +0800 | [diff] [blame] | 129 | #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x8400 |
| 130 | |
| 131 | #elif CONFIG_NAND_BOOT |
Bo Shen | 9a3b1fe | 2015-03-27 14:23:35 +0800 | [diff] [blame] | 132 | #define CONFIG_SPL_NAND_DRIVERS |
| 133 | #define CONFIG_SPL_NAND_BASE |
Wenyou Yang | e035ea7 | 2017-09-14 11:07:44 +0800 | [diff] [blame] | 134 | #endif |
Bo Shen | 9a3b1fe | 2015-03-27 14:23:35 +0800 | [diff] [blame] | 135 | #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000 |
| 136 | #define CONFIG_SYS_NAND_5_ADDR_CYCLE |
| 137 | #define CONFIG_SYS_NAND_PAGE_SIZE 0x800 |
| 138 | #define CONFIG_SYS_NAND_PAGE_COUNT 64 |
| 139 | #define CONFIG_SYS_NAND_OOBSIZE 64 |
| 140 | #define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000 |
| 141 | #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0x0 |
Bo Shen | 9a3b1fe | 2015-03-27 14:23:35 +0800 | [diff] [blame] | 142 | |
Bo Shen | 42aafb3 | 2012-07-05 17:21:46 +0000 | [diff] [blame] | 143 | #endif |