Tom Rini | 10e4779 | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2015 Freescale Semiconductor |
Yangbo Lu | bb32e68 | 2021-06-03 10:51:19 +0800 | [diff] [blame] | 4 | * Copyright 2019-2021 NXP |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef __LS1043A_COMMON_H |
| 8 | #define __LS1043A_COMMON_H |
| 9 | |
Sumit Garg | 2a2857b | 2017-03-30 09:52:38 +0530 | [diff] [blame] | 10 | /* SPL build */ |
| 11 | #ifdef CONFIG_SPL_BUILD |
| 12 | #define SPL_NO_FMAN |
| 13 | #define SPL_NO_DSPI |
| 14 | #define SPL_NO_PCIE |
| 15 | #define SPL_NO_ENV |
| 16 | #define SPL_NO_MISC |
| 17 | #define SPL_NO_USB |
| 18 | #define SPL_NO_SATA |
| 19 | #define SPL_NO_QE |
| 20 | #define SPL_NO_EEPROM |
| 21 | #endif |
| 22 | #if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_NAND_BOOT)) |
| 23 | #define SPL_NO_MMC |
| 24 | #endif |
Yangbo Lu | 83c4ece | 2017-09-15 09:51:58 +0800 | [diff] [blame] | 25 | #if (defined(CONFIG_SPL_BUILD) && defined(CONFIG_SD_BOOT_QSPI)) |
Sumit Garg | 2a2857b | 2017-03-30 09:52:38 +0530 | [diff] [blame] | 26 | #define SPL_NO_IFC |
| 27 | #endif |
| 28 | |
Bharat Bhushan | 882b632 | 2017-03-22 12:06:27 +0530 | [diff] [blame] | 29 | #include <asm/arch/stream_id_lsch2.h> |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 30 | #include <asm/arch/config.h> |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 31 | |
| 32 | /* Link Definitions */ |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 33 | |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 34 | #define CONFIG_VERY_BIG_RAM |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 35 | #define CFG_SYS_DDR_SDRAM_BASE 0x80000000 |
Tom Rini | 376b88a | 2022-10-28 20:27:13 -0400 | [diff] [blame] | 36 | #define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 37 | #define CFG_SYS_SDRAM_BASE CFG_SYS_DDR_SDRAM_BASE |
| 38 | #define CFG_SYS_DDR_BLOCK2_BASE 0x880000000ULL |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 39 | |
Michael Walle | f056e0f | 2020-06-01 21:53:26 +0200 | [diff] [blame] | 40 | #define CPU_RELEASE_ADDR secondary_boot_addr |
Hou Zhiqiang | c7098fa | 2015-10-26 19:47:57 +0800 | [diff] [blame] | 41 | |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 42 | /* Serial Port */ |
Tom Rini | df6a215 | 2022-11-16 13:10:28 -0500 | [diff] [blame] | 43 | #define CFG_SYS_NS16550_CLK (get_serial_clock()) |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 44 | |
Gong Qianyu | f671f6c | 2015-10-26 19:47:56 +0800 | [diff] [blame] | 45 | /* SD boot SPL */ |
| 46 | #ifdef CONFIG_SD_BOOT |
Udit Agarwal | 22ec238 | 2019-11-07 16:11:32 +0000 | [diff] [blame] | 47 | #ifdef CONFIG_NXP_ESBC |
Ruchika Gupta | d6b8920 | 2017-04-17 18:07:17 +0530 | [diff] [blame] | 48 | #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) |
| 49 | /* |
| 50 | * HDR would be appended at end of image and copied to DDR along |
| 51 | * with U-Boot image. Here u-boot max. size is 512K. So if binary |
| 52 | * size increases then increase this size in case of secure boot as |
| 53 | * it uses raw u-boot image instead of fit image. |
| 54 | */ |
Udit Agarwal | 22ec238 | 2019-11-07 16:11:32 +0000 | [diff] [blame] | 55 | #endif /* ifdef CONFIG_NXP_ESBC */ |
Gong Qianyu | f671f6c | 2015-10-26 19:47:56 +0800 | [diff] [blame] | 56 | #endif |
| 57 | |
Gong Qianyu | 8168a0f | 2015-10-26 19:47:53 +0800 | [diff] [blame] | 58 | /* NAND SPL */ |
| 59 | #ifdef CONFIG_NAND_BOOT |
Tom Rini | b421349 | 2022-11-12 17:36:51 -0500 | [diff] [blame] | 60 | #define CFG_SYS_NAND_U_BOOT_DST CONFIG_TEXT_BASE |
| 61 | #define CFG_SYS_NAND_U_BOOT_START CONFIG_TEXT_BASE |
Ruchika Gupta | ba68875 | 2017-04-17 18:07:18 +0530 | [diff] [blame] | 62 | |
Udit Agarwal | 22ec238 | 2019-11-07 16:11:32 +0000 | [diff] [blame] | 63 | #ifdef CONFIG_NXP_ESBC |
Ruchika Gupta | ba68875 | 2017-04-17 18:07:18 +0530 | [diff] [blame] | 64 | #define CONFIG_U_BOOT_HDR_SIZE (16 << 10) |
Udit Agarwal | 22ec238 | 2019-11-07 16:11:32 +0000 | [diff] [blame] | 65 | #endif /* ifdef CONFIG_NXP_ESBC */ |
Ruchika Gupta | ba68875 | 2017-04-17 18:07:18 +0530 | [diff] [blame] | 66 | |
| 67 | #ifdef CONFIG_U_BOOT_HDR_SIZE |
| 68 | /* |
| 69 | * HDR would be appended at end of image and copied to DDR along |
| 70 | * with U-Boot image. Here u-boot max. size is 512K. So if binary |
| 71 | * size increases then increase this size in case of secure boot as |
| 72 | * it uses raw u-boot image instead of fit image. |
| 73 | */ |
Ruchika Gupta | ba68875 | 2017-04-17 18:07:18 +0530 | [diff] [blame] | 74 | #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */ |
| 75 | |
Gong Qianyu | 8168a0f | 2015-10-26 19:47:53 +0800 | [diff] [blame] | 76 | #endif |
| 77 | |
Biwen Li | 46de400 | 2021-02-05 19:01:56 +0800 | [diff] [blame] | 78 | /* GPIO */ |
Biwen Li | 46de400 | 2021-02-05 19:01:56 +0800 | [diff] [blame] | 79 | |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 80 | /* IFC */ |
Sumit Garg | 2a2857b | 2017-03-30 09:52:38 +0530 | [diff] [blame] | 81 | #ifndef SPL_NO_IFC |
Rajesh Bhagat | b89aed4 | 2018-11-05 18:02:44 +0000 | [diff] [blame] | 82 | #if defined(CONFIG_TFABOOT) || \ |
| 83 | (!defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)) |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 84 | /* |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 85 | * CFG_SYS_FLASH_BASE has the final address (core view) |
| 86 | * CFG_SYS_FLASH_BASE_PHYS has the final address (IFC view) |
| 87 | * CFG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address |
Simon Glass | 72cc538 | 2022-10-20 18:22:39 -0600 | [diff] [blame] | 88 | * CONFIG_TEXT_BASE is linked to 0x60000000 for booting |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 89 | */ |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 90 | #define CFG_SYS_FLASH_BASE 0x60000000 |
| 91 | #define CFG_SYS_FLASH_BASE_PHYS CFG_SYS_FLASH_BASE |
| 92 | #define CFG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000 |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 93 | |
Masahiro Yamada | 8cea9b5 | 2017-02-11 22:43:54 +0900 | [diff] [blame] | 94 | #ifdef CONFIG_MTD_NOR_FLASH |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 95 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ |
| 96 | #endif |
Gong Qianyu | 760df89 | 2016-01-25 15:16:06 +0800 | [diff] [blame] | 97 | #endif |
Sumit Garg | 2a2857b | 2017-03-30 09:52:38 +0530 | [diff] [blame] | 98 | #endif |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 99 | |
| 100 | /* I2C */ |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 101 | |
Gong Qianyu | 51c18dc | 2016-01-25 15:16:05 +0800 | [diff] [blame] | 102 | /* DSPI */ |
Gong Qianyu | 51c18dc | 2016-01-25 15:16:05 +0800 | [diff] [blame] | 103 | |
Shaohui Xie | 0464326 | 2015-10-26 19:47:54 +0800 | [diff] [blame] | 104 | /* FMan ucode */ |
Sumit Garg | 2a2857b | 2017-03-30 09:52:38 +0530 | [diff] [blame] | 105 | #ifndef SPL_NO_FMAN |
Shaohui Xie | 0464326 | 2015-10-26 19:47:54 +0800 | [diff] [blame] | 106 | #ifdef CONFIG_SYS_DPAA_FMAN |
Tom Rini | 6a5dccc | 2022-11-16 13:10:41 -0500 | [diff] [blame] | 107 | #define CFG_SYS_FM_MURAM_SIZE 0x60000 |
Shaohui Xie | 0464326 | 2015-10-26 19:47:54 +0800 | [diff] [blame] | 108 | #endif |
Sumit Garg | 2a2857b | 2017-03-30 09:52:38 +0530 | [diff] [blame] | 109 | #endif |
Shaohui Xie | 0464326 | 2015-10-26 19:47:54 +0800 | [diff] [blame] | 110 | |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 111 | /* Miscellaneous configurable options */ |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 112 | |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 113 | #define HWCONFIG_BUFFER_SIZE 128 |
| 114 | |
Sumit Garg | 2a2857b | 2017-03-30 09:52:38 +0530 | [diff] [blame] | 115 | #ifndef SPL_NO_MISC |
Shengzhou Liu | 9d66254 | 2017-06-08 15:59:48 +0800 | [diff] [blame] | 116 | #define BOOT_TARGET_DEVICES(func) \ |
| 117 | func(MMC, mmc, 0) \ |
Mian Yousaf Kaukab | 6519df7 | 2019-01-29 16:38:40 +0100 | [diff] [blame] | 118 | func(USB, usb, 0) \ |
| 119 | func(DHCP, dhcp, na) |
Shengzhou Liu | 9d66254 | 2017-06-08 15:59:48 +0800 | [diff] [blame] | 120 | #include <config_distro_bootcmd.h> |
Shengzhou Liu | 9d66254 | 2017-06-08 15:59:48 +0800 | [diff] [blame] | 121 | |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 122 | /* Initial environment variables */ |
| 123 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 124 | "hwconfig=fsl_ddr:bank_intlv=auto\0" \ |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 125 | "fdt_high=0xffffffffffffffff\0" \ |
| 126 | "initrd_high=0xffffffffffffffff\0" \ |
Vinitha Pillai-B57223 | 0c6e10a | 2017-11-22 10:38:35 +0530 | [diff] [blame] | 127 | "kernel_addr=0x61000000\0" \ |
Shengzhou Liu | 9d66254 | 2017-06-08 15:59:48 +0800 | [diff] [blame] | 128 | "scriptaddr=0x80000000\0" \ |
Sumit Garg | 9cbcc4d | 2017-06-05 23:51:51 +0530 | [diff] [blame] | 129 | "scripthdraddr=0x80080000\0" \ |
Shengzhou Liu | 9d66254 | 2017-06-08 15:59:48 +0800 | [diff] [blame] | 130 | "fdtheader_addr_r=0x80100000\0" \ |
| 131 | "kernelheader_addr_r=0x80200000\0" \ |
| 132 | "kernel_addr_r=0x81000000\0" \ |
Wen He | 335b386 | 2018-11-20 16:55:25 +0800 | [diff] [blame] | 133 | "kernel_start=0x1000000\0" \ |
| 134 | "kernelheader_start=0x800000\0" \ |
Shengzhou Liu | 9d66254 | 2017-06-08 15:59:48 +0800 | [diff] [blame] | 135 | "fdt_addr_r=0x90000000\0" \ |
| 136 | "load_addr=0xa0000000\0" \ |
Manish Tomar | 8d38801 | 2020-11-05 14:08:55 +0530 | [diff] [blame] | 137 | "kernelheader_addr=0x60600000\0" \ |
Qianyu Gong | 2758edf | 2016-03-15 16:35:57 +0800 | [diff] [blame] | 138 | "kernel_size=0x2800000\0" \ |
Vinitha Pillai-B57223 | 0c6e10a | 2017-11-22 10:38:35 +0530 | [diff] [blame] | 139 | "kernelheader_size=0x40000\0" \ |
Shengzhou Liu | 4286275 | 2017-11-09 17:57:55 +0800 | [diff] [blame] | 140 | "kernel_addr_sd=0x8000\0" \ |
| 141 | "kernel_size_sd=0x14000\0" \ |
Manish Tomar | 8d38801 | 2020-11-05 14:08:55 +0530 | [diff] [blame] | 142 | "kernelhdr_addr_sd=0x3000\0" \ |
Vinitha Pillai-B57223 | 0c6e10a | 2017-11-22 10:38:35 +0530 | [diff] [blame] | 143 | "kernelhdr_size_sd=0x10\0" \ |
Shengzhou Liu | 9d66254 | 2017-06-08 15:59:48 +0800 | [diff] [blame] | 144 | "console=ttyS0,115200\0" \ |
York Sun | f7eed6b | 2017-09-28 08:42:16 -0700 | [diff] [blame] | 145 | "boot_os=y\0" \ |
Shengzhou Liu | 9d66254 | 2017-06-08 15:59:48 +0800 | [diff] [blame] | 146 | BOOTENV \ |
| 147 | "boot_scripts=ls1043ardb_boot.scr\0" \ |
Sumit Garg | 9cbcc4d | 2017-06-05 23:51:51 +0530 | [diff] [blame] | 148 | "boot_script_hdr=hdr_ls1043ardb_bs.out\0" \ |
Shengzhou Liu | 9d66254 | 2017-06-08 15:59:48 +0800 | [diff] [blame] | 149 | "scan_dev_for_boot_part=" \ |
| 150 | "part list ${devtype} ${devnum} devplist; " \ |
| 151 | "env exists devplist || setenv devplist 1; " \ |
| 152 | "for distro_bootpart in ${devplist}; do " \ |
| 153 | "if fstype ${devtype} " \ |
| 154 | "${devnum}:${distro_bootpart} " \ |
| 155 | "bootfstype; then " \ |
| 156 | "run scan_dev_for_boot; " \ |
| 157 | "fi; " \ |
| 158 | "done\0" \ |
Sumit Garg | 9cbcc4d | 2017-06-05 23:51:51 +0530 | [diff] [blame] | 159 | "boot_a_script=" \ |
| 160 | "load ${devtype} ${devnum}:${distro_bootpart} " \ |
| 161 | "${scriptaddr} ${prefix}${script}; " \ |
| 162 | "env exists secureboot && load ${devtype} " \ |
| 163 | "${devnum}:${distro_bootpart} " \ |
Vinitha V Pillai | 25355ec | 2019-04-23 05:52:17 +0000 | [diff] [blame] | 164 | "${scripthdraddr} ${prefix}${boot_script_hdr}; " \ |
| 165 | "env exists secureboot " \ |
Sumit Garg | 9cbcc4d | 2017-06-05 23:51:51 +0530 | [diff] [blame] | 166 | "&& esbc_validate ${scripthdraddr};" \ |
| 167 | "source ${scriptaddr}\0" \ |
Shengzhou Liu | 9d66254 | 2017-06-08 15:59:48 +0800 | [diff] [blame] | 168 | "qspi_bootcmd=echo Trying load from qspi..;" \ |
| 169 | "sf probe && sf read $load_addr " \ |
Wen He | cabe55c | 2019-11-14 15:08:15 +0800 | [diff] [blame] | 170 | "$kernel_start $kernel_size; env exists secureboot " \ |
| 171 | "&& sf read $kernelheader_addr_r $kernelheader_start " \ |
Vinitha Pillai-B57223 | 0c6e10a | 2017-11-22 10:38:35 +0530 | [diff] [blame] | 172 | "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ |
| 173 | "bootm $load_addr#$board\0" \ |
Shengzhou Liu | 9d66254 | 2017-06-08 15:59:48 +0800 | [diff] [blame] | 174 | "nor_bootcmd=echo Trying load from nor..;" \ |
| 175 | "cp.b $kernel_addr $load_addr " \ |
Vinitha Pillai-B57223 | 0c6e10a | 2017-11-22 10:38:35 +0530 | [diff] [blame] | 176 | "$kernel_size; env exists secureboot " \ |
| 177 | "&& cp.b $kernelheader_addr $kernelheader_addr_r " \ |
| 178 | "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ |
| 179 | "bootm $load_addr#$board\0" \ |
Wen He | 335b386 | 2018-11-20 16:55:25 +0800 | [diff] [blame] | 180 | "nand_bootcmd=echo Trying load from NAND..;" \ |
| 181 | "nand info; nand read $load_addr " \ |
| 182 | "$kernel_start $kernel_size; env exists secureboot " \ |
| 183 | "&& nand read $kernelheader_addr_r $kernelheader_start " \ |
| 184 | "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \ |
| 185 | "bootm $load_addr#$board\0" \ |
Shengzhou Liu | 4286275 | 2017-11-09 17:57:55 +0800 | [diff] [blame] | 186 | "sd_bootcmd=echo Trying load from SD ..;" \ |
| 187 | "mmcinfo; mmc read $load_addr " \ |
| 188 | "$kernel_addr_sd $kernel_size_sd && " \ |
Vinitha Pillai-B57223 | 0c6e10a | 2017-11-22 10:38:35 +0530 | [diff] [blame] | 189 | "env exists secureboot && mmc read $kernelheader_addr_r " \ |
| 190 | "$kernelhdr_addr_sd $kernelhdr_size_sd " \ |
| 191 | " && esbc_validate ${kernelheader_addr_r};" \ |
Shengzhou Liu | 4286275 | 2017-11-09 17:57:55 +0800 | [diff] [blame] | 192 | "bootm $load_addr#$board\0" |
| 193 | |
Wenbin Song | 1738ca7 | 2016-07-21 18:55:16 +0800 | [diff] [blame] | 194 | |
Rajesh Bhagat | b89aed4 | 2018-11-05 18:02:44 +0000 | [diff] [blame] | 195 | #ifdef CONFIG_TFABOOT |
| 196 | #define QSPI_NOR_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd; " \ |
| 197 | "env exists secureboot && esbc_halt;" |
| 198 | #define SD_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; " \ |
| 199 | "env exists secureboot && esbc_halt;" |
| 200 | #define IFC_NOR_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd; " \ |
| 201 | "env exists secureboot && esbc_halt;" |
Pankit Garg | 6921072 | 2018-12-27 04:37:53 +0000 | [diff] [blame] | 202 | #define IFC_NAND_BOOTCOMMAND "run distro_bootcmd; run nand_bootcmd; " \ |
| 203 | "env exists secureboot && esbc_halt;" |
Sumit Garg | 2a2857b | 2017-03-30 09:52:38 +0530 | [diff] [blame] | 204 | #endif |
Rajesh Bhagat | b89aed4 | 2018-11-05 18:02:44 +0000 | [diff] [blame] | 205 | #endif |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 206 | |
Simon Glass | 89e0a3a | 2017-05-17 08:23:10 -0600 | [diff] [blame] | 207 | #include <asm/arch/soc.h> |
| 208 | |
Mingkai Hu | eee86ff | 2015-10-26 19:47:52 +0800 | [diff] [blame] | 209 | #endif /* __LS1043A_COMMON_H */ |