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Tom Rini10e47792018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Matthew Fettke9f3b3bb2008-01-24 14:02:32 -06002/*
3 * Configuation settings for the Motorola MC5275EVB board.
4 *
5 * By Arthur Shipkowski <art@videon-central.com>
6 * Copyright (C) 2005 Videon Central, Inc.
7 *
8 * Based off of M5272C3 board code by Josef Baumgartner
9 * <josef.baumgartner@telex.de>
Matthew Fettke9f3b3bb2008-01-24 14:02:32 -060010 */
11
12/*
13 * board/config.h - configuration options, board specific
14 */
15
16#ifndef _M5275EVB_H
17#define _M5275EVB_H
18
19/*
20 * High Level Configuration Options
21 * (easy to change)
22 */
Matthew Fettke9f3b3bb2008-01-24 14:02:32 -060023
Tom Rini6a5dccc2022-11-16 13:10:41 -050024#define CFG_SYS_UART_PORT (0)
Matthew Fettke9f3b3bb2008-01-24 14:02:32 -060025
26/* Configuration for environment
27 * Environment is embedded in u-boot in the second sector of the flash
28 */
Matthew Fettke9f3b3bb2008-01-24 14:02:32 -060029
angelo@sysam.it6312a952015-03-29 22:54:16 +020030#define LDS_BOARD_TEXT \
Simon Glass547cb402017-08-03 12:21:49 -060031 . = DEFINED(env_offset) ? env_offset : .; \
32 env/embedded.o(.text);
angelo@sysam.it6312a952015-03-29 22:54:16 +020033
Matthew Fettke9f3b3bb2008-01-24 14:02:32 -060034/* Available command configuration */
Matthew Fettke9f3b3bb2008-01-24 14:02:32 -060035
Matthew Fettke9f3b3bb2008-01-24 14:02:32 -060036/* I2C */
Tom Rini6a5dccc2022-11-16 13:10:41 -050037#define CFG_SYS_I2C_PINMUX_REG (gpio_reg->par_feci2c)
38#define CFG_SYS_I2C_PINMUX_CLR (0xFFF0)
39#define CFG_SYS_I2C_PINMUX_SET (0x000F)
Matthew Fettke9f3b3bb2008-01-24 14:02:32 -060040
TsiChung Liew23cc28c2010-03-10 16:33:03 -060041#ifdef CONFIG_MCFFEC
TsiChung Liew23cc28c2010-03-10 16:33:03 -060042# define CONFIG_OVERWRITE_ETHADDR_ONCE
43#endif /* FEC_ENET */
44
45#define CONFIG_EXTRA_ENV_SETTINGS \
46 "netdev=eth0\0" \
47 "loadaddr=10000\0" \
48 "uboot=u-boot.bin\0" \
49 "load=tftp ${loadaddr} ${uboot}\0" \
50 "upd=run load; run prog\0" \
51 "prog=prot off ffe00000 ffe3ffff;" \
52 "era ffe00000 ffe3ffff;" \
53 "cp.b ${loadaddr} ffe00000 ${filesize};"\
54 "save\0" \
55 ""
56
Tom Rini6a5dccc2022-11-16 13:10:41 -050057#define CFG_SYS_CLK 150000000
Matthew Fettke9f3b3bb2008-01-24 14:02:32 -060058
59/*
60 * Low Level Configuration Settings
61 * (address mappings, register initial values, etc.)
62 * You should know what you are doing if you make changes here.
63 */
64
Tom Rini6a5dccc2022-11-16 13:10:41 -050065#define CFG_SYS_MBAR 0x40000000
Matthew Fettke9f3b3bb2008-01-24 14:02:32 -060066
67/*-----------------------------------------------------------------------
68 * Definitions for initial stack pointer and data area (in DPRAM)
69 */
Tom Rini6a5dccc2022-11-16 13:10:41 -050070#define CFG_SYS_INIT_RAM_ADDR 0x20000000
71#define CFG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
Matthew Fettke9f3b3bb2008-01-24 14:02:32 -060072
73/*-----------------------------------------------------------------------
74 * Start addresses for the final memory configuration
75 * (Set up by the startup code)
Tom Rinibb4dd962022-11-16 13:10:37 -050076 * Please note that CFG_SYS_SDRAM_BASE _must_ start at 0
Matthew Fettke9f3b3bb2008-01-24 14:02:32 -060077 */
Tom Rinibb4dd962022-11-16 13:10:37 -050078#define CFG_SYS_SDRAM_BASE 0x00000000
79#define CFG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
Tom Rini6a5dccc2022-11-16 13:10:41 -050080#define CFG_SYS_FLASH_BASE CFG_SYS_CS0_BASE
Matthew Fettke9f3b3bb2008-01-24 14:02:32 -060081
Matthew Fettke9f3b3bb2008-01-24 14:02:32 -060082/*
83 * For booting Linux, the board info and command line data
84 * have to be in the first 8 MB of memory, since this is
85 * the maximum mapped by the Linux kernel during initialization ??
86 */
Tom Rini6a5dccc2022-11-16 13:10:41 -050087#define CFG_SYS_BOOTMAPSZ (CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
Matthew Fettke9f3b3bb2008-01-24 14:02:32 -060088
89/*-----------------------------------------------------------------------
90 * FLASH organization
91 */
Matthew Fettke9f3b3bb2008-01-24 14:02:32 -060092
Tom Rini6a5dccc2022-11-16 13:10:41 -050093#define CFG_SYS_FLASH_SIZE 0x200000
Matthew Fettke9f3b3bb2008-01-24 14:02:32 -060094
95/*-----------------------------------------------------------------------
96 * Cache Configuration
97 */
Matthew Fettke9f3b3bb2008-01-24 14:02:32 -060098
Tom Rini6a5dccc2022-11-16 13:10:41 -050099#define ICACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
100 CFG_SYS_INIT_RAM_SIZE - 8)
101#define DCACHE_STATUS (CFG_SYS_INIT_RAM_ADDR + \
102 CFG_SYS_INIT_RAM_SIZE - 4)
103#define CFG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
104#define CFG_SYS_CACHE_ACR0 (CFG_SYS_SDRAM_BASE | \
Tom Rinibb4dd962022-11-16 13:10:37 -0500105 CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600106 CF_ACR_EN | CF_ACR_SM_ALL)
Tom Rini6a5dccc2022-11-16 13:10:41 -0500107#define CFG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
TsiChung Liew0ee47d42010-03-11 22:12:53 -0600108 CF_CACR_DISD | CF_CACR_INVI | \
109 CF_CACR_CEIB | CF_CACR_DCM | \
110 CF_CACR_EUSP)
111
Matthew Fettke9f3b3bb2008-01-24 14:02:32 -0600112/*-----------------------------------------------------------------------
113 * Memory bank definitions
114 */
Tom Rini6a5dccc2022-11-16 13:10:41 -0500115#define CFG_SYS_CS0_BASE 0xffe00000
116#define CFG_SYS_CS0_CTRL 0x00001980
117#define CFG_SYS_CS0_MASK 0x001F0001
Matthew Fettke9f3b3bb2008-01-24 14:02:32 -0600118
Tom Rini6a5dccc2022-11-16 13:10:41 -0500119#define CFG_SYS_CS1_BASE 0x30000000
120#define CFG_SYS_CS1_CTRL 0x00001900
121#define CFG_SYS_CS1_MASK 0x00070001
Matthew Fettke9f3b3bb2008-01-24 14:02:32 -0600122
Matthew Fettke9f3b3bb2008-01-24 14:02:32 -0600123#endif /* _M5275EVB_H */