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git01.mediatek.com / filogic / uboot / 36c8fe0f354b1f28b3f76f15145bb6064cd2aace / . / arch / arm / dts / ast2600.dtsi
blob: beabcf14f81d4c6104cd934169f1b882df1ed82b [file] [log] [blame]
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2#include <dt-bindings/interrupt-controller/arm-gic.h>
3#include "skeleton.dtsi"
4
5/ {
6 model = "Aspeed BMC";
7 compatible = "aspeed,ast2600";
8 #address-cells = <1>;
9 #size-cells = <1>;
10 interrupt-parent = <&gic>;
11
12 aliases {
13 i2c0 = &i2c0;
14 i2c1 = &i2c1;
15 i2c2 = &i2c2;
16 i2c3 = &i2c3;
17 i2c4 = &i2c4;
18 i2c5 = &i2c5;
19 i2c6 = &i2c6;
20 i2c7 = &i2c7;
21 i2c8 = &i2c8;
22 i2c9 = &i2c9;
23 i2c10 = &i2c10;
24 i2c11 = &i2c11;
25 i2c12 = &i2c12;
26 i2c13 = &i2c13;
27 i2c14 = &i2c14;
28 i2c15 = &i2c15;
29 serial0 = &uart1;
30 serial1 = &uart2;
31 serial2 = &uart3;
32 serial3 = &uart4;
33 serial4 = &uart5;
34 serial5 = &uart6;
35 serial6 = &uart7;
36 serial7 = &uart8;
37 serial8 = &uart9;
38 serial9 = &uart10;
39 serial10 = &uart11;
40 serial11 = &uart12;
41 serial12 = &uart13;
42 };
43
44 cpus {
45 #address-cells = <1>;
46 #size-cells = <0>;
47 enable-method = "aspeed,ast2600-smp";
48
49 cpu@0 {
50 compatible = "arm,cortex-a7";
51 device_type = "cpu";
52 reg = <0xf00>;
53 };
54
55 cpu@1 {
56 compatible = "arm,cortex-a7";
57 device_type = "cpu";
58 reg = <0xf01>;
59 };
60
61 };
62
63 timer {
64 compatible = "arm,armv7-timer";
65 interrupt-parent = <&gic>;
66 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
67 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
68 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
69 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
70 };
71
72 reserved-memory {
73 #address-cells = <1>;
74 #size-cells = <1>;
75 ranges;
76
77 gfx_memory: framebuffer {
78 size = <0x01000000>;
79 alignment = <0x01000000>;
80 compatible = "shared-dma-pool";
81 reusable;
82 };
83
84 video_memory: video {
85 size = <0x04000000>;
86 alignment = <0x01000000>;
87 compatible = "shared-dma-pool";
88 no-map;
89 };
90 };
91
92 ahb {
93 compatible = "simple-bus";
94 #address-cells = <1>;
95 #size-cells = <1>;
96 device_type = "soc";
97 ranges;
98
99 gic: interrupt-controller@40461000 {
100 compatible = "arm,cortex-a7-gic";
101 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
102 #interrupt-cells = <3>;
103 interrupt-controller;
104 interrupt-parent = <&gic>;
105 reg = <0x40461000 0x1000>,
106 <0x40462000 0x1000>,
107 <0x40464000 0x2000>,
108 <0x40466000 0x2000>;
109 };
110
111 ahbc: ahbc@1e600000 {
112 compatible = "aspeed,aspeed-ahbc";
113 reg = < 0x1e600000 0x100>;
114 };
115
Billy Tsai2193dc62022-03-08 11:04:07 +0800[diff] [blame]116 pwm_tach: pwm_tach@1e610000 {
117 compatible = "aspeed,ast2600-pwm-tach", "simple-mfd", "syscon";
118 reg = <0x1e610000 0x100>;
119 clocks = <&scu ASPEED_CLK_AHB>;
120 resets = <&rst ASPEED_RESET_PWM>;
121
122 pwm: pwm {
123 compatible = "aspeed,ast2600-pwm";
124 #pwm-cells = <3>;
125 #address-cells = <1>;
126 #size-cells = <0>;
127 status = "disabled";
128 };
129 };
130
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]131 fmc: flash-controller@1e620000 {
Chin-Ting Kuo0ec02742022-08-19 17:01:07 +0800[diff] [blame]132 reg = <0x1e620000 0xc4>, <0x20000000 0x10000000>;
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]133 #address-cells = <1>;
134 #size-cells = <0>;
135 compatible = "aspeed,ast2600-fmc";
136 status = "disabled";
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]137 clocks = <&scu ASPEED_CLK_AHB>;
138 num-cs = <3>;
Chin-Ting Kuo0ec02742022-08-19 17:01:07 +0800[diff] [blame]139
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]140 flash@0 {
Chin-Ting Kuo0ec02742022-08-19 17:01:07 +0800[diff] [blame]141 reg = <0>;
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]142 compatible = "jedec,spi-nor";
143 status = "disabled";
144 };
Chin-Ting Kuo0ec02742022-08-19 17:01:07 +0800[diff] [blame]145
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]146 flash@1 {
Chin-Ting Kuo0ec02742022-08-19 17:01:07 +0800[diff] [blame]147 reg = <1>;
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]148 compatible = "jedec,spi-nor";
149 status = "disabled";
150 };
Chin-Ting Kuo0ec02742022-08-19 17:01:07 +0800[diff] [blame]151
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]152 flash@2 {
Chin-Ting Kuo0ec02742022-08-19 17:01:07 +0800[diff] [blame]153 reg = <2>;
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]154 compatible = "jedec,spi-nor";
155 status = "disabled";
156 };
157 };
158
159 spi1: flash-controller@1e630000 {
Chin-Ting Kuo0ec02742022-08-19 17:01:07 +0800[diff] [blame]160 reg = <0x1e630000 0xc4>, <0x30000000 0x10000000>;
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]161 #address-cells = <1>;
162 #size-cells = <0>;
163 compatible = "aspeed,ast2600-spi";
164 clocks = <&scu ASPEED_CLK_AHB>;
165 num-cs = <2>;
166 status = "disabled";
Chin-Ting Kuo0ec02742022-08-19 17:01:07 +0800[diff] [blame]167
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]168 flash@0 {
Chin-Ting Kuo0ec02742022-08-19 17:01:07 +0800[diff] [blame]169 reg = <0>;
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]170 compatible = "jedec,spi-nor";
171 status = "disabled";
172 };
Chin-Ting Kuo0ec02742022-08-19 17:01:07 +0800[diff] [blame]173
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]174 flash@1 {
Chin-Ting Kuo0ec02742022-08-19 17:01:07 +0800[diff] [blame]175 reg = <1>;
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]176 compatible = "jedec,spi-nor";
177 status = "disabled";
178 };
179 };
180
181 spi2: flash-controller@1e631000 {
Chin-Ting Kuo0ec02742022-08-19 17:01:07 +0800[diff] [blame]182 reg = <0x1e631000 0xc4>, <0x50000000 0x10000000>;
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]183 #address-cells = <1>;
184 #size-cells = <0>;
185 compatible = "aspeed,ast2600-spi";
186 clocks = <&scu ASPEED_CLK_AHB>;
187 num-cs = <3>;
188 status = "disabled";
Chin-Ting Kuo0ec02742022-08-19 17:01:07 +0800[diff] [blame]189
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]190 flash@0 {
Chin-Ting Kuo0ec02742022-08-19 17:01:07 +0800[diff] [blame]191 reg = <0>;
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]192 compatible = "jedec,spi-nor";
193 status = "disabled";
194 };
Chin-Ting Kuo0ec02742022-08-19 17:01:07 +0800[diff] [blame]195
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]196 flash@1 {
Chin-Ting Kuo0ec02742022-08-19 17:01:07 +0800[diff] [blame]197 reg = <1>;
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]198 compatible = "jedec,spi-nor";
199 status = "disabled";
200 };
Chin-Ting Kuo0ec02742022-08-19 17:01:07 +0800[diff] [blame]201
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]202 flash@2 {
Chin-Ting Kuo0ec02742022-08-19 17:01:07 +0800[diff] [blame]203 reg = <2>;
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]204 compatible = "jedec,spi-nor";
205 status = "disabled";
206 };
207 };
208
Joel Stanleyd18ef4f2021-10-27 14:17:28 +0800[diff] [blame]209 hace: hace@1e6d0000 {
210 compatible = "aspeed,ast2600-hace";
211 reg = <0x1e6d0000 0x200>;
212 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
213 clocks = <&scu ASPEED_CLK_GATE_YCLK>;
214 status = "disabled";
215 };
216
Chia-Wei Wang3435a3f2021-10-27 14:17:31 +0800[diff] [blame]217 acry: acry@1e6fa000 {
218 compatible = "aspeed,ast2600-acry";
219 reg = <0x1e6fa000 0x1000>,
220 <0x1e710000 0x10000>;
221 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
222 clocks = <&scu ASPEED_CLK_GATE_RSACLK>;
223 status = "disabled";
224 };
225
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]226 edac: sdram@1e6e0000 {
227 compatible = "aspeed,ast2600-sdram-edac";
228 reg = <0x1e6e0000 0x174>;
229 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
230 };
231
Dylan Hung82f25842021-12-09 10:12:26 +0800[diff] [blame]232 mdio: bus@1e650000 {
233 compatible = "simple-bus";
234 #address-cells = <1>;
235 #size-cells = <1>;
236 ranges = <0 0x1e650000 0x100>;
237
238 mdio0: mdio@0 {
239 compatible = "aspeed,ast2600-mdio";
240 reg = <0 0x8>;
241 resets = <&rst ASPEED_RESET_MII>;
242 pinctrl-names = "default";
243 pinctrl-0 = <&pinctrl_mdio1_default>;
244 status = "disabled";
245 };
246
247 mdio1: mdio@8 {
248 compatible = "aspeed,ast2600-mdio";
249 reg = <0x8 0x8>;
250 resets = <&rst ASPEED_RESET_MII>;
251 pinctrl-names = "default";
252 pinctrl-0 = <&pinctrl_mdio2_default>;
253 status = "disabled";
254 };
255
256 mdio2: mdio@10 {
257 compatible = "aspeed,ast2600-mdio";
258 reg = <0x10 0x8>;
259 resets = <&rst ASPEED_RESET_MII>;
260 pinctrl-names = "default";
261 pinctrl-0 = <&pinctrl_mdio3_default>;
262 status = "disabled";
263 };
264
265 mdio3: mdio@18 {
266 compatible = "aspeed,ast2600-mdio";
267 reg = <0x18 0x8>;
268 resets = <&rst ASPEED_RESET_MII>;
269 pinctrl-names = "default";
270 pinctrl-0 = <&pinctrl_mdio4_default>;
271 status = "disabled";
272 };
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]273 };
274
275 mac0: ftgmac@1e660000 {
276 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
277 reg = <0x1e660000 0x180>, <0x1e650000 0x4>;
278 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
279 clocks = <&scu ASPEED_CLK_GATE_MAC1CLK>;
280 status = "disabled";
281 };
282
283 mac1: ftgmac@1e680000 {
284 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
285 reg = <0x1e680000 0x180>, <0x1e650008 0x4>;
286 #address-cells = <1>;
287 #size-cells = <0>;
288 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
289 clocks = <&scu ASPEED_CLK_GATE_MAC2CLK>;
290 status = "disabled";
291 };
292
293 mac2: ftgmac@1e670000 {
294 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
295 reg = <0x1e670000 0x180>, <0x1e650010 0x4>;
296 #address-cells = <1>;
297 #size-cells = <0>;
298 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
299 clocks = <&scu ASPEED_CLK_GATE_MAC3CLK>;
300 status = "disabled";
301 };
302
303 mac3: ftgmac@1e690000 {
304 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
305 reg = <0x1e690000 0x180>, <0x1e650018 0x4>;
306 #address-cells = <1>;
307 #size-cells = <0>;
308 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
309 clocks = <&scu ASPEED_CLK_GATE_MAC4CLK>;
310 status = "disabled";
311 };
312
313 ehci0: usb@1e6a1000 {
314 compatible = "aspeed,aspeed-ehci", "usb-ehci";
315 reg = <0x1e6a1000 0x100>;
316 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
317 clocks = <&scu ASPEED_CLK_GATE_USBPORT1CLK>;
318 pinctrl-names = "default";
319 pinctrl-0 = <&pinctrl_usb2ah_default>;
320 status = "disabled";
321 };
322
323 ehci1: usb@1e6a3000 {
324 compatible = "aspeed,aspeed-ehci", "usb-ehci";
325 reg = <0x1e6a3000 0x100>;
326 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
327 clocks = <&scu ASPEED_CLK_GATE_USBPORT2CLK>;
328 pinctrl-names = "default";
329 pinctrl-0 = <&pinctrl_usb2bh_default>;
330 status = "disabled";
331 };
332
333 apb {
334 compatible = "simple-bus";
335 #address-cells = <1>;
336 #size-cells = <1>;
337 ranges;
338
339 syscon: syscon@1e6e2000 {
340 compatible = "aspeed,g6-scu", "syscon", "simple-mfd";
341 reg = <0x1e6e2000 0x1000>;
342 #address-cells = <1>;
343 #size-cells = <1>;
344 #clock-cells = <1>;
345 #reset-cells = <1>;
346 ranges = <0 0x1e6e2000 0x1000>;
347
348 pinctrl: pinctrl {
349 compatible = "aspeed,g6-pinctrl";
350 aspeed,external-nodes = <&gfx &lhc>;
351
352 };
353
354 vga_scratch: scratch {
355 compatible = "aspeed,bmc-misc";
356 };
357
358 scu_ic0: interrupt-controller@0 {
359 #interrupt-cells = <1>;
360 compatible = "aspeed,ast2600-scu-ic";
361 reg = <0x560 0x10>;
362 interrupt-parent = <&gic>;
363 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
364 interrupt-controller;
365 };
366
367 scu_ic1: interrupt-controller@1 {
368 #interrupt-cells = <1>;
369 compatible = "aspeed,ast2600-scu-ic";
370 reg = <0x570 0x10>;
371 interrupt-parent = <&gic>;
372 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
373 interrupt-controller;
374 };
375
376 };
377
378 smp-memram@0 {
379 compatible = "aspeed,ast2600-smpmem", "syscon";
380 reg = <0x1e6e2180 0x40>;
381 };
382
383 gfx: display@1e6e6000 {
384 compatible = "aspeed,ast2500-gfx", "syscon";
385 reg = <0x1e6e6000 0x1000>;
386 reg-io-width = <4>;
387 };
388
389 pcie_bridge0: pcie@1e6ed000 {
390 compatible = "aspeed,ast2600-pcie";
391 #address-cells = <3>;
392 #size-cells = <2>;
393 reg = <0x1e6ed000 0x100>;
394 ranges = <0x81000000 0x0 0x0 0x0 0x0 0x10000>,
395 <0x82000000 0x0 0x60000000 0x60000000 0x0 0x10000000>;
396 device_type = "pci";
397 bus-range = <0x00 0xff>;
398 resets = <&rst ASPEED_RESET_PCIE_DEV_O>;
399 cfg-handle = <&pcie_cfg0>;
400 pinctrl-names = "default";
401 pinctrl-0 = <&pinctrl_pcie0rc_default>;
402
403 status = "disabled";
404 };
405
406 pcie_bridge1: pcie@1e6ed200 {
407 compatible = "aspeed,ast2600-pcie";
408 #address-cells = <3>;
409 #size-cells = <2>;
410 reg = <0x1e6ed200 0x100>;
411 ranges = <0x81000000 0x0 0x0 0x10000 0x00 0x10000>,
412 <0x82000000 0x0 0x70000000 0x70000000 0x0 0x10000000>;
413 device_type = "pci";
414 bus-range = <0x00 0xff>;
415 resets = <&rst ASPEED_RESET_PCIE_RC_O>;
416 cfg-handle = <&pcie_cfg1>;
417 pinctrl-names = "default";
418 pinctrl-0 = <&pinctrl_pcie1rc_default>;
419
420 status = "disabled";
421 };
422
Joel Stanleya0c21182022-06-23 18:35:28 +0930[diff] [blame]423 sdc: sdc@1e740000 {
424 compatible = "aspeed,ast2600-sd-controller";
425 reg = <0x1e740000 0x100>;
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]426 #address-cells = <1>;
427 #size-cells = <1>;
Joel Stanleya0c21182022-06-23 18:35:28 +0930[diff] [blame]428 ranges = <0 0x1e740000 0x10000>;
429 clocks = <&scu ASPEED_CLK_GATE_SDCLK>;
430 status = "disabled";
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]431
Joel Stanleya0c21182022-06-23 18:35:28 +0930[diff] [blame]432 sdhci0: sdhci@1e740100 {
433 compatible = "aspeed,ast2600-sdhci", "sdhci";
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]434 reg = <0x100 0x100>;
Joel Stanleya0c21182022-06-23 18:35:28 +0930[diff] [blame]435 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]436 sdhci,auto-cmd12;
437 clocks = <&scu ASPEED_CLK_SDIO>;
438 status = "disabled";
439 };
440
Joel Stanleya0c21182022-06-23 18:35:28 +0930[diff] [blame]441 sdhci1: sdhci@1e740200 {
442 compatible = "aspeed,ast2600-sdhci", "sdhci";
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]443 reg = <0x200 0x100>;
Joel Stanleya0c21182022-06-23 18:35:28 +0930[diff] [blame]444 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]445 sdhci,auto-cmd12;
446 clocks = <&scu ASPEED_CLK_SDIO>;
447 status = "disabled";
448 };
449 };
450
Joel Stanleya0c21182022-06-23 18:35:28 +0930[diff] [blame]451 emmc_controller: sdc@1e750000 {
452 compatible = "aspeed,ast2600-sd-controller";
453 reg = <0x1e750000 0x100>;
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]454 #address-cells = <1>;
455 #size-cells = <1>;
Joel Stanleya0c21182022-06-23 18:35:28 +0930[diff] [blame]456 ranges = <0 0x1e750000 0x10000>;
457 clocks = <&scu ASPEED_CLK_GATE_EMMCCLK>;
458 status = "disabled";
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]459
Joel Stanleya0c21182022-06-23 18:35:28 +0930[diff] [blame]460 emmc: sdhci@1e750100 {
461 compatible = "aspeed,ast2600-sdhci";
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]462 reg = <0x100 0x100>;
Joel Stanleya0c21182022-06-23 18:35:28 +0930[diff] [blame]463 sdhci,auto-cmd12;
464 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]465 clocks = <&scu ASPEED_CLK_EMMC>;
Joel Stanleya0c21182022-06-23 18:35:28 +0930[diff] [blame]466 pinctrl-names = "default";
467 pinctrl-0 = <&pinctrl_emmc_default>;
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]468 };
469 };
470
471 h2x: h2x@1e770000 {
472 compatible = "aspeed,ast2600-h2x";
473 reg = <0x1e770000 0x100>;
474 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
475 resets = <&rst ASPEED_RESET_H2X>;
476 #address-cells = <1>;
477 #size-cells = <1>;
478 ranges = <0x0 0x1e770000 0x100>;
479
480 status = "disabled";
481
482 pcie_cfg0: cfg0@80 {
483 reg = <0x80 0x80>;
484 compatible = "aspeed,ast2600-pcie-cfg";
485 };
486
487 pcie_cfg1: cfg1@C0 {
488 compatible = "aspeed,ast2600-pcie-cfg";
489 reg = <0xC0 0x80>;
490 };
491 };
492
493 gpio0: gpio@1e780000 {
494 compatible = "aspeed,ast2600-gpio";
495 reg = <0x1e780000 0x1000>;
496 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
497 #gpio-cells = <2>;
498 gpio-controller;
499 interrupt-controller;
500 gpio-ranges = <&pinctrl 0 0 220>;
501 ngpios = <208>;
502 };
503
504 gpio1: gpio@1e780800 {
505 compatible = "aspeed,ast2600-gpio";
506 reg = <0x1e780800 0x800>;
507 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
508 #gpio-cells = <2>;
509 gpio-controller;
510 interrupt-controller;
511 gpio-ranges = <&pinctrl 0 0 208>;
512 ngpios = <36>;
513 };
514
515 uart1: serial@1e783000 {
516 compatible = "ns16550a";
517 reg = <0x1e783000 0x20>;
518 reg-shift = <2>;
519 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
520 clocks = <&scu ASPEED_CLK_GATE_UART1CLK>;
521 clock-frequency = <1846154>;
522 no-loopback-test;
523 status = "disabled";
524 };
525
526 uart5: serial@1e784000 {
527 compatible = "ns16550a";
528 reg = <0x1e784000 0x1000>;
529 reg-shift = <2>;
530 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
531 clocks = <&scu ASPEED_CLK_GATE_UART5CLK>;
532 clock-frequency = <1846154>;
533 no-loopback-test;
534 status = "disabled";
535 };
536
537 wdt1: watchdog@1e785000 {
538 compatible = "aspeed,ast2600-wdt";
539 reg = <0x1e785000 0x40>;
Chia-Wei Wang12364cc2021-09-16 14:10:09 +0800[diff] [blame]540 status = "disabled";
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]541 };
542
543 wdt2: watchdog@1e785040 {
544 compatible = "aspeed,ast2600-wdt";
545 reg = <0x1e785040 0x40>;
Chia-Wei Wang12364cc2021-09-16 14:10:09 +0800[diff] [blame]546 status = "disabled";
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]547 };
548
549 wdt3: watchdog@1e785080 {
550 compatible = "aspeed,ast2600-wdt";
551 reg = <0x1e785080 0x40>;
Chia-Wei Wang12364cc2021-09-16 14:10:09 +0800[diff] [blame]552 status = "disabled";
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]553 };
554
555 wdt4: watchdog@1e7850C0 {
556 compatible = "aspeed,ast2600-wdt";
557 reg = <0x1e7850C0 0x40>;
Chia-Wei Wang12364cc2021-09-16 14:10:09 +0800[diff] [blame]558 status = "disabled";
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]559 };
560
561 lpc: lpc@1e789000 {
562 compatible = "aspeed,ast2600-lpc", "simple-mfd", "syscon";
563 reg = <0x1e789000 0x1000>;
564
565 #address-cells = <1>;
566 #size-cells = <1>;
567 ranges = <0x0 0x1e789000 0x1000>;
568
569 kcs1: kcs1@0 {
570 compatible = "aspeed,ast2600-kcs-bmc";
571 reg = <0x0 0x80>;
572 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
573 kcs_chan = <1>;
574 kcs_addr = <0xCA0>;
575 status = "disabled";
576 };
577
578 kcs2: kcs2@0 {
579 compatible = "aspeed,ast2600-kcs-bmc";
580 reg = <0x0 0x80>;
581 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
582 kcs_chan = <2>;
583 kcs_addr = <0xCA8>;
584 status = "disabled";
585 };
586
587 kcs3: kcs3@0 {
588 compatible = "aspeed,ast2600-kcs-bmc";
589 reg = <0x0 0x80>;
590 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
591 kcs_chan = <3>;
592 kcs_addr = <0xCA2>;
593 };
594
595 kcs4: kcs4@0 {
596 compatible = "aspeed,ast2600-kcs-bmc";
597 reg = <0x0 0x120>;
598 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
599 kcs_chan = <4>;
600 kcs_addr = <0xCA4>;
601 status = "disabled";
602 };
603
604 lpc_ctrl: lpc-ctrl@80 {
605 compatible = "aspeed,ast2600-lpc-ctrl";
606 reg = <0x80 0x80>;
607 status = "disabled";
608 };
609
610 lpc_snoop: lpc-snoop@80 {
611 compatible = "aspeed,ast2600-lpc-snoop";
612 reg = <0x80 0x80>;
613 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
614 status = "disabled";
615 };
616
617 lhc: lhc@a0 {
618 compatible = "aspeed,ast2600-lhc";
619 reg = <0xa0 0x24 0xc8 0x8>;
620 };
621
622 lpc_reset: reset-controller@98 {
623 compatible = "aspeed,ast2600-lpc-reset";
624 reg = <0x98 0x4>;
625 #reset-cells = <1>;
626 status = "disabled";
627 };
628
629 ibt: ibt@140 {
630 compatible = "aspeed,ast2600-ibt-bmc";
631 reg = <0x140 0x18>;
632 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
633 status = "disabled";
634 };
635
636 sio_regs: regs {
637 compatible = "aspeed,bmc-misc";
638 };
639
640 mbox: mbox@200 {
641 compatible = "aspeed,ast2600-mbox";
642 reg = <0x200 0x5c>;
643 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
644 #mbox-cells = <1>;
645 status = "disabled";
646 };
647 };
648
649 uart2: serial@1e78d000 {
650 compatible = "ns16550a";
651 reg = <0x1e78d000 0x20>;
652 reg-shift = <2>;
653 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
654 clocks = <&scu ASPEED_CLK_GATE_UART2CLK>;
655 clock-frequency = <1846154>;
656 no-loopback-test;
657 status = "disabled";
658 };
659
660 uart3: serial@1e78e000 {
661 compatible = "ns16550a";
662 reg = <0x1e78e000 0x20>;
663 reg-shift = <2>;
664 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
665 clocks = <&scu ASPEED_CLK_GATE_UART3CLK>;
666 clock-frequency = <1846154>;
667 no-loopback-test;
668 status = "disabled";
669 };
670
671 uart4: serial@1e78f000 {
672 compatible = "ns16550a";
673 reg = <0x1e78f000 0x20>;
674 reg-shift = <2>;
675 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
676 clocks = <&scu ASPEED_CLK_GATE_UART4CLK>;
677 clock-frequency = <1846154>;
678 no-loopback-test;
679 status = "disabled";
680 };
681
682 i2c: bus@1e78a000 {
683 compatible = "simple-bus";
Ryan Chen56dd9182023-01-30 14:19:25 +0800[diff] [blame]684 reg = <0x1e78a000 0x1000>;
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]685 #address-cells = <1>;
686 #size-cells = <1>;
687 ranges = <0 0x1e78a000 0x1000>;
688 };
689
690 fsim0: fsi@1e79b000 {
691 compatible = "aspeed,ast2600-fsi-master", "fsi-master";
692 reg = <0x1e79b000 0x94>;
693 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
694 pinctrl-names = "default";
695 pinctrl-0 = <&pinctrl_fsi1_default>;
696 clocks = <&scu ASPEED_CLK_GATE_FSICLK>;
697 status = "disabled";
698 };
699
700 fsim1: fsi@1e79b100 {
701 compatible = "aspeed,ast2600-fsi-master", "fsi-master";
702 reg = <0x1e79b100 0x94>;
703 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
704 pinctrl-names = "default";
705 pinctrl-0 = <&pinctrl_fsi2_default>;
706 clocks = <&scu ASPEED_CLK_GATE_FSICLK>;
707 status = "disabled";
708 };
709
710 uart6: serial@1e790000 {
711 compatible = "ns16550a";
712 reg = <0x1e790000 0x20>;
713 reg-shift = <2>;
714 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
715 clocks = <&scu ASPEED_CLK_GATE_UART6CLK>;
716 clock-frequency = <1846154>;
717 no-loopback-test;
718 status = "disabled";
719 };
720
721 uart7: serial@1e790100 {
722 compatible = "ns16550a";
723 reg = <0x1e790100 0x20>;
724 reg-shift = <2>;
725 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
726 clocks = <&scu ASPEED_CLK_GATE_UART7CLK>;
727 clock-frequency = <1846154>;
728 no-loopback-test;
729 status = "disabled";
730 };
731
732 uart8: serial@1e790200 {
733 compatible = "ns16550a";
734 reg = <0x1e790200 0x20>;
735 reg-shift = <2>;
736 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
737 clocks = <&scu ASPEED_CLK_GATE_UART8CLK>;
738 clock-frequency = <1846154>;
739 no-loopback-test;
740 status = "disabled";
741 };
742
743 uart9: serial@1e790300 {
744 compatible = "ns16550a";
745 reg = <0x1e790300 0x20>;
746 reg-shift = <2>;
747 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
748 clocks = <&scu ASPEED_CLK_GATE_UART9CLK>;
749 clock-frequency = <1846154>;
750 no-loopback-test;
751 status = "disabled";
752 };
753
754 uart10: serial@1e790400 {
755 compatible = "ns16550a";
756 reg = <0x1e790400 0x20>;
757 reg-shift = <2>;
758 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
759 clocks = <&scu ASPEED_CLK_GATE_UART10CLK>;
760 clock-frequency = <1846154>;
761 no-loopback-test;
762 status = "disabled";
763 };
764
765 uart11: serial@1e790500 {
766 compatible = "ns16550a";
767 reg = <0x1e790400 0x20>;
768 reg-shift = <2>;
769 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
770 clocks = <&scu ASPEED_CLK_GATE_UART11CLK>;
771 clock-frequency = <1846154>;
772 no-loopback-test;
773 status = "disabled";
774 };
775
776 uart12: serial@1e790600 {
777 compatible = "ns16550a";
778 reg = <0x1e790600 0x20>;
779 reg-shift = <2>;
780 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
781 clocks = <&scu ASPEED_CLK_GATE_UART12CLK>;
782 clock-frequency = <1846154>;
783 no-loopback-test;
784 status = "disabled";
785 };
786
787 uart13: serial@1e790700 {
788 compatible = "ns16550a";
789 reg = <0x1e790700 0x20>;
790 reg-shift = <2>;
791 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
792 clocks = <&scu ASPEED_CLK_GATE_UART13CLK>;
793 clock-frequency = <1846154>;
794 no-loopback-test;
795 status = "disabled";
796 };
797
798 display_port: dp@1e6eb000 {
799 compatible = "aspeed,ast2600-displayport";
800 reg = <0x1e6eb000 0x200>;
801 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
802 resets = <&rst ASPEED_RESET_DP> ,<&rst ASPEED_RESET_DP_MCU>;
803 status = "disabled";
804 };
805
806 };
807
808 };
809
810};
811
812&i2c {
813 i2cglobal: i2cg@00 {
814 compatible = "aspeed,ast2600-i2c-global";
815 reg = <0x0 0x40>;
816 resets = <&rst ASPEED_RESET_I2C>;
817#if 0
818 new-mode;
819#endif
820 };
821
822 i2c0: i2c@80 {
823 #address-cells = <1>;
824 #size-cells = <0>;
825 #interrupt-cells = <1>;
826
827 reg = <0x80 0x80 0xC00 0x20>;
828 compatible = "aspeed,ast2600-i2c-bus";
829 bus-frequency = <100000>;
830 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
Joel Stanley2e8783b2022-06-23 14:40:32 +0930[diff] [blame]831 resets = <&rst ASPEED_RESET_I2C>;
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]832 clocks = <&scu ASPEED_CLK_APB2>;
Eddie James5b1ae362022-06-23 14:40:31 +0930[diff] [blame]833 pinctrl-names = "default";
834 pinctrl-0 = <&pinctrl_i2c1_default>;
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]835 status = "disabled";
836 };
837
838 i2c1: i2c@100 {
839 #address-cells = <1>;
840 #size-cells = <0>;
841 #interrupt-cells = <1>;
842
843 reg = <0x100 0x80 0xC20 0x20>;
844 compatible = "aspeed,ast2600-i2c-bus";
845 bus-frequency = <100000>;
846 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
Joel Stanley2e8783b2022-06-23 14:40:32 +0930[diff] [blame]847 resets = <&rst ASPEED_RESET_I2C>;
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]848 clocks = <&scu ASPEED_CLK_APB2>;
Eddie James5b1ae362022-06-23 14:40:31 +0930[diff] [blame]849 pinctrl-names = "default";
850 pinctrl-0 = <&pinctrl_i2c2_default>;
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]851 status = "disabled";
852 };
853
854 i2c2: i2c@180 {
855 #address-cells = <1>;
856 #size-cells = <0>;
857 #interrupt-cells = <1>;
858
859 reg = <0x180 0x80 0xC40 0x20>;
860 compatible = "aspeed,ast2600-i2c-bus";
861 bus-frequency = <100000>;
862 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
Joel Stanley2e8783b2022-06-23 14:40:32 +0930[diff] [blame]863 resets = <&rst ASPEED_RESET_I2C>;
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]864 clocks = <&scu ASPEED_CLK_APB2>;
Eddie James5b1ae362022-06-23 14:40:31 +0930[diff] [blame]865 pinctrl-names = "default";
866 pinctrl-0 = <&pinctrl_i2c3_default>;
Joel Stanleybfd04b22022-06-23 14:40:33 +0930[diff] [blame]867 status = "disabled";
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]868 };
869
870 i2c3: i2c@200 {
871 #address-cells = <1>;
872 #size-cells = <0>;
873 #interrupt-cells = <1>;
874
875 reg = <0x200 0x40 0xC60 0x20>;
876 compatible = "aspeed,ast2600-i2c-bus";
877 bus-frequency = <100000>;
878 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
Joel Stanley2e8783b2022-06-23 14:40:32 +0930[diff] [blame]879 resets = <&rst ASPEED_RESET_I2C>;
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]880 clocks = <&scu ASPEED_CLK_APB2>;
Eddie James5b1ae362022-06-23 14:40:31 +0930[diff] [blame]881 pinctrl-names = "default";
882 pinctrl-0 = <&pinctrl_i2c4_default>;
Joel Stanleybfd04b22022-06-23 14:40:33 +0930[diff] [blame]883 status = "disabled";
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]884 };
885
886 i2c4: i2c@280 {
887 #address-cells = <1>;
888 #size-cells = <0>;
889 #interrupt-cells = <1>;
890
891 reg = <0x280 0x80 0xC80 0x20>;
892 compatible = "aspeed,ast2600-i2c-bus";
893 bus-frequency = <100000>;
894 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
Joel Stanley2e8783b2022-06-23 14:40:32 +0930[diff] [blame]895 resets = <&rst ASPEED_RESET_I2C>;
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]896 clocks = <&scu ASPEED_CLK_APB2>;
Eddie James5b1ae362022-06-23 14:40:31 +0930[diff] [blame]897 pinctrl-names = "default";
898 pinctrl-0 = <&pinctrl_i2c5_default>;
Joel Stanleybfd04b22022-06-23 14:40:33 +0930[diff] [blame]899 status = "disabled";
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]900 };
901
902 i2c5: i2c@300 {
903 #address-cells = <1>;
904 #size-cells = <0>;
905 #interrupt-cells = <1>;
906
907 reg = <0x300 0x40 0xCA0 0x20>;
908 compatible = "aspeed,ast2600-i2c-bus";
909 bus-frequency = <100000>;
910 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
Joel Stanley2e8783b2022-06-23 14:40:32 +0930[diff] [blame]911 resets = <&rst ASPEED_RESET_I2C>;
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]912 clocks = <&scu ASPEED_CLK_APB2>;
Eddie James5b1ae362022-06-23 14:40:31 +0930[diff] [blame]913 pinctrl-names = "default";
914 pinctrl-0 = <&pinctrl_i2c6_default>;
Joel Stanleybfd04b22022-06-23 14:40:33 +0930[diff] [blame]915 status = "disabled";
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]916 };
917
918 i2c6: i2c@380 {
919 #address-cells = <1>;
920 #size-cells = <0>;
921 #interrupt-cells = <1>;
922
923 reg = <0x380 0x80 0xCC0 0x20>;
924 compatible = "aspeed,ast2600-i2c-bus";
925 bus-frequency = <100000>;
926 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
Joel Stanley2e8783b2022-06-23 14:40:32 +0930[diff] [blame]927 resets = <&rst ASPEED_RESET_I2C>;
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]928 clocks = <&scu ASPEED_CLK_APB2>;
Eddie James5b1ae362022-06-23 14:40:31 +0930[diff] [blame]929 pinctrl-names = "default";
930 pinctrl-0 = <&pinctrl_i2c7_default>;
Joel Stanleybfd04b22022-06-23 14:40:33 +0930[diff] [blame]931 status = "disabled";
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]932 };
933
934 i2c7: i2c@400 {
935 #address-cells = <1>;
936 #size-cells = <0>;
937 #interrupt-cells = <1>;
938
939 reg = <0x400 0x80 0xCE0 0x20>;
940 compatible = "aspeed,ast2600-i2c-bus";
941 bus-frequency = <100000>;
942 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
Joel Stanley2e8783b2022-06-23 14:40:32 +0930[diff] [blame]943 resets = <&rst ASPEED_RESET_I2C>;
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]944 clocks = <&scu ASPEED_CLK_APB2>;
Eddie James5b1ae362022-06-23 14:40:31 +0930[diff] [blame]945 pinctrl-names = "default";
946 pinctrl-0 = <&pinctrl_i2c8_default>;
Joel Stanleybfd04b22022-06-23 14:40:33 +0930[diff] [blame]947 status = "disabled";
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]948 };
949
950 i2c8: i2c@480 {
951 #address-cells = <1>;
952 #size-cells = <0>;
953 #interrupt-cells = <1>;
954
955 reg = <0x480 0x80 0xD00 0x20>;
956 compatible = "aspeed,ast2600-i2c-bus";
957 bus-frequency = <100000>;
958 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
Joel Stanley2e8783b2022-06-23 14:40:32 +0930[diff] [blame]959 resets = <&rst ASPEED_RESET_I2C>;
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]960 clocks = <&scu ASPEED_CLK_APB2>;
Eddie James5b1ae362022-06-23 14:40:31 +0930[diff] [blame]961 pinctrl-names = "default";
962 pinctrl-0 = <&pinctrl_i2c9_default>;
Joel Stanleybfd04b22022-06-23 14:40:33 +0930[diff] [blame]963 status = "disabled";
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]964 };
965
966 i2c9: i2c@500 {
967 #address-cells = <1>;
968 #size-cells = <0>;
969 #interrupt-cells = <1>;
970
971 reg = <0x500 0x80 0xD20 0x20>;
972 compatible = "aspeed,ast2600-i2c-bus";
973 bus-frequency = <100000>;
974 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
Joel Stanley2e8783b2022-06-23 14:40:32 +0930[diff] [blame]975 resets = <&rst ASPEED_RESET_I2C>;
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]976 clocks = <&scu ASPEED_CLK_APB2>;
Eddie James5b1ae362022-06-23 14:40:31 +0930[diff] [blame]977 pinctrl-names = "default";
978 pinctrl-0 = <&pinctrl_i2c10_default>;
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]979 status = "disabled";
980 };
981
982 i2c10: i2c@580 {
983 #address-cells = <1>;
984 #size-cells = <0>;
985 #interrupt-cells = <1>;
986
987 reg = <0x580 0x80 0xD40 0x20>;
988 compatible = "aspeed,ast2600-i2c-bus";
989 bus-frequency = <100000>;
990 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
Joel Stanley2e8783b2022-06-23 14:40:32 +0930[diff] [blame]991 resets = <&rst ASPEED_RESET_I2C>;
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]992 clocks = <&scu ASPEED_CLK_APB2>;
Eddie James5b1ae362022-06-23 14:40:31 +0930[diff] [blame]993 pinctrl-names = "default";
994 pinctrl-0 = <&pinctrl_i2c11_default>;
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]995 status = "disabled";
996 };
997
998 i2c11: i2c@600 {
999 #address-cells = <1>;
1000 #size-cells = <0>;
1001 #interrupt-cells = <1>;
1002
1003 reg = <0x600 0x80 0xD60 0x20>;
1004 compatible = "aspeed,ast2600-i2c-bus";
1005 bus-frequency = <100000>;
1006 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
Joel Stanley2e8783b2022-06-23 14:40:32 +0930[diff] [blame]1007 resets = <&rst ASPEED_RESET_I2C>;
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]1008 clocks = <&scu ASPEED_CLK_APB2>;
Eddie James5b1ae362022-06-23 14:40:31 +0930[diff] [blame]1009 pinctrl-names = "default";
1010 pinctrl-0 = <&pinctrl_i2c12_default>;
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]1011 status = "disabled";
1012 };
1013
1014 i2c12: i2c@680 {
1015 #address-cells = <1>;
1016 #size-cells = <0>;
1017 #interrupt-cells = <1>;
1018
1019 reg = <0x680 0x80 0xD80 0x20>;
1020 compatible = "aspeed,ast2600-i2c-bus";
1021 bus-frequency = <100000>;
1022 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
Joel Stanley2e8783b2022-06-23 14:40:32 +0930[diff] [blame]1023 resets = <&rst ASPEED_RESET_I2C>;
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]1024 clocks = <&scu ASPEED_CLK_APB2>;
Eddie James5b1ae362022-06-23 14:40:31 +0930[diff] [blame]1025 pinctrl-names = "default";
1026 pinctrl-0 = <&pinctrl_i2c13_default>;
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]1027 status = "disabled";
1028 };
1029
1030 i2c13: i2c@700 {
1031 #address-cells = <1>;
1032 #size-cells = <0>;
1033 #interrupt-cells = <1>;
1034
1035 reg = <0x700 0x80 0xDA0 0x20>;
1036 compatible = "aspeed,ast2600-i2c-bus";
1037 bus-frequency = <100000>;
1038 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
Joel Stanley2e8783b2022-06-23 14:40:32 +0930[diff] [blame]1039 resets = <&rst ASPEED_RESET_I2C>;
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]1040 clocks = <&scu ASPEED_CLK_APB2>;
Eddie James5b1ae362022-06-23 14:40:31 +0930[diff] [blame]1041 pinctrl-names = "default";
1042 pinctrl-0 = <&pinctrl_i2c14_default>;
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]1043 status = "disabled";
1044 };
1045
1046 i2c14: i2c@780 {
1047 #address-cells = <1>;
1048 #size-cells = <0>;
1049 #interrupt-cells = <1>;
1050
1051 reg = <0x780 0x80 0xDC0 0x20>;
1052 compatible = "aspeed,ast2600-i2c-bus";
1053 bus-frequency = <100000>;
1054 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
Joel Stanley2e8783b2022-06-23 14:40:32 +0930[diff] [blame]1055 resets = <&rst ASPEED_RESET_I2C>;
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]1056 clocks = <&scu ASPEED_CLK_APB2>;
Eddie James5b1ae362022-06-23 14:40:31 +0930[diff] [blame]1057 pinctrl-names = "default";
1058 pinctrl-0 = <&pinctrl_i2c15_default>;
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]1059 status = "disabled";
1060 };
1061
1062 i2c15: i2c@800 {
1063 #address-cells = <1>;
1064 #size-cells = <0>;
1065 #interrupt-cells = <1>;
1066
1067 reg = <0x800 0x80 0xDE0 0x20>;
1068 compatible = "aspeed,ast2600-i2c-bus";
1069 bus-frequency = <100000>;
1070 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
Joel Stanley2e8783b2022-06-23 14:40:32 +0930[diff] [blame]1071 resets = <&rst ASPEED_RESET_I2C>;
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]1072 clocks = <&scu ASPEED_CLK_APB2>;
Eddie James5b1ae362022-06-23 14:40:31 +0930[diff] [blame]1073 pinctrl-names = "default";
1074 pinctrl-0 = <&pinctrl_i2c16_default>;
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]1075 status = "disabled";
1076 };
1077
1078};
1079
1080&pinctrl {
1081 pinctrl_fmcquad_default: fmcquad_default {
1082 function = "FMCQUAD";
1083 groups = "FMCQUAD";
1084 };
1085
1086 pinctrl_spi1_default: spi1_default {
1087 function = "SPI1";
1088 groups = "SPI1";
1089 };
1090
1091 pinctrl_spi1abr_default: spi1abr_default {
1092 function = "SPI1ABR";
1093 groups = "SPI1ABR";
1094 };
1095
1096 pinctrl_spi1cs1_default: spi1cs1_default {
1097 function = "SPI1CS1";
1098 groups = "SPI1CS1";
1099 };
1100
1101 pinctrl_spi1wp_default: spi1wp_default {
1102 function = "SPI1WP";
1103 groups = "SPI1WP";
1104 };
1105
1106 pinctrl_spi1quad_default: spi1quad_default {
1107 function = "SPI1QUAD";
1108 groups = "SPI1QUAD";
1109 };
1110
1111 pinctrl_spi2_default: spi2_default {
1112 function = "SPI2";
1113 groups = "SPI2";
1114 };
1115
1116 pinctrl_spi2cs1_default: spi2cs1_default {
1117 function = "SPI2CS1";
1118 groups = "SPI2CS1";
1119 };
1120
1121 pinctrl_spi2cs2_default: spi2cs2_default {
1122 function = "SPI2CS2";
1123 groups = "SPI2CS2";
1124 };
1125
1126 pinctrl_spi2quad_default: spi2quad_default {
1127 function = "SPI2QUAD";
1128 groups = "SPI2QUAD";
1129 };
1130
1131 pinctrl_acpi_default: acpi_default {
1132 function = "ACPI";
1133 groups = "ACPI";
1134 };
1135
1136 pinctrl_adc0_default: adc0_default {
1137 function = "ADC0";
1138 groups = "ADC0";
1139 };
1140
1141 pinctrl_adc1_default: adc1_default {
1142 function = "ADC1";
1143 groups = "ADC1";
1144 };
1145
1146 pinctrl_adc10_default: adc10_default {
1147 function = "ADC10";
1148 groups = "ADC10";
1149 };
1150
1151 pinctrl_adc11_default: adc11_default {
1152 function = "ADC11";
1153 groups = "ADC11";
1154 };
1155
1156 pinctrl_adc12_default: adc12_default {
1157 function = "ADC12";
1158 groups = "ADC12";
1159 };
1160
1161 pinctrl_adc13_default: adc13_default {
1162 function = "ADC13";
1163 groups = "ADC13";
1164 };
1165
1166 pinctrl_adc14_default: adc14_default {
1167 function = "ADC14";
1168 groups = "ADC14";
1169 };
1170
1171 pinctrl_adc15_default: adc15_default {
1172 function = "ADC15";
1173 groups = "ADC15";
1174 };
1175
1176 pinctrl_adc2_default: adc2_default {
1177 function = "ADC2";
1178 groups = "ADC2";
1179 };
1180
1181 pinctrl_adc3_default: adc3_default {
1182 function = "ADC3";
1183 groups = "ADC3";
1184 };
1185
1186 pinctrl_adc4_default: adc4_default {
1187 function = "ADC4";
1188 groups = "ADC4";
1189 };
1190
1191 pinctrl_adc5_default: adc5_default {
1192 function = "ADC5";
1193 groups = "ADC5";
1194 };
1195
1196 pinctrl_adc6_default: adc6_default {
1197 function = "ADC6";
1198 groups = "ADC6";
1199 };
1200
1201 pinctrl_adc7_default: adc7_default {
1202 function = "ADC7";
1203 groups = "ADC7";
1204 };
1205
1206 pinctrl_adc8_default: adc8_default {
1207 function = "ADC8";
1208 groups = "ADC8";
1209 };
1210
1211 pinctrl_adc9_default: adc9_default {
1212 function = "ADC9";
1213 groups = "ADC9";
1214 };
1215
1216 pinctrl_bmcint_default: bmcint_default {
1217 function = "BMCINT";
1218 groups = "BMCINT";
1219 };
1220
1221 pinctrl_ddcclk_default: ddcclk_default {
1222 function = "DDCCLK";
1223 groups = "DDCCLK";
1224 };
1225
1226 pinctrl_ddcdat_default: ddcdat_default {
1227 function = "DDCDAT";
1228 groups = "DDCDAT";
1229 };
1230
1231 pinctrl_espi_default: espi_default {
1232 function = "ESPI";
1233 groups = "ESPI";
1234 };
1235
1236 pinctrl_fsi1_default: fsi1_default {
1237 function = "FSI1";
1238 groups = "FSI1";
1239 };
1240
1241 pinctrl_fsi2_default: fsi2_default {
1242 function = "FSI2";
1243 groups = "FSI2";
1244 };
1245
1246 pinctrl_fwspics1_default: fwspics1_default {
1247 function = "FWSPICS1";
1248 groups = "FWSPICS1";
1249 };
1250
1251 pinctrl_fwspics2_default: fwspics2_default {
1252 function = "FWSPICS2";
1253 groups = "FWSPICS2";
1254 };
1255
1256 pinctrl_gpid0_default: gpid0_default {
1257 function = "GPID0";
1258 groups = "GPID0";
1259 };
1260
1261 pinctrl_gpid2_default: gpid2_default {
1262 function = "GPID2";
1263 groups = "GPID2";
1264 };
1265
1266 pinctrl_gpid4_default: gpid4_default {
1267 function = "GPID4";
1268 groups = "GPID4";
1269 };
1270
1271 pinctrl_gpid6_default: gpid6_default {
1272 function = "GPID6";
1273 groups = "GPID6";
1274 };
1275
1276 pinctrl_gpie0_default: gpie0_default {
1277 function = "GPIE0";
1278 groups = "GPIE0";
1279 };
1280
1281 pinctrl_gpie2_default: gpie2_default {
1282 function = "GPIE2";
1283 groups = "GPIE2";
1284 };
1285
1286 pinctrl_gpie4_default: gpie4_default {
1287 function = "GPIE4";
1288 groups = "GPIE4";
1289 };
1290
1291 pinctrl_gpie6_default: gpie6_default {
1292 function = "GPIE6";
1293 groups = "GPIE6";
1294 };
1295
1296 pinctrl_i2c1_default: i2c1_default {
1297 function = "I2C1";
1298 groups = "I2C1";
1299 };
Eddie James5b1ae362022-06-23 14:40:31 +0930[diff] [blame]1300
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]1301 pinctrl_i2c2_default: i2c2_default {
1302 function = "I2C2";
1303 groups = "I2C2";
1304 };
1305
1306 pinctrl_i2c3_default: i2c3_default {
1307 function = "I2C3";
1308 groups = "I2C3";
1309 };
1310
1311 pinctrl_i2c4_default: i2c4_default {
1312 function = "I2C4";
1313 groups = "I2C4";
1314 };
1315
1316 pinctrl_i2c5_default: i2c5_default {
1317 function = "I2C5";
1318 groups = "I2C5";
1319 };
1320
1321 pinctrl_i2c6_default: i2c6_default {
1322 function = "I2C6";
1323 groups = "I2C6";
1324 };
1325
1326 pinctrl_i2c7_default: i2c7_default {
1327 function = "I2C7";
1328 groups = "I2C7";
1329 };
1330
1331 pinctrl_i2c8_default: i2c8_default {
1332 function = "I2C8";
1333 groups = "I2C8";
1334 };
1335
1336 pinctrl_i2c9_default: i2c9_default {
1337 function = "I2C9";
1338 groups = "I2C9";
1339 };
1340
1341 pinctrl_i2c10_default: i2c10_default {
1342 function = "I2C10";
1343 groups = "I2C10";
1344 };
1345
1346 pinctrl_i2c11_default: i2c11_default {
1347 function = "I2C11";
1348 groups = "I2C11";
1349 };
1350
1351 pinctrl_i2c12_default: i2c12_default {
1352 function = "I2C12";
1353 groups = "I2C12";
1354 };
1355
1356 pinctrl_i2c13_default: i2c13_default {
1357 function = "I2C13";
1358 groups = "I2C13";
1359 };
1360
1361 pinctrl_i2c14_default: i2c14_default {
1362 function = "I2C14";
1363 groups = "I2C14";
1364 };
1365
1366 pinctrl_i2c15_default: i2c15_default {
1367 function = "I2C15";
1368 groups = "I2C15";
1369 };
1370
1371 pinctrl_i2c16_default: i2c16_default {
1372 function = "I2C16";
1373 groups = "I2C16";
1374 };
1375
1376 pinctrl_lad0_default: lad0_default {
1377 function = "LAD0";
1378 groups = "LAD0";
1379 };
1380
1381 pinctrl_lad1_default: lad1_default {
1382 function = "LAD1";
1383 groups = "LAD1";
1384 };
1385
1386 pinctrl_lad2_default: lad2_default {
1387 function = "LAD2";
1388 groups = "LAD2";
1389 };
1390
1391 pinctrl_lad3_default: lad3_default {
1392 function = "LAD3";
1393 groups = "LAD3";
1394 };
1395
1396 pinctrl_lclk_default: lclk_default {
1397 function = "LCLK";
1398 groups = "LCLK";
1399 };
1400
1401 pinctrl_lframe_default: lframe_default {
1402 function = "LFRAME";
1403 groups = "LFRAME";
1404 };
1405
1406 pinctrl_lpchc_default: lpchc_default {
1407 function = "LPCHC";
1408 groups = "LPCHC";
1409 };
1410
1411 pinctrl_lpcpd_default: lpcpd_default {
1412 function = "LPCPD";
1413 groups = "LPCPD";
1414 };
1415
1416 pinctrl_lpcplus_default: lpcplus_default {
1417 function = "LPCPLUS";
1418 groups = "LPCPLUS";
1419 };
1420
1421 pinctrl_lpcpme_default: lpcpme_default {
1422 function = "LPCPME";
1423 groups = "LPCPME";
1424 };
1425
1426 pinctrl_lpcrst_default: lpcrst_default {
1427 function = "LPCRST";
1428 groups = "LPCRST";
1429 };
1430
1431 pinctrl_lpcsmi_default: lpcsmi_default {
1432 function = "LPCSMI";
1433 groups = "LPCSMI";
1434 };
1435
1436 pinctrl_lsirq_default: lsirq_default {
1437 function = "LSIRQ";
1438 groups = "LSIRQ";
1439 };
1440
1441 pinctrl_mac1link_default: mac1link_default {
1442 function = "MAC1LINK";
1443 groups = "MAC1LINK";
1444 };
1445
1446 pinctrl_mac2link_default: mac2link_default {
1447 function = "MAC2LINK";
1448 groups = "MAC2LINK";
1449 };
1450
1451 pinctrl_mac3link_default: mac3link_default {
1452 function = "MAC3LINK";
1453 groups = "MAC3LINK";
1454 };
1455
1456 pinctrl_mac4link_default: mac4link_default {
1457 function = "MAC4LINK";
1458 groups = "MAC4LINK";
1459 };
1460
1461 pinctrl_mdio1_default: mdio1_default {
1462 function = "MDIO1";
1463 groups = "MDIO1";
1464 };
1465
1466 pinctrl_mdio2_default: mdio2_default {
1467 function = "MDIO2";
1468 groups = "MDIO2";
1469 };
1470
1471 pinctrl_mdio3_default: mdio3_default {
1472 function = "MDIO3";
1473 groups = "MDIO3";
1474 };
1475
1476 pinctrl_mdio4_default: mdio4_default {
1477 function = "MDIO4";
1478 groups = "MDIO4";
1479 };
1480
1481 pinctrl_rmii1_default: rmii1_default {
1482 function = "RMII1";
1483 groups = "RMII1";
1484 };
1485
1486 pinctrl_rmii2_default: rmii2_default {
1487 function = "RMII2";
1488 groups = "RMII2";
1489 };
1490
1491 pinctrl_rmii3_default: rmii3_default {
1492 function = "RMII3";
1493 groups = "RMII3";
1494 };
1495
1496 pinctrl_rmii4_default: rmii4_default {
1497 function = "RMII4";
1498 groups = "RMII4";
1499 };
1500
1501 pinctrl_rmii1rclk_default: rmii1rclk_default {
1502 function = "RMII1RCLK";
1503 groups = "RMII1RCLK";
1504 };
1505
1506 pinctrl_rmii2rclk_default: rmii2rclk_default {
1507 function = "RMII2RCLK";
1508 groups = "RMII2RCLK";
1509 };
1510
1511 pinctrl_rmii3rclk_default: rmii3rclk_default {
1512 function = "RMII3RCLK";
1513 groups = "RMII3RCLK";
1514 };
1515
1516 pinctrl_rmii4rclk_default: rmii4rclk_default {
1517 function = "RMII4RCLK";
1518 groups = "RMII4RCLK";
1519 };
1520
1521 pinctrl_ncts1_default: ncts1_default {
1522 function = "NCTS1";
1523 groups = "NCTS1";
1524 };
1525
1526 pinctrl_ncts2_default: ncts2_default {
1527 function = "NCTS2";
1528 groups = "NCTS2";
1529 };
1530
1531 pinctrl_ncts3_default: ncts3_default {
1532 function = "NCTS3";
1533 groups = "NCTS3";
1534 };
1535
1536 pinctrl_ncts4_default: ncts4_default {
1537 function = "NCTS4";
1538 groups = "NCTS4";
1539 };
1540
1541 pinctrl_ndcd1_default: ndcd1_default {
1542 function = "NDCD1";
1543 groups = "NDCD1";
1544 };
1545
1546 pinctrl_ndcd2_default: ndcd2_default {
1547 function = "NDCD2";
1548 groups = "NDCD2";
1549 };
1550
1551 pinctrl_ndcd3_default: ndcd3_default {
1552 function = "NDCD3";
1553 groups = "NDCD3";
1554 };
1555
1556 pinctrl_ndcd4_default: ndcd4_default {
1557 function = "NDCD4";
1558 groups = "NDCD4";
1559 };
1560
1561 pinctrl_ndsr1_default: ndsr1_default {
1562 function = "NDSR1";
1563 groups = "NDSR1";
1564 };
1565
1566 pinctrl_ndsr2_default: ndsr2_default {
1567 function = "NDSR2";
1568 groups = "NDSR2";
1569 };
1570
1571 pinctrl_ndsr3_default: ndsr3_default {
1572 function = "NDSR3";
1573 groups = "NDSR3";
1574 };
1575
1576 pinctrl_ndsr4_default: ndsr4_default {
1577 function = "NDSR4";
1578 groups = "NDSR4";
1579 };
1580
1581 pinctrl_ndtr1_default: ndtr1_default {
1582 function = "NDTR1";
1583 groups = "NDTR1";
1584 };
1585
1586 pinctrl_ndtr2_default: ndtr2_default {
1587 function = "NDTR2";
1588 groups = "NDTR2";
1589 };
1590
1591 pinctrl_ndtr3_default: ndtr3_default {
1592 function = "NDTR3";
1593 groups = "NDTR3";
1594 };
1595
1596 pinctrl_ndtr4_default: ndtr4_default {
1597 function = "NDTR4";
1598 groups = "NDTR4";
1599 };
1600
1601 pinctrl_nri1_default: nri1_default {
1602 function = "NRI1";
1603 groups = "NRI1";
1604 };
1605
1606 pinctrl_nri2_default: nri2_default {
1607 function = "NRI2";
1608 groups = "NRI2";
1609 };
1610
1611 pinctrl_nri3_default: nri3_default {
1612 function = "NRI3";
1613 groups = "NRI3";
1614 };
1615
1616 pinctrl_nri4_default: nri4_default {
1617 function = "NRI4";
1618 groups = "NRI4";
1619 };
1620
1621 pinctrl_nrts1_default: nrts1_default {
1622 function = "NRTS1";
1623 groups = "NRTS1";
1624 };
1625
1626 pinctrl_nrts2_default: nrts2_default {
1627 function = "NRTS2";
1628 groups = "NRTS2";
1629 };
1630
1631 pinctrl_nrts3_default: nrts3_default {
1632 function = "NRTS3";
1633 groups = "NRTS3";
1634 };
1635
1636 pinctrl_nrts4_default: nrts4_default {
1637 function = "NRTS4";
1638 groups = "NRTS4";
1639 };
1640
1641 pinctrl_oscclk_default: oscclk_default {
1642 function = "OSCCLK";
1643 groups = "OSCCLK";
1644 };
1645
1646 pinctrl_pewake_default: pewake_default {
1647 function = "PEWAKE";
1648 groups = "PEWAKE";
1649 };
1650
1651 pinctrl_pnor_default: pnor_default {
1652 function = "PNOR";
1653 groups = "PNOR";
1654 };
1655
1656 pinctrl_pwm0_default: pwm0_default {
1657 function = "PWM0";
1658 groups = "PWM0";
1659 };
1660
1661 pinctrl_pwm1_default: pwm1_default {
1662 function = "PWM1";
1663 groups = "PWM1";
1664 };
1665
1666 pinctrl_pwm2_default: pwm2_default {
1667 function = "PWM2";
1668 groups = "PWM2";
1669 };
1670
1671 pinctrl_pwm3_default: pwm3_default {
1672 function = "PWM3";
1673 groups = "PWM3";
1674 };
1675
1676 pinctrl_pwm4_default: pwm4_default {
1677 function = "PWM4";
1678 groups = "PWM4";
1679 };
1680
1681 pinctrl_pwm5_default: pwm5_default {
1682 function = "PWM5";
1683 groups = "PWM5";
1684 };
1685
1686 pinctrl_pwm6_default: pwm6_default {
1687 function = "PWM6";
1688 groups = "PWM6";
1689 };
1690
1691 pinctrl_pwm7_default: pwm7_default {
1692 function = "PWM7";
1693 groups = "PWM7";
1694 };
1695
Billy Tsai01013c82022-03-08 11:04:06 +0800[diff] [blame]1696 pinctrl_pwm8g0_default: pwm8g0_default {
1697 function = "PWM8G0";
1698 groups = "PWM8G0";
1699 };
1700
1701 pinctrl_pwm8g1_default: pwm8g1_default {
1702 function = "PWM8G1";
1703 groups = "PWM8G1";
1704 };
1705
1706 pinctrl_pwm9g0_default: pwm9g0_default {
1707 function = "PWM9G0";
1708 groups = "PWM9G0";
1709 };
1710
1711 pinctrl_pwm9g1_default: pwm9g1_default {
1712 function = "PWM9G1";
1713 groups = "PWM9G1";
1714 };
1715
1716 pinctrl_pwm10g0_default: pwm10g0_default {
1717 function = "PWM10G0";
1718 groups = "PWM10G0";
1719 };
1720
1721 pinctrl_pwm10g1_default: pwm10g1_default {
1722 function = "PWM10G1";
1723 groups = "PWM10G1";
1724 };
1725
1726 pinctrl_pwm11g0_default: pwm11g0_default {
1727 function = "PWM11G0";
1728 groups = "PWM11G0";
1729 };
1730
1731 pinctrl_pwm11g1_default: pwm11g1_default {
1732 function = "PWM11G1";
1733 groups = "PWM11G1";
1734 };
1735
1736 pinctrl_pwm12g0_default: pwm12g0_default {
1737 function = "PWM12G0";
1738 groups = "PWM12G0";
1739 };
1740
1741 pinctrl_pwm12g1_default: pwm12g1_default {
1742 function = "PWM12G1";
1743 groups = "PWM12G1";
1744 };
1745
1746 pinctrl_pwm13g0_default: pwm13g0_default {
1747 function = "PWM13G0";
1748 groups = "PWM13G0";
1749 };
1750
1751 pinctrl_pwm13g1_default: pwm13g1_default {
1752 function = "PWM13G1";
1753 groups = "PWM13G1";
1754 };
1755
1756 pinctrl_pwm14g0_default: pwm14g0_default {
1757 function = "PWM14G0";
1758 groups = "PWM14G0";
1759 };
1760
1761 pinctrl_pwm14g1_default: pwm14g1_default {
1762 function = "PWM14G1";
1763 groups = "PWM14G1";
1764 };
1765
1766 pinctrl_pwm15g0_default: pwm15g0_default {
1767 function = "PWM15G0";
1768 groups = "PWM15G0";
1769 };
1770
1771 pinctrl_pwm15g1_default: pwm15g1_default {
1772 function = "PWM15G1";
1773 groups = "PWM15G1";
1774 };
1775
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]1776 pinctrl_rgmii1_default: rgmii1_default {
1777 function = "RGMII1";
1778 groups = "RGMII1";
1779 };
1780
1781 pinctrl_rgmii2_default: rgmii2_default {
1782 function = "RGMII2";
1783 groups = "RGMII2";
1784 };
1785
1786 pinctrl_rgmii3_default: rgmii3_default {
1787 function = "RGMII3";
1788 groups = "RGMII3";
1789 };
1790
1791 pinctrl_rgmii4_default: rgmii4_default {
1792 function = "RGMII4";
1793 groups = "RGMII4";
1794 };
1795
1796 pinctrl_rmii1_default: rmii1_default {
1797 function = "RMII1";
1798 groups = "RMII1";
1799 };
1800
1801 pinctrl_rmii2_default: rmii2_default {
1802 function = "RMII2";
1803 groups = "RMII2";
1804 };
1805
1806 pinctrl_rxd1_default: rxd1_default {
1807 function = "RXD1";
1808 groups = "RXD1";
1809 };
1810
1811 pinctrl_rxd2_default: rxd2_default {
1812 function = "RXD2";
1813 groups = "RXD2";
1814 };
1815
1816 pinctrl_rxd3_default: rxd3_default {
1817 function = "RXD3";
1818 groups = "RXD3";
1819 };
1820
1821 pinctrl_rxd4_default: rxd4_default {
1822 function = "RXD4";
1823 groups = "RXD4";
1824 };
1825
1826 pinctrl_salt1_default: salt1_default {
1827 function = "SALT1";
1828 groups = "SALT1";
1829 };
1830
1831 pinctrl_salt10_default: salt10_default {
1832 function = "SALT10";
1833 groups = "SALT10";
1834 };
1835
1836 pinctrl_salt11_default: salt11_default {
1837 function = "SALT11";
1838 groups = "SALT11";
1839 };
1840
1841 pinctrl_salt12_default: salt12_default {
1842 function = "SALT12";
1843 groups = "SALT12";
1844 };
1845
1846 pinctrl_salt13_default: salt13_default {
1847 function = "SALT13";
1848 groups = "SALT13";
1849 };
1850
1851 pinctrl_salt14_default: salt14_default {
1852 function = "SALT14";
1853 groups = "SALT14";
1854 };
1855
1856 pinctrl_salt2_default: salt2_default {
1857 function = "SALT2";
1858 groups = "SALT2";
1859 };
1860
1861 pinctrl_salt3_default: salt3_default {
1862 function = "SALT3";
1863 groups = "SALT3";
1864 };
1865
1866 pinctrl_salt4_default: salt4_default {
1867 function = "SALT4";
1868 groups = "SALT4";
1869 };
1870
1871 pinctrl_salt5_default: salt5_default {
1872 function = "SALT5";
1873 groups = "SALT5";
1874 };
1875
1876 pinctrl_salt6_default: salt6_default {
1877 function = "SALT6";
1878 groups = "SALT6";
1879 };
1880
1881 pinctrl_salt7_default: salt7_default {
1882 function = "SALT7";
1883 groups = "SALT7";
1884 };
1885
1886 pinctrl_salt8_default: salt8_default {
1887 function = "SALT8";
1888 groups = "SALT8";
1889 };
1890
1891 pinctrl_salt9_default: salt9_default {
1892 function = "SALT9";
1893 groups = "SALT9";
1894 };
1895
1896 pinctrl_scl1_default: scl1_default {
1897 function = "SCL1";
1898 groups = "SCL1";
1899 };
1900
1901 pinctrl_scl2_default: scl2_default {
1902 function = "SCL2";
1903 groups = "SCL2";
1904 };
1905
1906 pinctrl_sd1_default: sd1_default {
1907 function = "SD1";
1908 groups = "SD1";
1909 };
1910
1911 pinctrl_sd2_default: sd2_default {
1912 function = "SD2";
1913 groups = "SD2";
1914 };
1915
1916 pinctrl_emmc_default: emmc_default {
1917 function = "EMMC";
1918 groups = "EMMC";
1919 };
1920
1921 pinctrl_emmcg8_default: emmcg8_default {
1922 function = "EMMCG8";
1923 groups = "EMMCG8";
1924 };
1925
1926 pinctrl_sda1_default: sda1_default {
1927 function = "SDA1";
1928 groups = "SDA1";
1929 };
1930
1931 pinctrl_sda2_default: sda2_default {
1932 function = "SDA2";
1933 groups = "SDA2";
1934 };
1935
1936 pinctrl_sgps1_default: sgps1_default {
1937 function = "SGPS1";
1938 groups = "SGPS1";
1939 };
1940
1941 pinctrl_sgps2_default: sgps2_default {
1942 function = "SGPS2";
1943 groups = "SGPS2";
1944 };
1945
1946 pinctrl_sioonctrl_default: sioonctrl_default {
1947 function = "SIOONCTRL";
1948 groups = "SIOONCTRL";
1949 };
1950
1951 pinctrl_siopbi_default: siopbi_default {
1952 function = "SIOPBI";
1953 groups = "SIOPBI";
1954 };
1955
1956 pinctrl_siopbo_default: siopbo_default {
1957 function = "SIOPBO";
1958 groups = "SIOPBO";
1959 };
1960
1961 pinctrl_siopwreq_default: siopwreq_default {
1962 function = "SIOPWREQ";
1963 groups = "SIOPWREQ";
1964 };
1965
1966 pinctrl_siopwrgd_default: siopwrgd_default {
1967 function = "SIOPWRGD";
1968 groups = "SIOPWRGD";
1969 };
1970
1971 pinctrl_sios3_default: sios3_default {
1972 function = "SIOS3";
1973 groups = "SIOS3";
1974 };
1975
1976 pinctrl_sios5_default: sios5_default {
1977 function = "SIOS5";
1978 groups = "SIOS5";
1979 };
1980
1981 pinctrl_siosci_default: siosci_default {
1982 function = "SIOSCI";
1983 groups = "SIOSCI";
1984 };
1985
1986 pinctrl_spi1_default: spi1_default {
1987 function = "SPI1";
1988 groups = "SPI1";
1989 };
1990
1991 pinctrl_spi1cs1_default: spi1cs1_default {
1992 function = "SPI1CS1";
1993 groups = "SPI1CS1";
1994 };
1995
1996 pinctrl_spi1debug_default: spi1debug_default {
1997 function = "SPI1DEBUG";
1998 groups = "SPI1DEBUG";
1999 };
2000
2001 pinctrl_spi1passthru_default: spi1passthru_default {
2002 function = "SPI1PASSTHRU";
2003 groups = "SPI1PASSTHRU";
2004 };
2005
2006 pinctrl_spi2ck_default: spi2ck_default {
2007 function = "SPI2CK";
2008 groups = "SPI2CK";
2009 };
2010
2011 pinctrl_spi2cs0_default: spi2cs0_default {
2012 function = "SPI2CS0";
2013 groups = "SPI2CS0";
2014 };
2015
2016 pinctrl_spi2cs1_default: spi2cs1_default {
2017 function = "SPI2CS1";
2018 groups = "SPI2CS1";
2019 };
2020
2021 pinctrl_spi2miso_default: spi2miso_default {
2022 function = "SPI2MISO";
2023 groups = "SPI2MISO";
2024 };
2025
2026 pinctrl_spi2mosi_default: spi2mosi_default {
2027 function = "SPI2MOSI";
2028 groups = "SPI2MOSI";
2029 };
2030
2031 pinctrl_timer3_default: timer3_default {
2032 function = "TIMER3";
2033 groups = "TIMER3";
2034 };
2035
2036 pinctrl_timer4_default: timer4_default {
2037 function = "TIMER4";
2038 groups = "TIMER4";
2039 };
2040
2041 pinctrl_timer5_default: timer5_default {
2042 function = "TIMER5";
2043 groups = "TIMER5";
2044 };
2045
2046 pinctrl_timer6_default: timer6_default {
2047 function = "TIMER6";
2048 groups = "TIMER6";
2049 };
2050
2051 pinctrl_timer7_default: timer7_default {
2052 function = "TIMER7";
2053 groups = "TIMER7";
2054 };
2055
2056 pinctrl_timer8_default: timer8_default {
2057 function = "TIMER8";
2058 groups = "TIMER8";
2059 };
2060
2061 pinctrl_txd1_default: txd1_default {
2062 function = "TXD1";
2063 groups = "TXD1";
2064 };
2065
2066 pinctrl_txd2_default: txd2_default {
2067 function = "TXD2";
2068 groups = "TXD2";
2069 };
2070
2071 pinctrl_txd3_default: txd3_default {
2072 function = "TXD3";
2073 groups = "TXD3";
2074 };
2075
2076 pinctrl_txd4_default: txd4_default {
2077 function = "TXD4";
2078 groups = "TXD4";
2079 };
2080
2081 pinctrl_uart6_default: uart6_default {
2082 function = "UART6";
2083 groups = "UART6";
2084 };
2085
2086 pinctrl_usbcki_default: usbcki_default {
2087 function = "USBCKI";
2088 groups = "USBCKI";
2089 };
2090
2091 pinctrl_usb2ah_default: usb2ah_default {
2092 function = "USB2AH";
2093 groups = "USB2AH";
2094 };
2095
2096 pinctrl_usb11bhid_default: usb11bhid_default {
2097 function = "USB11BHID";
2098 groups = "USB11BHID";
2099 };
2100
2101 pinctrl_usb2bh_default: usb2bh_default {
2102 function = "USB2BH";
2103 groups = "USB2BH";
2104 };
2105
2106 pinctrl_vgabiosrom_default: vgabiosrom_default {
2107 function = "VGABIOSROM";
2108 groups = "VGABIOSROM";
2109 };
2110
2111 pinctrl_vgahs_default: vgahs_default {
2112 function = "VGAHS";
2113 groups = "VGAHS";
2114 };
2115
2116 pinctrl_vgavs_default: vgavs_default {
2117 function = "VGAVS";
2118 groups = "VGAVS";
2119 };
2120
2121 pinctrl_vpi24_default: vpi24_default {
2122 function = "VPI24";
2123 groups = "VPI24";
2124 };
2125
2126 pinctrl_vpo_default: vpo_default {
2127 function = "VPO";
2128 groups = "VPO";
2129 };
2130
2131 pinctrl_wdtrst1_default: wdtrst1_default {
2132 function = "WDTRST1";
2133 groups = "WDTRST1";
2134 };
2135
2136 pinctrl_wdtrst2_default: wdtrst2_default {
2137 function = "WDTRST2";
2138 groups = "WDTRST2";
2139 };
2140
2141 pinctrl_pcie0rc_default: pcie0rc_default {
2142 function = "PCIE0RC";
2143 groups = "PCIE0RC";
2144 };
2145
2146 pinctrl_pcie1rc_default: pcie1rc_default {
2147 function = "PCIE1RC";
2148 groups = "PCIE1RC";
2149 };
2150};