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git01.mediatek.com / filogic / uboot / 2193dc6dce59be05cf2052fee56d7b7e881de5d4 / . / arch / arm / dts / ast2600.dtsi
blob: 64074309b7b2393d7b39ab8168eaabb0b73194ee [file] [log] [blame]
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0+
2#include <dt-bindings/interrupt-controller/arm-gic.h>
3#include "skeleton.dtsi"
4
5/ {
6 model = "Aspeed BMC";
7 compatible = "aspeed,ast2600";
8 #address-cells = <1>;
9 #size-cells = <1>;
10 interrupt-parent = <&gic>;
11
12 aliases {
13 i2c0 = &i2c0;
14 i2c1 = &i2c1;
15 i2c2 = &i2c2;
16 i2c3 = &i2c3;
17 i2c4 = &i2c4;
18 i2c5 = &i2c5;
19 i2c6 = &i2c6;
20 i2c7 = &i2c7;
21 i2c8 = &i2c8;
22 i2c9 = &i2c9;
23 i2c10 = &i2c10;
24 i2c11 = &i2c11;
25 i2c12 = &i2c12;
26 i2c13 = &i2c13;
27 i2c14 = &i2c14;
28 i2c15 = &i2c15;
29 serial0 = &uart1;
30 serial1 = &uart2;
31 serial2 = &uart3;
32 serial3 = &uart4;
33 serial4 = &uart5;
34 serial5 = &uart6;
35 serial6 = &uart7;
36 serial7 = &uart8;
37 serial8 = &uart9;
38 serial9 = &uart10;
39 serial10 = &uart11;
40 serial11 = &uart12;
41 serial12 = &uart13;
42 };
43
44 cpus {
45 #address-cells = <1>;
46 #size-cells = <0>;
47 enable-method = "aspeed,ast2600-smp";
48
49 cpu@0 {
50 compatible = "arm,cortex-a7";
51 device_type = "cpu";
52 reg = <0xf00>;
53 };
54
55 cpu@1 {
56 compatible = "arm,cortex-a7";
57 device_type = "cpu";
58 reg = <0xf01>;
59 };
60
61 };
62
63 timer {
64 compatible = "arm,armv7-timer";
65 interrupt-parent = <&gic>;
66 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
67 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
68 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
69 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
70 };
71
72 reserved-memory {
73 #address-cells = <1>;
74 #size-cells = <1>;
75 ranges;
76
77 gfx_memory: framebuffer {
78 size = <0x01000000>;
79 alignment = <0x01000000>;
80 compatible = "shared-dma-pool";
81 reusable;
82 };
83
84 video_memory: video {
85 size = <0x04000000>;
86 alignment = <0x01000000>;
87 compatible = "shared-dma-pool";
88 no-map;
89 };
90 };
91
92 ahb {
93 compatible = "simple-bus";
94 #address-cells = <1>;
95 #size-cells = <1>;
96 device_type = "soc";
97 ranges;
98
99 gic: interrupt-controller@40461000 {
100 compatible = "arm,cortex-a7-gic";
101 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
102 #interrupt-cells = <3>;
103 interrupt-controller;
104 interrupt-parent = <&gic>;
105 reg = <0x40461000 0x1000>,
106 <0x40462000 0x1000>,
107 <0x40464000 0x2000>,
108 <0x40466000 0x2000>;
109 };
110
111 ahbc: ahbc@1e600000 {
112 compatible = "aspeed,aspeed-ahbc";
113 reg = < 0x1e600000 0x100>;
114 };
115
Billy Tsai2193dc62022-03-08 11:04:07 +0800[diff] [blame^]116 pwm_tach: pwm_tach@1e610000 {
117 compatible = "aspeed,ast2600-pwm-tach", "simple-mfd", "syscon";
118 reg = <0x1e610000 0x100>;
119 clocks = <&scu ASPEED_CLK_AHB>;
120 resets = <&rst ASPEED_RESET_PWM>;
121
122 pwm: pwm {
123 compatible = "aspeed,ast2600-pwm";
124 #pwm-cells = <3>;
125 #address-cells = <1>;
126 #size-cells = <0>;
127 status = "disabled";
128 };
129 };
130
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]131 fmc: flash-controller@1e620000 {
132 reg = < 0x1e620000 0xc4
133 0x20000000 0x10000000 >;
134 #address-cells = <1>;
135 #size-cells = <0>;
136 compatible = "aspeed,ast2600-fmc";
137 status = "disabled";
138 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
139 clocks = <&scu ASPEED_CLK_AHB>;
140 num-cs = <3>;
141 flash@0 {
142 reg = < 0 >;
143 compatible = "jedec,spi-nor";
144 status = "disabled";
145 };
146 flash@1 {
147 reg = < 1 >;
148 compatible = "jedec,spi-nor";
149 status = "disabled";
150 };
151 flash@2 {
152 reg = < 2 >;
153 compatible = "jedec,spi-nor";
154 status = "disabled";
155 };
156 };
157
158 spi1: flash-controller@1e630000 {
159 reg = < 0x1e630000 0xc4
160 0x30000000 0x08000000 >;
161 #address-cells = <1>;
162 #size-cells = <0>;
163 compatible = "aspeed,ast2600-spi";
164 clocks = <&scu ASPEED_CLK_AHB>;
165 num-cs = <2>;
166 status = "disabled";
167 flash@0 {
168 reg = < 0 >;
169 compatible = "jedec,spi-nor";
170 status = "disabled";
171 };
172 flash@1 {
173 reg = < 1 >;
174 compatible = "jedec,spi-nor";
175 status = "disabled";
176 };
177 };
178
179 spi2: flash-controller@1e631000 {
180 reg = < 0x1e631000 0xc4
181 0x50000000 0x08000000 >;
182 #address-cells = <1>;
183 #size-cells = <0>;
184 compatible = "aspeed,ast2600-spi";
185 clocks = <&scu ASPEED_CLK_AHB>;
186 num-cs = <3>;
187 status = "disabled";
188 flash@0 {
189 reg = < 0 >;
190 compatible = "jedec,spi-nor";
191 status = "disabled";
192 };
193 flash@1 {
194 reg = < 1 >;
195 compatible = "jedec,spi-nor";
196 status = "disabled";
197 };
198 flash@2 {
199 reg = < 2 >;
200 compatible = "jedec,spi-nor";
201 status = "disabled";
202 };
203 };
204
Joel Stanleyd18ef4f2021-10-27 14:17:28 +0800[diff] [blame]205 hace: hace@1e6d0000 {
206 compatible = "aspeed,ast2600-hace";
207 reg = <0x1e6d0000 0x200>;
208 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
209 clocks = <&scu ASPEED_CLK_GATE_YCLK>;
210 status = "disabled";
211 };
212
Chia-Wei Wang3435a3f2021-10-27 14:17:31 +0800[diff] [blame]213 acry: acry@1e6fa000 {
214 compatible = "aspeed,ast2600-acry";
215 reg = <0x1e6fa000 0x1000>,
216 <0x1e710000 0x10000>;
217 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
218 clocks = <&scu ASPEED_CLK_GATE_RSACLK>;
219 status = "disabled";
220 };
221
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]222 edac: sdram@1e6e0000 {
223 compatible = "aspeed,ast2600-sdram-edac";
224 reg = <0x1e6e0000 0x174>;
225 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
226 };
227
Dylan Hung82f25842021-12-09 10:12:26 +0800[diff] [blame]228 mdio: bus@1e650000 {
229 compatible = "simple-bus";
230 #address-cells = <1>;
231 #size-cells = <1>;
232 ranges = <0 0x1e650000 0x100>;
233
234 mdio0: mdio@0 {
235 compatible = "aspeed,ast2600-mdio";
236 reg = <0 0x8>;
237 resets = <&rst ASPEED_RESET_MII>;
238 pinctrl-names = "default";
239 pinctrl-0 = <&pinctrl_mdio1_default>;
240 status = "disabled";
241 };
242
243 mdio1: mdio@8 {
244 compatible = "aspeed,ast2600-mdio";
245 reg = <0x8 0x8>;
246 resets = <&rst ASPEED_RESET_MII>;
247 pinctrl-names = "default";
248 pinctrl-0 = <&pinctrl_mdio2_default>;
249 status = "disabled";
250 };
251
252 mdio2: mdio@10 {
253 compatible = "aspeed,ast2600-mdio";
254 reg = <0x10 0x8>;
255 resets = <&rst ASPEED_RESET_MII>;
256 pinctrl-names = "default";
257 pinctrl-0 = <&pinctrl_mdio3_default>;
258 status = "disabled";
259 };
260
261 mdio3: mdio@18 {
262 compatible = "aspeed,ast2600-mdio";
263 reg = <0x18 0x8>;
264 resets = <&rst ASPEED_RESET_MII>;
265 pinctrl-names = "default";
266 pinctrl-0 = <&pinctrl_mdio4_default>;
267 status = "disabled";
268 };
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]269 };
270
271 mac0: ftgmac@1e660000 {
272 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
273 reg = <0x1e660000 0x180>, <0x1e650000 0x4>;
274 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
275 clocks = <&scu ASPEED_CLK_GATE_MAC1CLK>;
276 status = "disabled";
277 };
278
279 mac1: ftgmac@1e680000 {
280 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
281 reg = <0x1e680000 0x180>, <0x1e650008 0x4>;
282 #address-cells = <1>;
283 #size-cells = <0>;
284 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
285 clocks = <&scu ASPEED_CLK_GATE_MAC2CLK>;
286 status = "disabled";
287 };
288
289 mac2: ftgmac@1e670000 {
290 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
291 reg = <0x1e670000 0x180>, <0x1e650010 0x4>;
292 #address-cells = <1>;
293 #size-cells = <0>;
294 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
295 clocks = <&scu ASPEED_CLK_GATE_MAC3CLK>;
296 status = "disabled";
297 };
298
299 mac3: ftgmac@1e690000 {
300 compatible = "aspeed,ast2600-mac", "faraday,ftgmac100";
301 reg = <0x1e690000 0x180>, <0x1e650018 0x4>;
302 #address-cells = <1>;
303 #size-cells = <0>;
304 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
305 clocks = <&scu ASPEED_CLK_GATE_MAC4CLK>;
306 status = "disabled";
307 };
308
309 ehci0: usb@1e6a1000 {
310 compatible = "aspeed,aspeed-ehci", "usb-ehci";
311 reg = <0x1e6a1000 0x100>;
312 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
313 clocks = <&scu ASPEED_CLK_GATE_USBPORT1CLK>;
314 pinctrl-names = "default";
315 pinctrl-0 = <&pinctrl_usb2ah_default>;
316 status = "disabled";
317 };
318
319 ehci1: usb@1e6a3000 {
320 compatible = "aspeed,aspeed-ehci", "usb-ehci";
321 reg = <0x1e6a3000 0x100>;
322 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
323 clocks = <&scu ASPEED_CLK_GATE_USBPORT2CLK>;
324 pinctrl-names = "default";
325 pinctrl-0 = <&pinctrl_usb2bh_default>;
326 status = "disabled";
327 };
328
329 apb {
330 compatible = "simple-bus";
331 #address-cells = <1>;
332 #size-cells = <1>;
333 ranges;
334
335 syscon: syscon@1e6e2000 {
336 compatible = "aspeed,g6-scu", "syscon", "simple-mfd";
337 reg = <0x1e6e2000 0x1000>;
338 #address-cells = <1>;
339 #size-cells = <1>;
340 #clock-cells = <1>;
341 #reset-cells = <1>;
342 ranges = <0 0x1e6e2000 0x1000>;
343
344 pinctrl: pinctrl {
345 compatible = "aspeed,g6-pinctrl";
346 aspeed,external-nodes = <&gfx &lhc>;
347
348 };
349
350 vga_scratch: scratch {
351 compatible = "aspeed,bmc-misc";
352 };
353
354 scu_ic0: interrupt-controller@0 {
355 #interrupt-cells = <1>;
356 compatible = "aspeed,ast2600-scu-ic";
357 reg = <0x560 0x10>;
358 interrupt-parent = <&gic>;
359 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
360 interrupt-controller;
361 };
362
363 scu_ic1: interrupt-controller@1 {
364 #interrupt-cells = <1>;
365 compatible = "aspeed,ast2600-scu-ic";
366 reg = <0x570 0x10>;
367 interrupt-parent = <&gic>;
368 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
369 interrupt-controller;
370 };
371
372 };
373
374 smp-memram@0 {
375 compatible = "aspeed,ast2600-smpmem", "syscon";
376 reg = <0x1e6e2180 0x40>;
377 };
378
379 gfx: display@1e6e6000 {
380 compatible = "aspeed,ast2500-gfx", "syscon";
381 reg = <0x1e6e6000 0x1000>;
382 reg-io-width = <4>;
383 };
384
385 pcie_bridge0: pcie@1e6ed000 {
386 compatible = "aspeed,ast2600-pcie";
387 #address-cells = <3>;
388 #size-cells = <2>;
389 reg = <0x1e6ed000 0x100>;
390 ranges = <0x81000000 0x0 0x0 0x0 0x0 0x10000>,
391 <0x82000000 0x0 0x60000000 0x60000000 0x0 0x10000000>;
392 device_type = "pci";
393 bus-range = <0x00 0xff>;
394 resets = <&rst ASPEED_RESET_PCIE_DEV_O>;
395 cfg-handle = <&pcie_cfg0>;
396 pinctrl-names = "default";
397 pinctrl-0 = <&pinctrl_pcie0rc_default>;
398
399 status = "disabled";
400 };
401
402 pcie_bridge1: pcie@1e6ed200 {
403 compatible = "aspeed,ast2600-pcie";
404 #address-cells = <3>;
405 #size-cells = <2>;
406 reg = <0x1e6ed200 0x100>;
407 ranges = <0x81000000 0x0 0x0 0x10000 0x00 0x10000>,
408 <0x82000000 0x0 0x70000000 0x70000000 0x0 0x10000000>;
409 device_type = "pci";
410 bus-range = <0x00 0xff>;
411 resets = <&rst ASPEED_RESET_PCIE_RC_O>;
412 cfg-handle = <&pcie_cfg1>;
413 pinctrl-names = "default";
414 pinctrl-0 = <&pinctrl_pcie1rc_default>;
415
416 status = "disabled";
417 };
418
419 sdhci: sdhci@1e740000 {
420 #interrupt-cells = <1>;
421 compatible = "aspeed,aspeed-sdhci-irq", "simple-mfd";
422 reg = <0x1e740000 0x1000>;
423 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
424 interrupt-controller;
425 clocks = <&scu ASPEED_CLK_GATE_SDCLK>,
426 <&scu ASPEED_CLK_GATE_SDEXTCLK>;
427 clock-names = "ctrlclk", "extclk";
428 #address-cells = <1>;
429 #size-cells = <1>;
430 ranges = <0x0 0x1e740000 0x1000>;
431
432 sdhci_slot0: sdhci_slot0@100 {
433 compatible = "aspeed,sdhci-ast2600";
434 reg = <0x100 0x100>;
435 interrupts = <0>;
436 interrupt-parent = <&sdhci>;
437 sdhci,auto-cmd12;
438 clocks = <&scu ASPEED_CLK_SDIO>;
439 status = "disabled";
440 };
441
442 sdhci_slot1: sdhci_slot1@200 {
443 compatible = "aspeed,sdhci-ast2600";
444 reg = <0x200 0x100>;
445 interrupts = <1>;
446 interrupt-parent = <&sdhci>;
447 sdhci,auto-cmd12;
448 clocks = <&scu ASPEED_CLK_SDIO>;
449 status = "disabled";
450 };
451 };
452
453 emmc: emmc@1e750000 {
454 #interrupt-cells = <1>;
455 compatible = "aspeed,aspeed-emmc-irq", "simple-mfd";
456 reg = <0x1e750000 0x1000>;
457 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
458 interrupt-controller;
459 clocks = <&scu ASPEED_CLK_GATE_EMMCCLK>,
460 <&scu ASPEED_CLK_GATE_EMMCEXTCLK>;
461 clock-names = "ctrlclk", "extclk";
462 #address-cells = <1>;
463 #size-cells = <1>;
464 ranges = <0x0 0x1e750000 0x1000>;
465
466 emmc_slot0: emmc_slot0@100 {
467 compatible = "aspeed,emmc-ast2600";
468 reg = <0x100 0x100>;
469 interrupts = <0>;
470 interrupt-parent = <&emmc>;
471 clocks = <&scu ASPEED_CLK_EMMC>;
472 status = "disabled";
473 };
474 };
475
476 h2x: h2x@1e770000 {
477 compatible = "aspeed,ast2600-h2x";
478 reg = <0x1e770000 0x100>;
479 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
480 resets = <&rst ASPEED_RESET_H2X>;
481 #address-cells = <1>;
482 #size-cells = <1>;
483 ranges = <0x0 0x1e770000 0x100>;
484
485 status = "disabled";
486
487 pcie_cfg0: cfg0@80 {
488 reg = <0x80 0x80>;
489 compatible = "aspeed,ast2600-pcie-cfg";
490 };
491
492 pcie_cfg1: cfg1@C0 {
493 compatible = "aspeed,ast2600-pcie-cfg";
494 reg = <0xC0 0x80>;
495 };
496 };
497
498 gpio0: gpio@1e780000 {
499 compatible = "aspeed,ast2600-gpio";
500 reg = <0x1e780000 0x1000>;
501 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
502 #gpio-cells = <2>;
503 gpio-controller;
504 interrupt-controller;
505 gpio-ranges = <&pinctrl 0 0 220>;
506 ngpios = <208>;
507 };
508
509 gpio1: gpio@1e780800 {
510 compatible = "aspeed,ast2600-gpio";
511 reg = <0x1e780800 0x800>;
512 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
513 #gpio-cells = <2>;
514 gpio-controller;
515 interrupt-controller;
516 gpio-ranges = <&pinctrl 0 0 208>;
517 ngpios = <36>;
518 };
519
520 uart1: serial@1e783000 {
521 compatible = "ns16550a";
522 reg = <0x1e783000 0x20>;
523 reg-shift = <2>;
524 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
525 clocks = <&scu ASPEED_CLK_GATE_UART1CLK>;
526 clock-frequency = <1846154>;
527 no-loopback-test;
528 status = "disabled";
529 };
530
531 uart5: serial@1e784000 {
532 compatible = "ns16550a";
533 reg = <0x1e784000 0x1000>;
534 reg-shift = <2>;
535 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
536 clocks = <&scu ASPEED_CLK_GATE_UART5CLK>;
537 clock-frequency = <1846154>;
538 no-loopback-test;
539 status = "disabled";
540 };
541
542 wdt1: watchdog@1e785000 {
543 compatible = "aspeed,ast2600-wdt";
544 reg = <0x1e785000 0x40>;
Chia-Wei Wang12364cc2021-09-16 14:10:09 +0800[diff] [blame]545 status = "disabled";
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]546 };
547
548 wdt2: watchdog@1e785040 {
549 compatible = "aspeed,ast2600-wdt";
550 reg = <0x1e785040 0x40>;
Chia-Wei Wang12364cc2021-09-16 14:10:09 +0800[diff] [blame]551 status = "disabled";
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]552 };
553
554 wdt3: watchdog@1e785080 {
555 compatible = "aspeed,ast2600-wdt";
556 reg = <0x1e785080 0x40>;
Chia-Wei Wang12364cc2021-09-16 14:10:09 +0800[diff] [blame]557 status = "disabled";
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]558 };
559
560 wdt4: watchdog@1e7850C0 {
561 compatible = "aspeed,ast2600-wdt";
562 reg = <0x1e7850C0 0x40>;
Chia-Wei Wang12364cc2021-09-16 14:10:09 +0800[diff] [blame]563 status = "disabled";
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]564 };
565
566 lpc: lpc@1e789000 {
567 compatible = "aspeed,ast2600-lpc", "simple-mfd", "syscon";
568 reg = <0x1e789000 0x1000>;
569
570 #address-cells = <1>;
571 #size-cells = <1>;
572 ranges = <0x0 0x1e789000 0x1000>;
573
574 kcs1: kcs1@0 {
575 compatible = "aspeed,ast2600-kcs-bmc";
576 reg = <0x0 0x80>;
577 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
578 kcs_chan = <1>;
579 kcs_addr = <0xCA0>;
580 status = "disabled";
581 };
582
583 kcs2: kcs2@0 {
584 compatible = "aspeed,ast2600-kcs-bmc";
585 reg = <0x0 0x80>;
586 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
587 kcs_chan = <2>;
588 kcs_addr = <0xCA8>;
589 status = "disabled";
590 };
591
592 kcs3: kcs3@0 {
593 compatible = "aspeed,ast2600-kcs-bmc";
594 reg = <0x0 0x80>;
595 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
596 kcs_chan = <3>;
597 kcs_addr = <0xCA2>;
598 };
599
600 kcs4: kcs4@0 {
601 compatible = "aspeed,ast2600-kcs-bmc";
602 reg = <0x0 0x120>;
603 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
604 kcs_chan = <4>;
605 kcs_addr = <0xCA4>;
606 status = "disabled";
607 };
608
609 lpc_ctrl: lpc-ctrl@80 {
610 compatible = "aspeed,ast2600-lpc-ctrl";
611 reg = <0x80 0x80>;
612 status = "disabled";
613 };
614
615 lpc_snoop: lpc-snoop@80 {
616 compatible = "aspeed,ast2600-lpc-snoop";
617 reg = <0x80 0x80>;
618 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
619 status = "disabled";
620 };
621
622 lhc: lhc@a0 {
623 compatible = "aspeed,ast2600-lhc";
624 reg = <0xa0 0x24 0xc8 0x8>;
625 };
626
627 lpc_reset: reset-controller@98 {
628 compatible = "aspeed,ast2600-lpc-reset";
629 reg = <0x98 0x4>;
630 #reset-cells = <1>;
631 status = "disabled";
632 };
633
634 ibt: ibt@140 {
635 compatible = "aspeed,ast2600-ibt-bmc";
636 reg = <0x140 0x18>;
637 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
638 status = "disabled";
639 };
640
641 sio_regs: regs {
642 compatible = "aspeed,bmc-misc";
643 };
644
645 mbox: mbox@200 {
646 compatible = "aspeed,ast2600-mbox";
647 reg = <0x200 0x5c>;
648 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
649 #mbox-cells = <1>;
650 status = "disabled";
651 };
652 };
653
654 uart2: serial@1e78d000 {
655 compatible = "ns16550a";
656 reg = <0x1e78d000 0x20>;
657 reg-shift = <2>;
658 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
659 clocks = <&scu ASPEED_CLK_GATE_UART2CLK>;
660 clock-frequency = <1846154>;
661 no-loopback-test;
662 status = "disabled";
663 };
664
665 uart3: serial@1e78e000 {
666 compatible = "ns16550a";
667 reg = <0x1e78e000 0x20>;
668 reg-shift = <2>;
669 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
670 clocks = <&scu ASPEED_CLK_GATE_UART3CLK>;
671 clock-frequency = <1846154>;
672 no-loopback-test;
673 status = "disabled";
674 };
675
676 uart4: serial@1e78f000 {
677 compatible = "ns16550a";
678 reg = <0x1e78f000 0x20>;
679 reg-shift = <2>;
680 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
681 clocks = <&scu ASPEED_CLK_GATE_UART4CLK>;
682 clock-frequency = <1846154>;
683 no-loopback-test;
684 status = "disabled";
685 };
686
687 i2c: bus@1e78a000 {
688 compatible = "simple-bus";
689 #address-cells = <1>;
690 #size-cells = <1>;
691 ranges = <0 0x1e78a000 0x1000>;
692 };
693
694 fsim0: fsi@1e79b000 {
695 compatible = "aspeed,ast2600-fsi-master", "fsi-master";
696 reg = <0x1e79b000 0x94>;
697 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
698 pinctrl-names = "default";
699 pinctrl-0 = <&pinctrl_fsi1_default>;
700 clocks = <&scu ASPEED_CLK_GATE_FSICLK>;
701 status = "disabled";
702 };
703
704 fsim1: fsi@1e79b100 {
705 compatible = "aspeed,ast2600-fsi-master", "fsi-master";
706 reg = <0x1e79b100 0x94>;
707 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
708 pinctrl-names = "default";
709 pinctrl-0 = <&pinctrl_fsi2_default>;
710 clocks = <&scu ASPEED_CLK_GATE_FSICLK>;
711 status = "disabled";
712 };
713
714 uart6: serial@1e790000 {
715 compatible = "ns16550a";
716 reg = <0x1e790000 0x20>;
717 reg-shift = <2>;
718 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
719 clocks = <&scu ASPEED_CLK_GATE_UART6CLK>;
720 clock-frequency = <1846154>;
721 no-loopback-test;
722 status = "disabled";
723 };
724
725 uart7: serial@1e790100 {
726 compatible = "ns16550a";
727 reg = <0x1e790100 0x20>;
728 reg-shift = <2>;
729 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
730 clocks = <&scu ASPEED_CLK_GATE_UART7CLK>;
731 clock-frequency = <1846154>;
732 no-loopback-test;
733 status = "disabled";
734 };
735
736 uart8: serial@1e790200 {
737 compatible = "ns16550a";
738 reg = <0x1e790200 0x20>;
739 reg-shift = <2>;
740 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
741 clocks = <&scu ASPEED_CLK_GATE_UART8CLK>;
742 clock-frequency = <1846154>;
743 no-loopback-test;
744 status = "disabled";
745 };
746
747 uart9: serial@1e790300 {
748 compatible = "ns16550a";
749 reg = <0x1e790300 0x20>;
750 reg-shift = <2>;
751 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
752 clocks = <&scu ASPEED_CLK_GATE_UART9CLK>;
753 clock-frequency = <1846154>;
754 no-loopback-test;
755 status = "disabled";
756 };
757
758 uart10: serial@1e790400 {
759 compatible = "ns16550a";
760 reg = <0x1e790400 0x20>;
761 reg-shift = <2>;
762 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
763 clocks = <&scu ASPEED_CLK_GATE_UART10CLK>;
764 clock-frequency = <1846154>;
765 no-loopback-test;
766 status = "disabled";
767 };
768
769 uart11: serial@1e790500 {
770 compatible = "ns16550a";
771 reg = <0x1e790400 0x20>;
772 reg-shift = <2>;
773 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
774 clocks = <&scu ASPEED_CLK_GATE_UART11CLK>;
775 clock-frequency = <1846154>;
776 no-loopback-test;
777 status = "disabled";
778 };
779
780 uart12: serial@1e790600 {
781 compatible = "ns16550a";
782 reg = <0x1e790600 0x20>;
783 reg-shift = <2>;
784 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
785 clocks = <&scu ASPEED_CLK_GATE_UART12CLK>;
786 clock-frequency = <1846154>;
787 no-loopback-test;
788 status = "disabled";
789 };
790
791 uart13: serial@1e790700 {
792 compatible = "ns16550a";
793 reg = <0x1e790700 0x20>;
794 reg-shift = <2>;
795 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
796 clocks = <&scu ASPEED_CLK_GATE_UART13CLK>;
797 clock-frequency = <1846154>;
798 no-loopback-test;
799 status = "disabled";
800 };
801
802 display_port: dp@1e6eb000 {
803 compatible = "aspeed,ast2600-displayport";
804 reg = <0x1e6eb000 0x200>;
805 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
806 resets = <&rst ASPEED_RESET_DP> ,<&rst ASPEED_RESET_DP_MCU>;
807 status = "disabled";
808 };
809
810 };
811
812 };
813
814};
815
816&i2c {
817 i2cglobal: i2cg@00 {
818 compatible = "aspeed,ast2600-i2c-global";
819 reg = <0x0 0x40>;
820 resets = <&rst ASPEED_RESET_I2C>;
821#if 0
822 new-mode;
823#endif
824 };
825
826 i2c0: i2c@80 {
827 #address-cells = <1>;
828 #size-cells = <0>;
829 #interrupt-cells = <1>;
830
831 reg = <0x80 0x80 0xC00 0x20>;
832 compatible = "aspeed,ast2600-i2c-bus";
833 bus-frequency = <100000>;
834 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
835 clocks = <&scu ASPEED_CLK_APB2>;
836 status = "disabled";
837 };
838
839 i2c1: i2c@100 {
840 #address-cells = <1>;
841 #size-cells = <0>;
842 #interrupt-cells = <1>;
843
844 reg = <0x100 0x80 0xC20 0x20>;
845 compatible = "aspeed,ast2600-i2c-bus";
846 bus-frequency = <100000>;
847 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
848 clocks = <&scu ASPEED_CLK_APB2>;
849 status = "disabled";
850 };
851
852 i2c2: i2c@180 {
853 #address-cells = <1>;
854 #size-cells = <0>;
855 #interrupt-cells = <1>;
856
857 reg = <0x180 0x80 0xC40 0x20>;
858 compatible = "aspeed,ast2600-i2c-bus";
859 bus-frequency = <100000>;
860 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
861 clocks = <&scu ASPEED_CLK_APB2>;
862 };
863
864 i2c3: i2c@200 {
865 #address-cells = <1>;
866 #size-cells = <0>;
867 #interrupt-cells = <1>;
868
869 reg = <0x200 0x40 0xC60 0x20>;
870 compatible = "aspeed,ast2600-i2c-bus";
871 bus-frequency = <100000>;
872 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
873 clocks = <&scu ASPEED_CLK_APB2>;
874 };
875
876 i2c4: i2c@280 {
877 #address-cells = <1>;
878 #size-cells = <0>;
879 #interrupt-cells = <1>;
880
881 reg = <0x280 0x80 0xC80 0x20>;
882 compatible = "aspeed,ast2600-i2c-bus";
883 bus-frequency = <100000>;
884 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
885 clocks = <&scu ASPEED_CLK_APB2>;
886 };
887
888 i2c5: i2c@300 {
889 #address-cells = <1>;
890 #size-cells = <0>;
891 #interrupt-cells = <1>;
892
893 reg = <0x300 0x40 0xCA0 0x20>;
894 compatible = "aspeed,ast2600-i2c-bus";
895 bus-frequency = <100000>;
896 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
897 clocks = <&scu ASPEED_CLK_APB2>;
898 };
899
900 i2c6: i2c@380 {
901 #address-cells = <1>;
902 #size-cells = <0>;
903 #interrupt-cells = <1>;
904
905 reg = <0x380 0x80 0xCC0 0x20>;
906 compatible = "aspeed,ast2600-i2c-bus";
907 bus-frequency = <100000>;
908 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
909 clocks = <&scu ASPEED_CLK_APB2>;
910 };
911
912 i2c7: i2c@400 {
913 #address-cells = <1>;
914 #size-cells = <0>;
915 #interrupt-cells = <1>;
916
917 reg = <0x400 0x80 0xCE0 0x20>;
918 compatible = "aspeed,ast2600-i2c-bus";
919 bus-frequency = <100000>;
920 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
921 clocks = <&scu ASPEED_CLK_APB2>;
922 };
923
924 i2c8: i2c@480 {
925 #address-cells = <1>;
926 #size-cells = <0>;
927 #interrupt-cells = <1>;
928
929 reg = <0x480 0x80 0xD00 0x20>;
930 compatible = "aspeed,ast2600-i2c-bus";
931 bus-frequency = <100000>;
932 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
933 clocks = <&scu ASPEED_CLK_APB2>;
934 };
935
936 i2c9: i2c@500 {
937 #address-cells = <1>;
938 #size-cells = <0>;
939 #interrupt-cells = <1>;
940
941 reg = <0x500 0x80 0xD20 0x20>;
942 compatible = "aspeed,ast2600-i2c-bus";
943 bus-frequency = <100000>;
944 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
945 clocks = <&scu ASPEED_CLK_APB2>;
946 status = "disabled";
947 };
948
949 i2c10: i2c@580 {
950 #address-cells = <1>;
951 #size-cells = <0>;
952 #interrupt-cells = <1>;
953
954 reg = <0x580 0x80 0xD40 0x20>;
955 compatible = "aspeed,ast2600-i2c-bus";
956 bus-frequency = <100000>;
957 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
958 clocks = <&scu ASPEED_CLK_APB2>;
959 status = "disabled";
960 };
961
962 i2c11: i2c@600 {
963 #address-cells = <1>;
964 #size-cells = <0>;
965 #interrupt-cells = <1>;
966
967 reg = <0x600 0x80 0xD60 0x20>;
968 compatible = "aspeed,ast2600-i2c-bus";
969 bus-frequency = <100000>;
970 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
971 clocks = <&scu ASPEED_CLK_APB2>;
972 status = "disabled";
973 };
974
975 i2c12: i2c@680 {
976 #address-cells = <1>;
977 #size-cells = <0>;
978 #interrupt-cells = <1>;
979
980 reg = <0x680 0x80 0xD80 0x20>;
981 compatible = "aspeed,ast2600-i2c-bus";
982 bus-frequency = <100000>;
983 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
984 clocks = <&scu ASPEED_CLK_APB2>;
985 status = "disabled";
986 };
987
988 i2c13: i2c@700 {
989 #address-cells = <1>;
990 #size-cells = <0>;
991 #interrupt-cells = <1>;
992
993 reg = <0x700 0x80 0xDA0 0x20>;
994 compatible = "aspeed,ast2600-i2c-bus";
995 bus-frequency = <100000>;
996 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
997 clocks = <&scu ASPEED_CLK_APB2>;
998 status = "disabled";
999 };
1000
1001 i2c14: i2c@780 {
1002 #address-cells = <1>;
1003 #size-cells = <0>;
1004 #interrupt-cells = <1>;
1005
1006 reg = <0x780 0x80 0xDC0 0x20>;
1007 compatible = "aspeed,ast2600-i2c-bus";
1008 bus-frequency = <100000>;
1009 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
1010 clocks = <&scu ASPEED_CLK_APB2>;
1011 status = "disabled";
1012 };
1013
1014 i2c15: i2c@800 {
1015 #address-cells = <1>;
1016 #size-cells = <0>;
1017 #interrupt-cells = <1>;
1018
1019 reg = <0x800 0x80 0xDE0 0x20>;
1020 compatible = "aspeed,ast2600-i2c-bus";
1021 bus-frequency = <100000>;
1022 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
1023 clocks = <&scu ASPEED_CLK_APB2>;
1024 status = "disabled";
1025 };
1026
1027};
1028
1029&pinctrl {
1030 pinctrl_fmcquad_default: fmcquad_default {
1031 function = "FMCQUAD";
1032 groups = "FMCQUAD";
1033 };
1034
1035 pinctrl_spi1_default: spi1_default {
1036 function = "SPI1";
1037 groups = "SPI1";
1038 };
1039
1040 pinctrl_spi1abr_default: spi1abr_default {
1041 function = "SPI1ABR";
1042 groups = "SPI1ABR";
1043 };
1044
1045 pinctrl_spi1cs1_default: spi1cs1_default {
1046 function = "SPI1CS1";
1047 groups = "SPI1CS1";
1048 };
1049
1050 pinctrl_spi1wp_default: spi1wp_default {
1051 function = "SPI1WP";
1052 groups = "SPI1WP";
1053 };
1054
1055 pinctrl_spi1quad_default: spi1quad_default {
1056 function = "SPI1QUAD";
1057 groups = "SPI1QUAD";
1058 };
1059
1060 pinctrl_spi2_default: spi2_default {
1061 function = "SPI2";
1062 groups = "SPI2";
1063 };
1064
1065 pinctrl_spi2cs1_default: spi2cs1_default {
1066 function = "SPI2CS1";
1067 groups = "SPI2CS1";
1068 };
1069
1070 pinctrl_spi2cs2_default: spi2cs2_default {
1071 function = "SPI2CS2";
1072 groups = "SPI2CS2";
1073 };
1074
1075 pinctrl_spi2quad_default: spi2quad_default {
1076 function = "SPI2QUAD";
1077 groups = "SPI2QUAD";
1078 };
1079
1080 pinctrl_acpi_default: acpi_default {
1081 function = "ACPI";
1082 groups = "ACPI";
1083 };
1084
1085 pinctrl_adc0_default: adc0_default {
1086 function = "ADC0";
1087 groups = "ADC0";
1088 };
1089
1090 pinctrl_adc1_default: adc1_default {
1091 function = "ADC1";
1092 groups = "ADC1";
1093 };
1094
1095 pinctrl_adc10_default: adc10_default {
1096 function = "ADC10";
1097 groups = "ADC10";
1098 };
1099
1100 pinctrl_adc11_default: adc11_default {
1101 function = "ADC11";
1102 groups = "ADC11";
1103 };
1104
1105 pinctrl_adc12_default: adc12_default {
1106 function = "ADC12";
1107 groups = "ADC12";
1108 };
1109
1110 pinctrl_adc13_default: adc13_default {
1111 function = "ADC13";
1112 groups = "ADC13";
1113 };
1114
1115 pinctrl_adc14_default: adc14_default {
1116 function = "ADC14";
1117 groups = "ADC14";
1118 };
1119
1120 pinctrl_adc15_default: adc15_default {
1121 function = "ADC15";
1122 groups = "ADC15";
1123 };
1124
1125 pinctrl_adc2_default: adc2_default {
1126 function = "ADC2";
1127 groups = "ADC2";
1128 };
1129
1130 pinctrl_adc3_default: adc3_default {
1131 function = "ADC3";
1132 groups = "ADC3";
1133 };
1134
1135 pinctrl_adc4_default: adc4_default {
1136 function = "ADC4";
1137 groups = "ADC4";
1138 };
1139
1140 pinctrl_adc5_default: adc5_default {
1141 function = "ADC5";
1142 groups = "ADC5";
1143 };
1144
1145 pinctrl_adc6_default: adc6_default {
1146 function = "ADC6";
1147 groups = "ADC6";
1148 };
1149
1150 pinctrl_adc7_default: adc7_default {
1151 function = "ADC7";
1152 groups = "ADC7";
1153 };
1154
1155 pinctrl_adc8_default: adc8_default {
1156 function = "ADC8";
1157 groups = "ADC8";
1158 };
1159
1160 pinctrl_adc9_default: adc9_default {
1161 function = "ADC9";
1162 groups = "ADC9";
1163 };
1164
1165 pinctrl_bmcint_default: bmcint_default {
1166 function = "BMCINT";
1167 groups = "BMCINT";
1168 };
1169
1170 pinctrl_ddcclk_default: ddcclk_default {
1171 function = "DDCCLK";
1172 groups = "DDCCLK";
1173 };
1174
1175 pinctrl_ddcdat_default: ddcdat_default {
1176 function = "DDCDAT";
1177 groups = "DDCDAT";
1178 };
1179
1180 pinctrl_espi_default: espi_default {
1181 function = "ESPI";
1182 groups = "ESPI";
1183 };
1184
1185 pinctrl_fsi1_default: fsi1_default {
1186 function = "FSI1";
1187 groups = "FSI1";
1188 };
1189
1190 pinctrl_fsi2_default: fsi2_default {
1191 function = "FSI2";
1192 groups = "FSI2";
1193 };
1194
1195 pinctrl_fwspics1_default: fwspics1_default {
1196 function = "FWSPICS1";
1197 groups = "FWSPICS1";
1198 };
1199
1200 pinctrl_fwspics2_default: fwspics2_default {
1201 function = "FWSPICS2";
1202 groups = "FWSPICS2";
1203 };
1204
1205 pinctrl_gpid0_default: gpid0_default {
1206 function = "GPID0";
1207 groups = "GPID0";
1208 };
1209
1210 pinctrl_gpid2_default: gpid2_default {
1211 function = "GPID2";
1212 groups = "GPID2";
1213 };
1214
1215 pinctrl_gpid4_default: gpid4_default {
1216 function = "GPID4";
1217 groups = "GPID4";
1218 };
1219
1220 pinctrl_gpid6_default: gpid6_default {
1221 function = "GPID6";
1222 groups = "GPID6";
1223 };
1224
1225 pinctrl_gpie0_default: gpie0_default {
1226 function = "GPIE0";
1227 groups = "GPIE0";
1228 };
1229
1230 pinctrl_gpie2_default: gpie2_default {
1231 function = "GPIE2";
1232 groups = "GPIE2";
1233 };
1234
1235 pinctrl_gpie4_default: gpie4_default {
1236 function = "GPIE4";
1237 groups = "GPIE4";
1238 };
1239
1240 pinctrl_gpie6_default: gpie6_default {
1241 function = "GPIE6";
1242 groups = "GPIE6";
1243 };
1244
1245 pinctrl_i2c1_default: i2c1_default {
1246 function = "I2C1";
1247 groups = "I2C1";
1248 };
1249 pinctrl_i2c2_default: i2c2_default {
1250 function = "I2C2";
1251 groups = "I2C2";
1252 };
1253
1254 pinctrl_i2c3_default: i2c3_default {
1255 function = "I2C3";
1256 groups = "I2C3";
1257 };
1258
1259 pinctrl_i2c4_default: i2c4_default {
1260 function = "I2C4";
1261 groups = "I2C4";
1262 };
1263
1264 pinctrl_i2c5_default: i2c5_default {
1265 function = "I2C5";
1266 groups = "I2C5";
1267 };
1268
1269 pinctrl_i2c6_default: i2c6_default {
1270 function = "I2C6";
1271 groups = "I2C6";
1272 };
1273
1274 pinctrl_i2c7_default: i2c7_default {
1275 function = "I2C7";
1276 groups = "I2C7";
1277 };
1278
1279 pinctrl_i2c8_default: i2c8_default {
1280 function = "I2C8";
1281 groups = "I2C8";
1282 };
1283
1284 pinctrl_i2c9_default: i2c9_default {
1285 function = "I2C9";
1286 groups = "I2C9";
1287 };
1288
1289 pinctrl_i2c10_default: i2c10_default {
1290 function = "I2C10";
1291 groups = "I2C10";
1292 };
1293
1294 pinctrl_i2c11_default: i2c11_default {
1295 function = "I2C11";
1296 groups = "I2C11";
1297 };
1298
1299 pinctrl_i2c12_default: i2c12_default {
1300 function = "I2C12";
1301 groups = "I2C12";
1302 };
1303
1304 pinctrl_i2c13_default: i2c13_default {
1305 function = "I2C13";
1306 groups = "I2C13";
1307 };
1308
1309 pinctrl_i2c14_default: i2c14_default {
1310 function = "I2C14";
1311 groups = "I2C14";
1312 };
1313
1314 pinctrl_i2c15_default: i2c15_default {
1315 function = "I2C15";
1316 groups = "I2C15";
1317 };
1318
1319 pinctrl_i2c16_default: i2c16_default {
1320 function = "I2C16";
1321 groups = "I2C16";
1322 };
1323
1324 pinctrl_lad0_default: lad0_default {
1325 function = "LAD0";
1326 groups = "LAD0";
1327 };
1328
1329 pinctrl_lad1_default: lad1_default {
1330 function = "LAD1";
1331 groups = "LAD1";
1332 };
1333
1334 pinctrl_lad2_default: lad2_default {
1335 function = "LAD2";
1336 groups = "LAD2";
1337 };
1338
1339 pinctrl_lad3_default: lad3_default {
1340 function = "LAD3";
1341 groups = "LAD3";
1342 };
1343
1344 pinctrl_lclk_default: lclk_default {
1345 function = "LCLK";
1346 groups = "LCLK";
1347 };
1348
1349 pinctrl_lframe_default: lframe_default {
1350 function = "LFRAME";
1351 groups = "LFRAME";
1352 };
1353
1354 pinctrl_lpchc_default: lpchc_default {
1355 function = "LPCHC";
1356 groups = "LPCHC";
1357 };
1358
1359 pinctrl_lpcpd_default: lpcpd_default {
1360 function = "LPCPD";
1361 groups = "LPCPD";
1362 };
1363
1364 pinctrl_lpcplus_default: lpcplus_default {
1365 function = "LPCPLUS";
1366 groups = "LPCPLUS";
1367 };
1368
1369 pinctrl_lpcpme_default: lpcpme_default {
1370 function = "LPCPME";
1371 groups = "LPCPME";
1372 };
1373
1374 pinctrl_lpcrst_default: lpcrst_default {
1375 function = "LPCRST";
1376 groups = "LPCRST";
1377 };
1378
1379 pinctrl_lpcsmi_default: lpcsmi_default {
1380 function = "LPCSMI";
1381 groups = "LPCSMI";
1382 };
1383
1384 pinctrl_lsirq_default: lsirq_default {
1385 function = "LSIRQ";
1386 groups = "LSIRQ";
1387 };
1388
1389 pinctrl_mac1link_default: mac1link_default {
1390 function = "MAC1LINK";
1391 groups = "MAC1LINK";
1392 };
1393
1394 pinctrl_mac2link_default: mac2link_default {
1395 function = "MAC2LINK";
1396 groups = "MAC2LINK";
1397 };
1398
1399 pinctrl_mac3link_default: mac3link_default {
1400 function = "MAC3LINK";
1401 groups = "MAC3LINK";
1402 };
1403
1404 pinctrl_mac4link_default: mac4link_default {
1405 function = "MAC4LINK";
1406 groups = "MAC4LINK";
1407 };
1408
1409 pinctrl_mdio1_default: mdio1_default {
1410 function = "MDIO1";
1411 groups = "MDIO1";
1412 };
1413
1414 pinctrl_mdio2_default: mdio2_default {
1415 function = "MDIO2";
1416 groups = "MDIO2";
1417 };
1418
1419 pinctrl_mdio3_default: mdio3_default {
1420 function = "MDIO3";
1421 groups = "MDIO3";
1422 };
1423
1424 pinctrl_mdio4_default: mdio4_default {
1425 function = "MDIO4";
1426 groups = "MDIO4";
1427 };
1428
1429 pinctrl_rmii1_default: rmii1_default {
1430 function = "RMII1";
1431 groups = "RMII1";
1432 };
1433
1434 pinctrl_rmii2_default: rmii2_default {
1435 function = "RMII2";
1436 groups = "RMII2";
1437 };
1438
1439 pinctrl_rmii3_default: rmii3_default {
1440 function = "RMII3";
1441 groups = "RMII3";
1442 };
1443
1444 pinctrl_rmii4_default: rmii4_default {
1445 function = "RMII4";
1446 groups = "RMII4";
1447 };
1448
1449 pinctrl_rmii1rclk_default: rmii1rclk_default {
1450 function = "RMII1RCLK";
1451 groups = "RMII1RCLK";
1452 };
1453
1454 pinctrl_rmii2rclk_default: rmii2rclk_default {
1455 function = "RMII2RCLK";
1456 groups = "RMII2RCLK";
1457 };
1458
1459 pinctrl_rmii3rclk_default: rmii3rclk_default {
1460 function = "RMII3RCLK";
1461 groups = "RMII3RCLK";
1462 };
1463
1464 pinctrl_rmii4rclk_default: rmii4rclk_default {
1465 function = "RMII4RCLK";
1466 groups = "RMII4RCLK";
1467 };
1468
1469 pinctrl_ncts1_default: ncts1_default {
1470 function = "NCTS1";
1471 groups = "NCTS1";
1472 };
1473
1474 pinctrl_ncts2_default: ncts2_default {
1475 function = "NCTS2";
1476 groups = "NCTS2";
1477 };
1478
1479 pinctrl_ncts3_default: ncts3_default {
1480 function = "NCTS3";
1481 groups = "NCTS3";
1482 };
1483
1484 pinctrl_ncts4_default: ncts4_default {
1485 function = "NCTS4";
1486 groups = "NCTS4";
1487 };
1488
1489 pinctrl_ndcd1_default: ndcd1_default {
1490 function = "NDCD1";
1491 groups = "NDCD1";
1492 };
1493
1494 pinctrl_ndcd2_default: ndcd2_default {
1495 function = "NDCD2";
1496 groups = "NDCD2";
1497 };
1498
1499 pinctrl_ndcd3_default: ndcd3_default {
1500 function = "NDCD3";
1501 groups = "NDCD3";
1502 };
1503
1504 pinctrl_ndcd4_default: ndcd4_default {
1505 function = "NDCD4";
1506 groups = "NDCD4";
1507 };
1508
1509 pinctrl_ndsr1_default: ndsr1_default {
1510 function = "NDSR1";
1511 groups = "NDSR1";
1512 };
1513
1514 pinctrl_ndsr2_default: ndsr2_default {
1515 function = "NDSR2";
1516 groups = "NDSR2";
1517 };
1518
1519 pinctrl_ndsr3_default: ndsr3_default {
1520 function = "NDSR3";
1521 groups = "NDSR3";
1522 };
1523
1524 pinctrl_ndsr4_default: ndsr4_default {
1525 function = "NDSR4";
1526 groups = "NDSR4";
1527 };
1528
1529 pinctrl_ndtr1_default: ndtr1_default {
1530 function = "NDTR1";
1531 groups = "NDTR1";
1532 };
1533
1534 pinctrl_ndtr2_default: ndtr2_default {
1535 function = "NDTR2";
1536 groups = "NDTR2";
1537 };
1538
1539 pinctrl_ndtr3_default: ndtr3_default {
1540 function = "NDTR3";
1541 groups = "NDTR3";
1542 };
1543
1544 pinctrl_ndtr4_default: ndtr4_default {
1545 function = "NDTR4";
1546 groups = "NDTR4";
1547 };
1548
1549 pinctrl_nri1_default: nri1_default {
1550 function = "NRI1";
1551 groups = "NRI1";
1552 };
1553
1554 pinctrl_nri2_default: nri2_default {
1555 function = "NRI2";
1556 groups = "NRI2";
1557 };
1558
1559 pinctrl_nri3_default: nri3_default {
1560 function = "NRI3";
1561 groups = "NRI3";
1562 };
1563
1564 pinctrl_nri4_default: nri4_default {
1565 function = "NRI4";
1566 groups = "NRI4";
1567 };
1568
1569 pinctrl_nrts1_default: nrts1_default {
1570 function = "NRTS1";
1571 groups = "NRTS1";
1572 };
1573
1574 pinctrl_nrts2_default: nrts2_default {
1575 function = "NRTS2";
1576 groups = "NRTS2";
1577 };
1578
1579 pinctrl_nrts3_default: nrts3_default {
1580 function = "NRTS3";
1581 groups = "NRTS3";
1582 };
1583
1584 pinctrl_nrts4_default: nrts4_default {
1585 function = "NRTS4";
1586 groups = "NRTS4";
1587 };
1588
1589 pinctrl_oscclk_default: oscclk_default {
1590 function = "OSCCLK";
1591 groups = "OSCCLK";
1592 };
1593
1594 pinctrl_pewake_default: pewake_default {
1595 function = "PEWAKE";
1596 groups = "PEWAKE";
1597 };
1598
1599 pinctrl_pnor_default: pnor_default {
1600 function = "PNOR";
1601 groups = "PNOR";
1602 };
1603
1604 pinctrl_pwm0_default: pwm0_default {
1605 function = "PWM0";
1606 groups = "PWM0";
1607 };
1608
1609 pinctrl_pwm1_default: pwm1_default {
1610 function = "PWM1";
1611 groups = "PWM1";
1612 };
1613
1614 pinctrl_pwm2_default: pwm2_default {
1615 function = "PWM2";
1616 groups = "PWM2";
1617 };
1618
1619 pinctrl_pwm3_default: pwm3_default {
1620 function = "PWM3";
1621 groups = "PWM3";
1622 };
1623
1624 pinctrl_pwm4_default: pwm4_default {
1625 function = "PWM4";
1626 groups = "PWM4";
1627 };
1628
1629 pinctrl_pwm5_default: pwm5_default {
1630 function = "PWM5";
1631 groups = "PWM5";
1632 };
1633
1634 pinctrl_pwm6_default: pwm6_default {
1635 function = "PWM6";
1636 groups = "PWM6";
1637 };
1638
1639 pinctrl_pwm7_default: pwm7_default {
1640 function = "PWM7";
1641 groups = "PWM7";
1642 };
1643
Billy Tsai01013c82022-03-08 11:04:06 +0800[diff] [blame]1644 pinctrl_pwm8g0_default: pwm8g0_default {
1645 function = "PWM8G0";
1646 groups = "PWM8G0";
1647 };
1648
1649 pinctrl_pwm8g1_default: pwm8g1_default {
1650 function = "PWM8G1";
1651 groups = "PWM8G1";
1652 };
1653
1654 pinctrl_pwm9g0_default: pwm9g0_default {
1655 function = "PWM9G0";
1656 groups = "PWM9G0";
1657 };
1658
1659 pinctrl_pwm9g1_default: pwm9g1_default {
1660 function = "PWM9G1";
1661 groups = "PWM9G1";
1662 };
1663
1664 pinctrl_pwm10g0_default: pwm10g0_default {
1665 function = "PWM10G0";
1666 groups = "PWM10G0";
1667 };
1668
1669 pinctrl_pwm10g1_default: pwm10g1_default {
1670 function = "PWM10G1";
1671 groups = "PWM10G1";
1672 };
1673
1674 pinctrl_pwm11g0_default: pwm11g0_default {
1675 function = "PWM11G0";
1676 groups = "PWM11G0";
1677 };
1678
1679 pinctrl_pwm11g1_default: pwm11g1_default {
1680 function = "PWM11G1";
1681 groups = "PWM11G1";
1682 };
1683
1684 pinctrl_pwm12g0_default: pwm12g0_default {
1685 function = "PWM12G0";
1686 groups = "PWM12G0";
1687 };
1688
1689 pinctrl_pwm12g1_default: pwm12g1_default {
1690 function = "PWM12G1";
1691 groups = "PWM12G1";
1692 };
1693
1694 pinctrl_pwm13g0_default: pwm13g0_default {
1695 function = "PWM13G0";
1696 groups = "PWM13G0";
1697 };
1698
1699 pinctrl_pwm13g1_default: pwm13g1_default {
1700 function = "PWM13G1";
1701 groups = "PWM13G1";
1702 };
1703
1704 pinctrl_pwm14g0_default: pwm14g0_default {
1705 function = "PWM14G0";
1706 groups = "PWM14G0";
1707 };
1708
1709 pinctrl_pwm14g1_default: pwm14g1_default {
1710 function = "PWM14G1";
1711 groups = "PWM14G1";
1712 };
1713
1714 pinctrl_pwm15g0_default: pwm15g0_default {
1715 function = "PWM15G0";
1716 groups = "PWM15G0";
1717 };
1718
1719 pinctrl_pwm15g1_default: pwm15g1_default {
1720 function = "PWM15G1";
1721 groups = "PWM15G1";
1722 };
1723
Chia-Wei, Wangb9f6e7b2020-12-14 13:54:27 +0800[diff] [blame]1724 pinctrl_rgmii1_default: rgmii1_default {
1725 function = "RGMII1";
1726 groups = "RGMII1";
1727 };
1728
1729 pinctrl_rgmii2_default: rgmii2_default {
1730 function = "RGMII2";
1731 groups = "RGMII2";
1732 };
1733
1734 pinctrl_rgmii3_default: rgmii3_default {
1735 function = "RGMII3";
1736 groups = "RGMII3";
1737 };
1738
1739 pinctrl_rgmii4_default: rgmii4_default {
1740 function = "RGMII4";
1741 groups = "RGMII4";
1742 };
1743
1744 pinctrl_rmii1_default: rmii1_default {
1745 function = "RMII1";
1746 groups = "RMII1";
1747 };
1748
1749 pinctrl_rmii2_default: rmii2_default {
1750 function = "RMII2";
1751 groups = "RMII2";
1752 };
1753
1754 pinctrl_rxd1_default: rxd1_default {
1755 function = "RXD1";
1756 groups = "RXD1";
1757 };
1758
1759 pinctrl_rxd2_default: rxd2_default {
1760 function = "RXD2";
1761 groups = "RXD2";
1762 };
1763
1764 pinctrl_rxd3_default: rxd3_default {
1765 function = "RXD3";
1766 groups = "RXD3";
1767 };
1768
1769 pinctrl_rxd4_default: rxd4_default {
1770 function = "RXD4";
1771 groups = "RXD4";
1772 };
1773
1774 pinctrl_salt1_default: salt1_default {
1775 function = "SALT1";
1776 groups = "SALT1";
1777 };
1778
1779 pinctrl_salt10_default: salt10_default {
1780 function = "SALT10";
1781 groups = "SALT10";
1782 };
1783
1784 pinctrl_salt11_default: salt11_default {
1785 function = "SALT11";
1786 groups = "SALT11";
1787 };
1788
1789 pinctrl_salt12_default: salt12_default {
1790 function = "SALT12";
1791 groups = "SALT12";
1792 };
1793
1794 pinctrl_salt13_default: salt13_default {
1795 function = "SALT13";
1796 groups = "SALT13";
1797 };
1798
1799 pinctrl_salt14_default: salt14_default {
1800 function = "SALT14";
1801 groups = "SALT14";
1802 };
1803
1804 pinctrl_salt2_default: salt2_default {
1805 function = "SALT2";
1806 groups = "SALT2";
1807 };
1808
1809 pinctrl_salt3_default: salt3_default {
1810 function = "SALT3";
1811 groups = "SALT3";
1812 };
1813
1814 pinctrl_salt4_default: salt4_default {
1815 function = "SALT4";
1816 groups = "SALT4";
1817 };
1818
1819 pinctrl_salt5_default: salt5_default {
1820 function = "SALT5";
1821 groups = "SALT5";
1822 };
1823
1824 pinctrl_salt6_default: salt6_default {
1825 function = "SALT6";
1826 groups = "SALT6";
1827 };
1828
1829 pinctrl_salt7_default: salt7_default {
1830 function = "SALT7";
1831 groups = "SALT7";
1832 };
1833
1834 pinctrl_salt8_default: salt8_default {
1835 function = "SALT8";
1836 groups = "SALT8";
1837 };
1838
1839 pinctrl_salt9_default: salt9_default {
1840 function = "SALT9";
1841 groups = "SALT9";
1842 };
1843
1844 pinctrl_scl1_default: scl1_default {
1845 function = "SCL1";
1846 groups = "SCL1";
1847 };
1848
1849 pinctrl_scl2_default: scl2_default {
1850 function = "SCL2";
1851 groups = "SCL2";
1852 };
1853
1854 pinctrl_sd1_default: sd1_default {
1855 function = "SD1";
1856 groups = "SD1";
1857 };
1858
1859 pinctrl_sd2_default: sd2_default {
1860 function = "SD2";
1861 groups = "SD2";
1862 };
1863
1864 pinctrl_emmc_default: emmc_default {
1865 function = "EMMC";
1866 groups = "EMMC";
1867 };
1868
1869 pinctrl_emmcg8_default: emmcg8_default {
1870 function = "EMMCG8";
1871 groups = "EMMCG8";
1872 };
1873
1874 pinctrl_sda1_default: sda1_default {
1875 function = "SDA1";
1876 groups = "SDA1";
1877 };
1878
1879 pinctrl_sda2_default: sda2_default {
1880 function = "SDA2";
1881 groups = "SDA2";
1882 };
1883
1884 pinctrl_sgps1_default: sgps1_default {
1885 function = "SGPS1";
1886 groups = "SGPS1";
1887 };
1888
1889 pinctrl_sgps2_default: sgps2_default {
1890 function = "SGPS2";
1891 groups = "SGPS2";
1892 };
1893
1894 pinctrl_sioonctrl_default: sioonctrl_default {
1895 function = "SIOONCTRL";
1896 groups = "SIOONCTRL";
1897 };
1898
1899 pinctrl_siopbi_default: siopbi_default {
1900 function = "SIOPBI";
1901 groups = "SIOPBI";
1902 };
1903
1904 pinctrl_siopbo_default: siopbo_default {
1905 function = "SIOPBO";
1906 groups = "SIOPBO";
1907 };
1908
1909 pinctrl_siopwreq_default: siopwreq_default {
1910 function = "SIOPWREQ";
1911 groups = "SIOPWREQ";
1912 };
1913
1914 pinctrl_siopwrgd_default: siopwrgd_default {
1915 function = "SIOPWRGD";
1916 groups = "SIOPWRGD";
1917 };
1918
1919 pinctrl_sios3_default: sios3_default {
1920 function = "SIOS3";
1921 groups = "SIOS3";
1922 };
1923
1924 pinctrl_sios5_default: sios5_default {
1925 function = "SIOS5";
1926 groups = "SIOS5";
1927 };
1928
1929 pinctrl_siosci_default: siosci_default {
1930 function = "SIOSCI";
1931 groups = "SIOSCI";
1932 };
1933
1934 pinctrl_spi1_default: spi1_default {
1935 function = "SPI1";
1936 groups = "SPI1";
1937 };
1938
1939 pinctrl_spi1cs1_default: spi1cs1_default {
1940 function = "SPI1CS1";
1941 groups = "SPI1CS1";
1942 };
1943
1944 pinctrl_spi1debug_default: spi1debug_default {
1945 function = "SPI1DEBUG";
1946 groups = "SPI1DEBUG";
1947 };
1948
1949 pinctrl_spi1passthru_default: spi1passthru_default {
1950 function = "SPI1PASSTHRU";
1951 groups = "SPI1PASSTHRU";
1952 };
1953
1954 pinctrl_spi2ck_default: spi2ck_default {
1955 function = "SPI2CK";
1956 groups = "SPI2CK";
1957 };
1958
1959 pinctrl_spi2cs0_default: spi2cs0_default {
1960 function = "SPI2CS0";
1961 groups = "SPI2CS0";
1962 };
1963
1964 pinctrl_spi2cs1_default: spi2cs1_default {
1965 function = "SPI2CS1";
1966 groups = "SPI2CS1";
1967 };
1968
1969 pinctrl_spi2miso_default: spi2miso_default {
1970 function = "SPI2MISO";
1971 groups = "SPI2MISO";
1972 };
1973
1974 pinctrl_spi2mosi_default: spi2mosi_default {
1975 function = "SPI2MOSI";
1976 groups = "SPI2MOSI";
1977 };
1978
1979 pinctrl_timer3_default: timer3_default {
1980 function = "TIMER3";
1981 groups = "TIMER3";
1982 };
1983
1984 pinctrl_timer4_default: timer4_default {
1985 function = "TIMER4";
1986 groups = "TIMER4";
1987 };
1988
1989 pinctrl_timer5_default: timer5_default {
1990 function = "TIMER5";
1991 groups = "TIMER5";
1992 };
1993
1994 pinctrl_timer6_default: timer6_default {
1995 function = "TIMER6";
1996 groups = "TIMER6";
1997 };
1998
1999 pinctrl_timer7_default: timer7_default {
2000 function = "TIMER7";
2001 groups = "TIMER7";
2002 };
2003
2004 pinctrl_timer8_default: timer8_default {
2005 function = "TIMER8";
2006 groups = "TIMER8";
2007 };
2008
2009 pinctrl_txd1_default: txd1_default {
2010 function = "TXD1";
2011 groups = "TXD1";
2012 };
2013
2014 pinctrl_txd2_default: txd2_default {
2015 function = "TXD2";
2016 groups = "TXD2";
2017 };
2018
2019 pinctrl_txd3_default: txd3_default {
2020 function = "TXD3";
2021 groups = "TXD3";
2022 };
2023
2024 pinctrl_txd4_default: txd4_default {
2025 function = "TXD4";
2026 groups = "TXD4";
2027 };
2028
2029 pinctrl_uart6_default: uart6_default {
2030 function = "UART6";
2031 groups = "UART6";
2032 };
2033
2034 pinctrl_usbcki_default: usbcki_default {
2035 function = "USBCKI";
2036 groups = "USBCKI";
2037 };
2038
2039 pinctrl_usb2ah_default: usb2ah_default {
2040 function = "USB2AH";
2041 groups = "USB2AH";
2042 };
2043
2044 pinctrl_usb11bhid_default: usb11bhid_default {
2045 function = "USB11BHID";
2046 groups = "USB11BHID";
2047 };
2048
2049 pinctrl_usb2bh_default: usb2bh_default {
2050 function = "USB2BH";
2051 groups = "USB2BH";
2052 };
2053
2054 pinctrl_vgabiosrom_default: vgabiosrom_default {
2055 function = "VGABIOSROM";
2056 groups = "VGABIOSROM";
2057 };
2058
2059 pinctrl_vgahs_default: vgahs_default {
2060 function = "VGAHS";
2061 groups = "VGAHS";
2062 };
2063
2064 pinctrl_vgavs_default: vgavs_default {
2065 function = "VGAVS";
2066 groups = "VGAVS";
2067 };
2068
2069 pinctrl_vpi24_default: vpi24_default {
2070 function = "VPI24";
2071 groups = "VPI24";
2072 };
2073
2074 pinctrl_vpo_default: vpo_default {
2075 function = "VPO";
2076 groups = "VPO";
2077 };
2078
2079 pinctrl_wdtrst1_default: wdtrst1_default {
2080 function = "WDTRST1";
2081 groups = "WDTRST1";
2082 };
2083
2084 pinctrl_wdtrst2_default: wdtrst2_default {
2085 function = "WDTRST2";
2086 groups = "WDTRST2";
2087 };
2088
2089 pinctrl_pcie0rc_default: pcie0rc_default {
2090 function = "PCIE0RC";
2091 groups = "PCIE0RC";
2092 };
2093
2094 pinctrl_pcie1rc_default: pcie1rc_default {
2095 function = "PCIE1RC";
2096 groups = "PCIE1RC";
2097 };
2098};