blob: f30aebfe4c627ab8574cfe3530ab24e2941e1ede [file] [log] [blame]
Tom Rini10e47792018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0
Simon Glass71606de2016-03-11 22:07:18 -07002/*
3 * Copyright (c) 2016 Google, Inc
4 *
Simon Glass71606de2016-03-11 22:07:18 -07005 * Based on code from coreboot src/soc/intel/broadwell/cpu.c
6 */
7
8#include <common.h>
9#include <dm.h>
10#include <cpu.h>
Simon Glassfc557362022-03-04 08:43:05 -070011#include <event.h>
Simon Glass97589732020-05-10 11:40:02 -060012#include <init.h>
Simon Glass0f2af882020-05-10 11:40:05 -060013#include <log.h>
Simon Glass71606de2016-03-11 22:07:18 -070014#include <asm/cpu.h>
15#include <asm/cpu_x86.h>
16#include <asm/cpu_common.h>
Simon Glass3ba929a2020-10-30 21:38:53 -060017#include <asm/global_data.h>
Simon Glass71606de2016-03-11 22:07:18 -070018#include <asm/intel_regs.h>
Simon Glass412f11b2019-04-25 21:58:50 -060019#include <asm/lpc_common.h>
Simon Glass71606de2016-03-11 22:07:18 -070020#include <asm/msr.h>
Simon Glass412f11b2019-04-25 21:58:50 -060021#include <asm/pci.h>
Simon Glass71606de2016-03-11 22:07:18 -070022#include <asm/post.h>
23#include <asm/turbo.h>
24#include <asm/arch/cpu.h>
25#include <asm/arch/pch.h>
26#include <asm/arch/rcb.h>
27
Simon Glassfc557362022-03-04 08:43:05 -070028static int broadwell_init_cpu(void *ctx, struct event *event)
Simon Glass71606de2016-03-11 22:07:18 -070029{
30 struct udevice *dev;
31 int ret;
32
33 /* Start up the LPC so we have serial */
Michal Suchanekac12a2f2022-10-12 21:57:59 +020034 ret = uclass_first_device_err(UCLASS_LPC, &dev);
Simon Glass71606de2016-03-11 22:07:18 -070035 if (ret)
36 return ret;
Simon Glass71606de2016-03-11 22:07:18 -070037 ret = cpu_set_flex_ratio_to_tdp_nominal();
38 if (ret)
39 return ret;
40
41 return 0;
42}
Simon Glass93074012023-05-04 16:50:45 -060043EVENT_SPY(EVT_DM_POST_INIT_F, broadwell_init_cpu);
Simon Glass71606de2016-03-11 22:07:18 -070044
45void set_max_freq(void)
46{
Simon Glassb12689d2019-09-25 08:56:38 -060047 msr_t msr, perf_ctl;
Simon Glass71606de2016-03-11 22:07:18 -070048
Simon Glassb12689d2019-09-25 08:56:38 -060049 if (cpu_config_tdp_levels()) {
Simon Glass71606de2016-03-11 22:07:18 -070050 /* Set to nominal TDP ratio */
51 msr = msr_read(MSR_CONFIG_TDP_NOMINAL);
52 perf_ctl.lo = (msr.lo & 0xff) << 8;
53 } else {
54 /* Platform Info bits 15:8 give max ratio */
55 msr = msr_read(MSR_PLATFORM_INFO);
56 perf_ctl.lo = msr.lo & 0xff00;
57 }
58
59 perf_ctl.hi = 0;
Simon Glass76ae0272019-09-25 08:56:35 -060060 msr_write(MSR_IA32_PERF_CTL, perf_ctl);
Simon Glass71606de2016-03-11 22:07:18 -070061
62 debug("CPU: frequency set to %d MHz\n",
Simon Glass4347d832019-09-25 08:56:37 -060063 ((perf_ctl.lo >> 8) & 0xff) * INTEL_BCLK_MHZ);
Simon Glass71606de2016-03-11 22:07:18 -070064}
65
66int arch_cpu_init(void)
67{
68 post_code(POST_CPU_INIT);
69
Simon Glass42bf3b92019-09-25 08:11:40 -060070#ifdef CONFIG_TPL
71 /* Do a mini-init if TPL has already done the full init */
72 return x86_cpu_reinit_f();
73#else
Simon Glass71606de2016-03-11 22:07:18 -070074 return x86_cpu_init_f();
Simon Glass42bf3b92019-09-25 08:11:40 -060075#endif
Simon Glass71606de2016-03-11 22:07:18 -070076}
77
Simon Glassee7c36f2017-03-28 10:27:30 -060078int checkcpu(void)
Simon Glass71606de2016-03-11 22:07:18 -070079{
Simon Glass71606de2016-03-11 22:07:18 -070080 int ret;
81
82 set_max_freq();
83
84 ret = cpu_common_init();
85 if (ret)
86 return ret;
87 gd->arch.pei_boot_mode = PEI_BOOT_NONE;
88
Simon Glassee7c36f2017-03-28 10:27:30 -060089 return 0;
90}
91
92int print_cpuinfo(void)
93{
94 char processor_name[CPU_MAX_NAME_LEN];
95 const char *name;
96
Simon Glass71606de2016-03-11 22:07:18 -070097 /* Print processor name */
98 name = cpu_get_name(processor_name);
99 printf("CPU: %s\n", name);
100
101 return 0;
102}
103
Simon Glass412f11b2019-04-25 21:58:50 -0600104void board_debug_uart_init(void)
105{
Simon Glass412f11b2019-04-25 21:58:50 -0600106 /* com1 / com2 decode range */
Simon Glassa5464582019-08-31 21:23:18 -0600107 pci_x86_write_config(PCH_DEV_LPC, LPC_IO_DEC, 1 << 4, PCI_SIZE_16);
Simon Glass412f11b2019-04-25 21:58:50 -0600108
Simon Glassa5464582019-08-31 21:23:18 -0600109 pci_x86_write_config(PCH_DEV_LPC, LPC_EN, COMA_LPC_EN, PCI_SIZE_16);
Simon Glass412f11b2019-04-25 21:58:50 -0600110}